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Oct 18th, 2017
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  1.  
  2. .ORG    0x0000                 
  3. RJMP    main               
  4.  
  5. main:
  6. LDI r16, 0xFF              
  7. OUT DDRB, r16              
  8. LDI r17, 0xFF
  9. LDI r18, 0xFF
  10.  
  11. CBI DDRC, 0
  12. SBI DDRB, 5
  13. SBI PORTB, 5
  14.  
  15. loop:
  16. SBIS PINC, 0 //skip if bit cleared, clear if bit cleared
  17.     RJMP loop
  18. SBI PortB, 5               
  19. RCALL   delay_08
  20. RCALL   delay_08
  21. RCALL   delay_08
  22.  
  23. CBI PortB, 5
  24. RCALL   delay_08
  25. RCALL   delay_08
  26. RCALL   delay_08
  27.  
  28. SBI PortB, 5               
  29. RCALL   delay_08
  30.  
  31. CBI PortB, 5
  32. RCALL   delay_08
  33.  
  34.  
  35. RJMP    loop                   
  36.  
  37. delay_05: // long delay
  38. LDI r16, 255
  39. LDI r17, 0xFF
  40. outer_loop:
  41. LDI r24, low(3037)
  42. LDI r25, high(3037)
  43.  
  44. delay_loop:
  45. ADIW    r24, 1
  46. BRNE    delay_loop
  47. DEC r16
  48. BRNE    outer_loop
  49. RET
  50.  
  51. delay_08:
  52. LDI r17, 0x00
  53. LDI r16, 81
  54.  
  55. outer_loop8:
  56. LDI r24, low(3037)
  57. LDI r25, high(3037)
  58.  
  59. delay_loop8:
  60. ADIW    r24, 1
  61. BRNE    delay_loop8
  62. DEC r16
  63. BRNE    outer_loop8
  64. RET
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