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sliq19882

µConsole R01 device tree source

sliq19882
Jul 15th, 2024 (edited)
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  1. /dts-v1/;
  2.  
  3. /memreserve/ 0x0000000042000000 0x0000000000100000;
  4. /memreserve/ 0x0000000041fc0000 0x0000000000020000;
  5. / {
  6. model = "sun20iw1p1";
  7. compatible = "allwinner,d1-h\0arm,sun20iw1p1\0allwinner,sun20iw1p1";
  8. #address-cells = <0x02>;
  9. #size-cells = <0x02>;
  10.  
  11. aliases {
  12. serial0 = "/soc@3000000/uart@2500000";
  13. serial1 = "/soc@3000000/uart@2500400";
  14. serial2 = "/soc@3000000/uart@2500800";
  15. serial3 = "/soc@3000000/uart@2500c00";
  16. serial4 = "/soc@3000000/uart@2501000";
  17. serial5 = "/soc@3000000/uart@2501400";
  18. spi0 = "/soc@3000000/spi@4025000";
  19. spi1 = "/soc@3000000/spi@4026000";
  20. twi0 = "/soc@3000000/twi@2502000";
  21. twi1 = "/soc@3000000/twi@2502400";
  22. twi2 = "/soc@3000000/twi@2502800";
  23. twi3 = "/soc@3000000/twi@2502c00";
  24. mmc2 = "/soc@3000000/sdmmc@4022000";
  25. pwm0 = "/soc@3000000/pwm0@2000c10";
  26. pwm1 = "/soc@3000000/pwm1@2000c11";
  27. pwm2 = "/soc@3000000/pwm2@2000c12";
  28. pwm3 = "/soc@3000000/pwm3@2000c13";
  29. pwm4 = "/soc@3000000/pwm4@2000c14";
  30. pwm5 = "/soc@3000000/pwm5@2000c15";
  31. pwm6 = "/soc@3000000/pwm6@2000c16";
  32. pwm7 = "/soc@3000000/pwm7@2000c17";
  33. ir0 = "/soc@3000000/s_cir@7040000";
  34. ir1 = "/soc@3000000/ir@2003000";
  35. mmc0 = "/soc@3000000/sdmmc@4020000";
  36. ve0 = "/soc@3000000/ve@1c0e000";
  37. tvd = "/soc@3000000/tvd@05c00000";
  38. tvd0 = "/soc@3000000/tvd0@05c01000";
  39. dsp0 = "/dsp0";
  40. dsp0_gpio_int = "/dsp0_gpio_int";
  41. gmac0 = "/soc@3000000/eth@4500000";
  42. };
  43.  
  44. chosen {
  45. bootargs = "console=ttyS0,115200n8 debug loglevel=7,initcall_debug=1 init=/init earlycon=sbi";
  46. stdout-path = "serial0:115200n8";
  47. linux,initrd-start = <0x42000000>;
  48. linux,initrd-end = <0x43000000>;
  49. };
  50.  
  51. cpus {
  52. #address-cells = <0x01>;
  53. #size-cells = <0x00>;
  54. timebase-frequency = <0x16e3600>;
  55.  
  56. idle-states {
  57.  
  58. cpu-sleep {
  59. compatible = "riscv,idle-state";
  60. local-timer-stop;
  61. entry-latency-us = <0x3b>;
  62. exit-latency-us = <0x3b>;
  63. min-residency-us = <0x1388>;
  64. phandle = <0x03>;
  65. };
  66. };
  67.  
  68. cpu@0 {
  69. device_type = "cpu";
  70. reg = <0x00>;
  71. status = "okay";
  72. compatible = "riscv";
  73. riscv,isa = "rv64imafdcvsu";
  74. mmu-type = "riscv,sv39";
  75. clocks = <0x01 0x87>;
  76. clock-frequency = <0x16e3600>;
  77. operating-points-v2 = <0x02>;
  78. cpu-idle-states = <0x03>;
  79. #cooling-cells = <0x02>;
  80. cpu-supply = <0x04>;
  81. phandle = <0x09>;
  82.  
  83. interrupt-controller {
  84. #interrupt-cells = <0x01>;
  85. interrupt-controller;
  86. compatible = "riscv,cpu-intc";
  87. phandle = <0x0d>;
  88. };
  89. };
  90. };
  91.  
  92. dram {
  93. device_type = "dram";
  94. compatible = "allwinner,dram";
  95. clocks = <0x01 0x02>;
  96. clock-names = "pll_ddr";
  97. };
  98.  
  99. memory@40000000 {
  100. device_type = "memory";
  101. reg = <0x00 0x40000000 0x00 0x40000000>;
  102. };
  103.  
  104. dump_reg@20000 {
  105. compatible = "allwinner,sunxi-dump-reg";
  106. reg = <0x00 0x20000 0x00 0x04>;
  107. };
  108.  
  109. cpu-opp-table {
  110. compatible = "allwinner,sun50i-operating-points";
  111. nvmem-cells = <0x05 0x06>;
  112. nvmem-cell-names = "speed\0bin";
  113. opp-shared;
  114. phandle = <0x02>;
  115.  
  116. opp@480000000 {
  117. opp-hz = <0x00 0x1c9c3800>;
  118. clock-latency-ns = <0x3b9b0>;
  119. opp-microvolt-a0 = <0xdbba0>;
  120. opp-microvolt-a1 = <0xdbba0>;
  121. opp-microvolt-b0 = <0xe7ef0>;
  122. opp-microvolt-b1 = <0xe7ef0>;
  123. opp-microvolt-c0 = <0xe7ef0>;
  124. opp-microvolt-c1 = <0xe7ef0>;
  125. opp-supported-hw = <0x07>;
  126. };
  127.  
  128. opp@600000000 {
  129. opp-hz = <0x00 0x23c34600>;
  130. clock-latency-ns = <0x3b9b0>;
  131. opp-microvolt-b0 = <0xe7ef0>;
  132. opp-microvolt-c0 = <0xe7ef0>;
  133. opp-microvolt-c1 = <0xe7ef0>;
  134. opp-supported-hw = <0x06>;
  135. };
  136.  
  137. opp@720000000 {
  138. opp-hz = <0x00 0x2aea5400>;
  139. clock-latency-ns = <0x3b9b0>;
  140. opp-microvolt-a0 = <0xe7ef0>;
  141. opp-microvolt-a1 = <0xdbba0>;
  142. opp-microvolt-b0 = <0xe7ef0>;
  143. opp-microvolt-b1 = <0xe7ef0>;
  144. opp-microvolt-c0 = <0xe7ef0>;
  145. opp-microvolt-c1 = <0xe7ef0>;
  146. opp-supported-hw = <0x07>;
  147. };
  148.  
  149. opp@816000000 {
  150. opp-hz = <0x00 0x30a32c00>;
  151. clock-latency-ns = <0x3b9b0>;
  152. opp-microvolt-a0 = <0xf4240>;
  153. opp-microvolt-a1 = <0xdbba0>;
  154. opp-microvolt-b1 = <0xe7ef0>;
  155. opp-supported-hw = <0x01>;
  156. };
  157.  
  158. opp@912000000 {
  159. opp-hz = <0x00 0x365c0400>;
  160. clock-latency-ns = <0x3b9b0>;
  161. opp-microvolt-a0 = <0x100590>;
  162. opp-microvolt-a1 = <0xdbba0>;
  163. opp-microvolt-b1 = <0xe7ef0>;
  164. opp-microvolt-c1 = <0xe7ef0>;
  165. opp-supported-hw = <0x05>;
  166. };
  167.  
  168. opp@1008000000 {
  169. opp-hz = <0x00 0x3c14dc00>;
  170. clock-latency-ns = <0x3b9b0>;
  171. opp-microvolt-a0 = <0x10c8e0>;
  172. opp-microvolt-a1 = <0xe7ef0>;
  173. opp-microvolt-b1 = <0xe7ef0>;
  174. opp-microvolt-c1 = <0xe7ef0>;
  175. opp-supported-hw = <0x05>;
  176. };
  177. };
  178.  
  179. dcxo24M_clk {
  180. #clock-cells = <0x00>;
  181. compatible = "fixed-clock";
  182. clock-frequency = <0x16e3600>;
  183. clock-output-names = "dcxo24M";
  184. phandle = <0x0b>;
  185. };
  186.  
  187. rc16m_clk {
  188. #clock-cells = <0x00>;
  189. compatible = "fixed-clock";
  190. clock-frequency = <0xf42400>;
  191. clock-accuracy = <0x11e1a300>;
  192. clock-output-names = "rc-16m";
  193. };
  194.  
  195. ext32k_clk {
  196. #clock-cells = <0x00>;
  197. compatible = "fixed-clock";
  198. clock-frequency = <0x8000>;
  199. clock-output-names = "ext-32k";
  200. };
  201.  
  202. pio-18 {
  203. compatible = "regulator-fixed";
  204. regulator-name = "pio-18";
  205. regulator-min-microvolt = <0x1b7740>;
  206. regulator-max-microvolt = <0x1b7740>;
  207. phandle = <0x1e>;
  208. };
  209.  
  210. pio-33 {
  211. compatible = "regulator-fixed";
  212. regulator-name = "pio-33";
  213. regulator-min-microvolt = <0x325aa0>;
  214. regulator-max-microvolt = <0x325aa0>;
  215. phandle = <0x1f>;
  216. };
  217.  
  218. thermal-zones {
  219.  
  220. cpu_thermal_zone {
  221. polling-delay-passive = <0x1f4>;
  222. polling-delay = <0x3e8>;
  223. thermal-sensors = <0x07 0x00>;
  224. sustainable-power = <0x4b0>;
  225.  
  226. trips {
  227.  
  228. trip-point@0 {
  229. temperature = <0x11170>;
  230. type = "passive";
  231. hysteresis = <0x00>;
  232. };
  233.  
  234. trip-point@1 {
  235. temperature = <0x15f90>;
  236. type = "passive";
  237. hysteresis = <0x00>;
  238. phandle = <0x08>;
  239. };
  240.  
  241. cpu_crit@0 {
  242. temperature = <0x1adb0>;
  243. type = "critical";
  244. hysteresis = <0x00>;
  245. };
  246. };
  247.  
  248. cooling-maps {
  249.  
  250. map0 {
  251. trip = <0x08>;
  252. cooling-device = <0x09 0xffffffff 0xffffffff>;
  253. contribution = <0x400>;
  254. };
  255. };
  256. };
  257. };
  258.  
  259. iommu@2010000 {
  260. compatible = "allwinner,sunxi-iommu";
  261. reg = <0x00 0x2010000 0x00 0x1000>;
  262. interrupts-extended = <0x0a 0x50 0x04>;
  263. interrupt-names = "iommu-irq";
  264. clocks = <0x01 0x30>;
  265. clock-names = "iommu";
  266. #iommu-cells = <0x02>;
  267. status = "okay";
  268. phandle = <0x1a>;
  269. };
  270.  
  271. soc@3000000 {
  272. #address-cells = <0x02>;
  273. #size-cells = <0x02>;
  274. compatible = "simple-bus";
  275. ranges;
  276.  
  277. sram_ctrl@3000000 {
  278. compatible = "allwinner,sram_ctrl";
  279. reg = <0x00 0x3000000 0x00 0x16c>;
  280.  
  281. soc_ver {
  282. offset = <0x24>;
  283. mask = <0x07>;
  284. shift = <0x00>;
  285. ver_a = <0x18590000>;
  286. ver_b = <0x18590002>;
  287. ver_d = <0x18590003>;
  288. };
  289.  
  290. soc_id {
  291. offset = <0x200>;
  292. mask = <0x01>;
  293. shift = <0x16>;
  294. };
  295.  
  296. soc_bin {
  297. offset = <0x00>;
  298. mask = <0x3ff>;
  299. shift = <0x00>;
  300. };
  301. };
  302.  
  303. rtc_ccu@7090000 {
  304. compatible = "allwinner,sun20iw1-rtc-ccu";
  305. device_type = "rtc-ccu";
  306. reg = <0x00 0x7090000 0x00 0x320>;
  307. #clock-cells = <0x01>;
  308. phandle = <0x0c>;
  309. };
  310.  
  311. clock@2001000 {
  312. compatible = "allwinner,sun20iw1-ccu";
  313. reg = <0x00 0x2001000 0x00 0x1000>;
  314. clocks = <0x0b 0x0c 0x03 0x0c 0x00>;
  315. clock-names = "hosc\0losc\0iosc";
  316. #clock-cells = <0x01>;
  317. #reset-cells = <0x01>;
  318. phandle = <0x01>;
  319. };
  320.  
  321. clock@7010000 {
  322. compatible = "allwinner,sun20iw1-r-ccu";
  323. reg = <0x00 0x7010000 0x00 0x240>;
  324. clocks = <0x0b 0x0c 0x03 0x0c 0x00 0x01 0x04>;
  325. clock-names = "hosc\0losc\0iosc\0pll-periph0";
  326. #clock-cells = <0x01>;
  327. #reset-cells = <0x01>;
  328. phandle = <0x15>;
  329. };
  330.  
  331. interrupt-controller@10000000 {
  332. compatible = "riscv,plic0";
  333. #address-cells = <0x02>;
  334. #interrupt-cells = <0x02>;
  335. interrupt-controller;
  336. reg = <0x00 0x10000000 0x00 0x4000000>;
  337. interrupts-extended = <0x0d 0xffffffff 0x0d 0x09>;
  338. reg-names = "control";
  339. riscv,max-priority = <0x07>;
  340. riscv,ndev = <0xc8>;
  341. phandle = <0x0a>;
  342. };
  343.  
  344. uart@2500000 {
  345. compatible = "allwinner,sun20i-uart";
  346. device_type = "uart0";
  347. reg = <0x00 0x2500000 0x00 0x400>;
  348. interrupts-extended = <0x0a 0x12 0x04>;
  349. clocks = <0x01 0x3f>;
  350. clock-names = "uart0";
  351. resets = <0x01 0x12>;
  352. sunxi,uart-fifosize = <0x40>;
  353. uart0_port = <0x00>;
  354. uart0_type = <0x02>;
  355. status = "okay";
  356. pinctrl-names = "default\0sleep";
  357. pinctrl-0 = <0x0e>;
  358. pinctrl-1 = <0x0f>;
  359. };
  360.  
  361. uart@2500400 {
  362. compatible = "allwinner,sun20i-uart";
  363. device_type = "uart1";
  364. reg = <0x00 0x2500400 0x00 0x400>;
  365. interrupts-extended = <0x0a 0x13 0x04>;
  366. sunxi,uart-fifosize = <0x100>;
  367. clocks = <0x01 0x40>;
  368. clock-names = "uart1";
  369. resets = <0x01 0x13>;
  370. uart1_port = <0x01>;
  371. uart1_type = <0x04>;
  372. status = "okay";
  373. pinctrl-names = "default\0sleep";
  374. pinctrl-0 = <0x10>;
  375. pinctrl-1 = <0x11>;
  376. };
  377.  
  378. uart@2500800 {
  379. compatible = "allwinner,sun20i-uart";
  380. device_type = "uart2";
  381. reg = <0x00 0x2500800 0x00 0x400>;
  382. interrupts-extended = <0x0a 0x14 0x04>;
  383. sunxi,uart-fifosize = <0x100>;
  384. clocks = <0x01 0x41>;
  385. clock-names = "uart2";
  386. resets = <0x01 0x14>;
  387. uart2_port = <0x02>;
  388. uart2_type = <0x04>;
  389. status = "disabled";
  390. pinctrl-names = "default\0sleep";
  391. pinctrl-0 = <0x12>;
  392. pinctrl-1 = <0x13>;
  393. };
  394.  
  395. uart@2500c00 {
  396. compatible = "allwinner,sun20iw1-dsp-uart";
  397. device_type = "uart3";
  398. reg = <0x00 0x2500c00 0x00 0x400>;
  399. interrupts-extended = <0x0a 0x15 0x04>;
  400. sunxi,uart-fifosize = <0x100>;
  401. clocks = <0x01 0x42>;
  402. clock-names = "uart3";
  403. resets = <0x01 0x15>;
  404. uart3_port = <0x03>;
  405. uart3_type = <0x04>;
  406. status = "disabled";
  407. pinctrl-names = "default\0sleep";
  408. pinctrl-0 = <0x14>;
  409. pinctrl-1 = <0x14>;
  410. };
  411.  
  412. uart@2501000 {
  413. compatible = "allwinner,sun20i-uart";
  414. device_type = "uart4";
  415. reg = <0x00 0x2501000 0x00 0x400>;
  416. interrupts-extended = <0x0a 0x16 0x04>;
  417. sunxi,uart-fifosize = <0x100>;
  418. clocks = <0x01 0x43>;
  419. clock-names = "uart4";
  420. resets = <0x01 0x16>;
  421. uart4_port = <0x04>;
  422. uart4_type = <0x02>;
  423. status = "disabled";
  424. };
  425.  
  426. uart@2501400 {
  427. compatible = "allwinner,sun20i-uart";
  428. device_type = "uart5";
  429. reg = <0x00 0x2501400 0x00 0x400>;
  430. interrupts-extended = <0x0a 0x17 0x04>;
  431. sunxi,uart-fifosize = <0x100>;
  432. clocks = <0x01 0x44>;
  433. clock-names = "uart5";
  434. resets = <0x01 0x17>;
  435. uart5_port = <0x05>;
  436. uart5_type = <0x02>;
  437. status = "disabled";
  438. };
  439.  
  440. ce@03040000 {
  441. compatible = "allwinner,sunxi-ce";
  442. device_name = "ce";
  443. reg = <0x00 0x3040000 0x00 0xa0 0x00 0x3040800 0x00 0xa0>;
  444. interrupts-extended = <0x0a 0x44 0x01 0x0a 0x45 0x01>;
  445. clock-frequency = <0x17d78400>;
  446. clocks = <0x01 0x24 0x01 0x23 0x01 0x34 0x01 0x05>;
  447. clock-names = "bus_ce\0ce_clk\0mbus_ce\0pll_periph0_2x";
  448. resets = <0x01 0x04>;
  449. status = "okay";
  450. };
  451.  
  452. s_cir@7040000 {
  453. compatible = "allwinner,s_cir";
  454. reg = <0x00 0x7040000 0x00 0x400>;
  455. interrupts-extended = <0x0a 0xa7 0x04>;
  456. clocks = <0x15 0x06 0x0b 0x15 0x05>;
  457. clock-names = "bus\0pclk\0mclk";
  458. resets = <0x15 0x03>;
  459. supply = [00];
  460. supply_vol = [00];
  461. status = "disabled";
  462. pinctrl-names = "default\0sleep";
  463. pinctrl-0 = <0x16>;
  464. pinctrl-1 = <0x17>;
  465. };
  466.  
  467. ir@2003000 {
  468. compatible = "allwinner,irtx";
  469. reg = <0x00 0x2003000 0x00 0x400>;
  470. interrupts-extended = <0x0a 0x23 0x04>;
  471. clocks = <0x01 0x52 0x0b 0x01 0x51>;
  472. clock-names = "bus\0pclk\0mclk";
  473. resets = <0x01 0x21>;
  474. status = "disabled";
  475. pinctrl-names = "default\0sleep";
  476. pinctrl-0 = <0x18>;
  477. pinctrl-1 = <0x19>;
  478. };
  479.  
  480. deinterlace@5400000 {
  481. compatible = "allwinner,sunxi-deinterlace";
  482. reg = <0x00 0x5400000 0x00 0xffff>;
  483. interrupts-extended = <0x0a 0x68 0x04>;
  484. clocks = <0x01 0x1f 0x01 0x20 0x01 0x05>;
  485. clock-names = "clk_di\0pll_periph\0clk_bus_di";
  486. resets = <0x01 0x02>;
  487. reset-names = "rst_bus_di";
  488. assigned-clocks = <0x01 0x1f>;
  489. assigned-clock-parents = <0x01 0x05>;
  490. assigned-clock-rates = <0x11e1a300>;
  491. iommus = <0x1a 0x04 0x01>;
  492. status = "okay";
  493. };
  494.  
  495. eth@4500000 {
  496. compatible = "allwinner,sunxi-gmac";
  497. reg = <0x00 0x4500000 0x00 0x10000 0x00 0x3000030 0x00 0x04>;
  498. interrupts-extended = <0x0a 0x3e 0x04>;
  499. interrupt-names = "gmacirq";
  500. clocks = <0x01 0x50 0x01 0x4f>;
  501. clock-names = "gmac\0ephy";
  502. resets = <0x01 0x20>;
  503. device_type = "gmac0";
  504. pinctrl-0 = <0x1b>;
  505. pinctrl-1 = <0x1c>;
  506. pinctrl-names = "default\0sleep";
  507. phy-mode = "rgmii";
  508. use_ephy25m = <0x01>;
  509. tx-delay = <0x03>;
  510. rx-delay = <0x00>;
  511. phy-rst = <0x1d 0x04 0x10 0x00>;
  512. gmac-power0;
  513. gmac-power1;
  514. gmac-power2;
  515. status = "disabled";
  516. };
  517.  
  518. rtc@7090000 {
  519. compatible = "allwinner,sun20iw1-rtc";
  520. device_type = "rtc";
  521. wakeup-source;
  522. interrupts-extended = <0x0a 0xa0 0x04>;
  523. reg = <0x00 0x7090000 0x00 0x320>;
  524. clocks = <0x15 0x07 0x0c 0x08 0x0c 0x06>;
  525. clock-names = "r-ahb-rtc\0rtc-spi\0rtc-1k";
  526. resets = <0x15 0x04>;
  527. gpr_cur_pos = <0x06>;
  528. phandle = <0x69>;
  529. };
  530.  
  531. dma-controller@3002000 {
  532. compatible = "allwinner,sun8i-riscv-dma";
  533. reg = <0x00 0x3002000 0x00 0x1000>;
  534. interrupts-extended = <0x0a 0x42 0x04>;
  535. clocks = <0x01 0x27 0x01 0x32>;
  536. clock-names = "bus\0mbus";
  537. resets = <0x01 0x06>;
  538. dma-channels = <0x08>;
  539. dma-requests = <0x30>;
  540. #dma-cells = <0x01>;
  541. status = "okay";
  542. phandle = <0x20>;
  543. };
  544.  
  545. timer@2050000 {
  546. compatible = "allwinner,sun4i-a10-timer";
  547. device_type = "soc_timer";
  548. reg = <0x00 0x2050000 0x00 0xa0>;
  549. interrupts-extended = <0x0a 0x4b 0x04>;
  550. clocks = <0x0b>;
  551. status = "okay";
  552. };
  553.  
  554. watchdog@6011000 {
  555. compatible = "allwinner,sun20i-wdt";
  556. reg = <0x00 0x6011000 0x00 0x20>;
  557. interrupts-extended = <0x0a 0x93 0x04>;
  558. };
  559.  
  560. mbus-comtroller@3102000 {
  561. compatible = "allwinner,sun8i-mbus";
  562. reg = <0x00 0x3102000 0x00 0x1000>;
  563. #mbus-cells = <0x01>;
  564. };
  565.  
  566. pmu {
  567. compatible = "riscv,c910_pmu";
  568. };
  569.  
  570. idle {
  571. compatible = "riscv,idle";
  572. };
  573.  
  574. pinctrl@2000000 {
  575. compatible = "allwinner,sun20iw1-pinctrl";
  576. reg = <0x00 0x2000000 0x00 0x500>;
  577. interrupts-extended = <0x0a 0x55 0x04 0x0a 0x57 0x04 0x0a 0x59 0x04 0x0a 0x5b 0x04 0x0a 0x5d 0x04 0x0a 0x5f 0x04>;
  578. device_type = "pio";
  579. clocks = <0x01 0x1a 0x0b 0x0c 0x03>;
  580. clock-names = "apb\0hosc\0losc";
  581. gpio-controller;
  582. #gpio-cells = <0x03>;
  583. interrupt-controller;
  584. #interrupt-cells = <0x03>;
  585. #size-cells = <0x00>;
  586. vcc-pf-supply = <0x1e>;
  587. vcc-pfo-supply = <0x1f>;
  588. phandle = <0x1d>;
  589.  
  590. test_pins@0 {
  591. allwinner,pins = "PB0\0PB1";
  592. allwinner,function = "test";
  593. allwinner,muxsel = <0x07>;
  594. allwinner,drive = <0x01>;
  595. allwinner,pull = <0x01>;
  596. };
  597.  
  598. test_pins@1 {
  599. pins = "PB0\0PB1";
  600. function = "io_disabled";
  601. allwinner,muxsel = <0x0f>;
  602. allwinner,drive = <0x01>;
  603. allwinner,pull = <0x01>;
  604. };
  605.  
  606. gmac@0 {
  607. pins = "PE0\0PE1\0PE2\0PE3\0PE4\0PE5\0PE6\0PE7\0PE8\0PE9\0PE10\0PE11\0PE12\0PE13\0PE14\0PE15";
  608. function = "gmac0";
  609. drive-strength = <0x0a>;
  610. muxsel = <0x08>;
  611. phandle = <0x1b>;
  612. };
  613.  
  614. gmac@1 {
  615. pins = "PE0\0PE1\0PE2\0PE3\0PE4\0PE5\0PE6\0PE7\0PE8\0PE9\0PE10\0PE11\0PE12\0PE13\0PE14\0PE15";
  616. function = "gpio_in";
  617. drive-strength = <0x0a>;
  618. phandle = <0x1c>;
  619. };
  620.  
  621. ir1@0 {
  622. pins = "PB0";
  623. function = "ir";
  624. drive-strength = <0x0a>;
  625. bias-pull-up;
  626. phandle = <0x18>;
  627. };
  628.  
  629. csi_mclk0@0 {
  630. pins = "PE3";
  631. function = "csi0";
  632. drive-strength = <0x0a>;
  633. phandle = <0x62>;
  634. };
  635.  
  636. csi_mclk0@1 {
  637. pins = "PE3";
  638. function = "gpio_in";
  639. phandle = <0x63>;
  640. };
  641.  
  642. csi0@0 {
  643. pins = "PE2\0PE0\0PE1\0PE4\0PE5\0PE6\0PE7\0PE8\0PE9\0PE10\0PE11";
  644. function = "ncsi0";
  645. drive-strength = <0x0a>;
  646. phandle = <0x64>;
  647. };
  648.  
  649. csi0@1 {
  650. pins = "PE2\0PE0\0PE1\0PE4\0PE5\0PE6\0PE7\0PE8\0PE9\0PE10\0PE11";
  651. function = "io_disabled";
  652. drive-strength = <0x0a>;
  653. phandle = <0x65>;
  654. };
  655.  
  656. lvds0@0 {
  657. pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9";
  658. function = "lvds0";
  659. drive-strength = <0x1e>;
  660. bias-disable;
  661. };
  662.  
  663. lvds0@1 {
  664. pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9";
  665. function = "io_disabled";
  666. drive-strength = <0x1e>;
  667. bias-disable;
  668. };
  669.  
  670. rgb24@0 {
  671. pins = "PB2\0PB3\0PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PB4\0PB5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11\0PB6\0PB7\0PD12\0PD13\0PD14\0PD15\0PD16\0PD17\0PD18\0PD19\0PD20\0PD21";
  672. function = "lcd0";
  673. drive-strength = <0x1e>;
  674. bias-disable;
  675. };
  676.  
  677. rgb24@1 {
  678. pins = "PB2\0PB3\0PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PB4\0PB5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11\0PB6\0PB7\0PD12\0PD13\0PD14\0PD15\0PD16\0PD17\0PD18\0PD19\0PD20\0PD21";
  679. function = "io_disabled";
  680. bias-disable;
  681. };
  682.  
  683. rgb18@0 {
  684. pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11\0PD12\0PD13\0PD14\0PD15\0PD16\0PD17\0PD18\0PD19\0PD20\0PD21";
  685. function = "lcd0";
  686. drive-strength = <0x1e>;
  687. bias-disable;
  688. };
  689.  
  690. rgb18@1 {
  691. pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11\0PD12\0PD13\0PD14\0PD15\0PD16\0PD17\0PD18\0PD19\0PD20\0PD21";
  692. function = "io_disabled";
  693. bias-disable;
  694. };
  695.  
  696. dsi2lane@0 {
  697. pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5";
  698. function = "dsi";
  699. drive-strength = <0x1e>;
  700. bias-disable;
  701. };
  702.  
  703. dsi2lane@1 {
  704. pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5";
  705. function = "io_disabled";
  706. bias-disable;
  707. };
  708.  
  709. dsi4lane@0 {
  710. pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9";
  711. function = "dsi";
  712. drive-strength = <0x1e>;
  713. bias-disable;
  714. phandle = <0x4f>;
  715. };
  716.  
  717. dsi4lane@1 {
  718. pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9";
  719. function = "io_disabled";
  720. bias-disable;
  721. phandle = <0x50>;
  722. };
  723.  
  724. sdc0@0 {
  725. allwinner,pins = "PF0\0PF1\0PF2\0PF3\0PF4\0PF5";
  726. allwinner,function = "sdc0";
  727. allwinner,muxsel = <0x02>;
  728. allwinner,drive = <0x03>;
  729. allwinner,pull = <0x01>;
  730. pins = "PF0\0PF1\0PF2\0PF3\0PF4\0PF5";
  731. function = "sdc0";
  732. drive-strength = <0x1e>;
  733. bias-pull-up;
  734. power-source = <0xce4>;
  735. phandle = <0x53>;
  736. };
  737.  
  738. sdc0@1 {
  739. pins = "PF0\0PF1\0PF2\0PF3\0PF4\0PF5";
  740. function = "sdc0";
  741. drive-strength = <0x1e>;
  742. bias-pull-up;
  743. power-source = <0x708>;
  744. phandle = <0x54>;
  745. };
  746.  
  747. sdc0@2 {
  748. pins = "PF0\0PF1\0PF2\0PF3\0PF4\0PF5";
  749. function = "gpio_in";
  750. phandle = <0x55>;
  751. };
  752.  
  753. sdc0@3 {
  754. pins = "PF2\0PF4";
  755. function = "uart0";
  756. drive-strength = <0x0a>;
  757. bias-pull-up;
  758. phandle = <0x56>;
  759. };
  760.  
  761. sdc0@4 {
  762. pins = "PF0\0PF1\0PF3\0PF5";
  763. function = "jtag";
  764. drive-strength = <0x0a>;
  765. bias-pull-up;
  766. phandle = <0x57>;
  767. };
  768.  
  769. sdc1@0 {
  770. pins = "PG0\0PG1\0PG2\0PG3\0PG4\0PG5";
  771. function = "sdc1";
  772. drive-strength = <0x1e>;
  773. bias-pull-up;
  774. phandle = <0x58>;
  775. };
  776.  
  777. sdc1@1 {
  778. pins = "PG0\0PG1\0PG2\0PG3\0PG4\0PG5";
  779. function = "gpio_in";
  780. phandle = <0x59>;
  781. };
  782.  
  783. sdc2@0 {
  784. allwinner,pins = "PC2\0PC3\0PC4\0PC5\0PC6\0PC7";
  785. allwinner,function = "sdc2";
  786. allwinner,muxsel = <0x03>;
  787. allwinner,drive = <0x03>;
  788. allwinner,pull = <0x01>;
  789. pins = "PC2\0PC3\0PC4\0PC5\0PC6\0PC7";
  790. function = "sdc2";
  791. drive-strength = <0x1e>;
  792. bias-pull-up;
  793. phandle = <0x51>;
  794. };
  795.  
  796. sdc2@1 {
  797. pins = "PC2\0PC3\0PC4\0PC5\0PC6\0PC7";
  798. function = "gpio_in";
  799. phandle = <0x52>;
  800. };
  801.  
  802. uart0_pins@0 {
  803. pins = "PB8\0PB9";
  804. function = "uart0";
  805. drive-strength = <0x0a>;
  806. bias-pull-up;
  807. phandle = <0x0e>;
  808. };
  809.  
  810. uart0_pins@1 {
  811. pins = "PB8\0PB9";
  812. function = "gpio_in";
  813. phandle = <0x0f>;
  814. };
  815.  
  816. uart1_pins@0 {
  817. pins = "PG6\0PG7\0PG8\0PG9";
  818. function = "uart1";
  819. drive-strength = <0x0a>;
  820. bias-pull-up;
  821. phandle = <0x10>;
  822. };
  823.  
  824. uart1_pins {
  825. pins = "PG6\0PG7\0PG8\0PG9";
  826. function = "gpio_in";
  827. phandle = <0x11>;
  828. };
  829.  
  830. uart2_pins@0 {
  831. pins = "PC0\0PC1";
  832. function = "uart2";
  833. drive-strength = <0x0a>;
  834. bias-pull-up;
  835. phandle = <0x12>;
  836. };
  837.  
  838. uart2_pins@1 {
  839. pins = "PC0\0PC1";
  840. function = "gpio_in";
  841. phandle = <0x13>;
  842. };
  843.  
  844. uart3_pins@0 {
  845. pins = "PD10\0PD11";
  846. function = "uart3";
  847. muxsel = <0x05>;
  848. drive-strength = <0x0a>;
  849. bias-pull-up;
  850. phandle = <0x14>;
  851. };
  852.  
  853. twi0@0 {
  854. pins = "PB10\0PB11";
  855. function = "twi0";
  856. drive-strength = <0x0a>;
  857. phandle = <0x26>;
  858. };
  859.  
  860. twi0@1 {
  861. pins = "PB10\0PB11";
  862. function = "gpio_in";
  863. phandle = <0x27>;
  864. };
  865.  
  866. twi1@0 {
  867. pins = "PB4\0PB5";
  868. function = "twi1";
  869. drive-strength = <0x0a>;
  870. phandle = <0x29>;
  871. };
  872.  
  873. twi1@1 {
  874. pins = "PB4\0PB5";
  875. function = "gpio_in";
  876. phandle = <0x2a>;
  877. };
  878.  
  879. twi2@0 {
  880. pins = "PB0\0PB1";
  881. function = "twi2";
  882. drive-strength = <0x0a>;
  883. phandle = <0x2b>;
  884. };
  885.  
  886. twi2@1 {
  887. pins = "PB0\0PB1";
  888. function = "gpio_in";
  889. phandle = <0x2c>;
  890. };
  891.  
  892. twi3@0 {
  893. pins = "PB6\0PB7";
  894. function = "twi3";
  895. drive-strength = <0x0a>;
  896. phandle = <0x2d>;
  897. };
  898.  
  899. twi3@1 {
  900. pins = "PB6\0PB7";
  901. function = "gpio_in";
  902. phandle = <0x2e>;
  903. };
  904.  
  905. dmic@0 {
  906. pins = "PE17\0PB11\0PB10\0PD17";
  907. function = "dmic";
  908. drive-strength = <0x14>;
  909. bias-disable;
  910. phandle = <0x3c>;
  911. };
  912.  
  913. dmic@1 {
  914. pins = "PE17\0PB11\0PB10\0PD17";
  915. function = "io_disabled";
  916. drive-strength = <0x14>;
  917. bias-disable;
  918. phandle = <0x3d>;
  919. };
  920.  
  921. daudio0@0 {
  922. pins = "PE17\0PE16\0PE15";
  923. function = "i2s0";
  924. drive-strength = <0x14>;
  925. bias-disable;
  926. phandle = <0x40>;
  927. };
  928.  
  929. daudio0@1 {
  930. pins = "PE14";
  931. function = "i2s0_din";
  932. drive-strength = <0x14>;
  933. bias-disable;
  934. phandle = <0x41>;
  935. };
  936.  
  937. daudio0@2 {
  938. pins = "PE13";
  939. function = "i2s0_dout";
  940. drive-strength = <0x14>;
  941. bias-disable;
  942. phandle = <0x42>;
  943. };
  944.  
  945. daudio0_sleep@0 {
  946. pins = "PE17\0PE16\0PE15\0PE14\0PE13";
  947. function = "io_disabled";
  948. drive-strength = <0x14>;
  949. bias-disable;
  950. phandle = <0x43>;
  951. };
  952.  
  953. daudio1@0 {
  954. pins = "PG11\0PG12\0PG13";
  955. function = "i2s1";
  956. drive-strength = <0x14>;
  957. bias-disable;
  958. phandle = <0x45>;
  959. };
  960.  
  961. daudio1@1 {
  962. pins = "PG14";
  963. function = "i2s1_din";
  964. drive-strength = <0x14>;
  965. bias-disable;
  966. phandle = <0x46>;
  967. };
  968.  
  969. daudio1@2 {
  970. pins = "PG15";
  971. function = "i2s1_dout";
  972. drive-strength = <0x14>;
  973. bias-disable;
  974. phandle = <0x47>;
  975. };
  976.  
  977. daudio1_sleep@0 {
  978. pins = "PG11\0PG12\0PG13\0PG14\0PG15";
  979. function = "io_disabled";
  980. drive-strength = <0x14>;
  981. bias-disable;
  982. phandle = <0x48>;
  983. };
  984.  
  985. daudio2@0 {
  986. pins = "PB7\0PB5\0PB6";
  987. function = "i2s2";
  988. drive-strength = <0x14>;
  989. bias-disable;
  990. };
  991.  
  992. daudio2@1 {
  993. pins = "PB4";
  994. function = "i2s2_dout";
  995. drive-strength = <0x14>;
  996. bias-disable;
  997. };
  998.  
  999. daudio2@2 {
  1000. pins = "PB3";
  1001. function = "i2s2_din";
  1002. drive-strength = <0x14>;
  1003. bias-disable;
  1004. };
  1005.  
  1006. daudio2_sleep@0 {
  1007. pins = "PB7\0PB5\0PB6\0PB4\0PB3";
  1008. function = "io_disabled";
  1009. drive-strength = <0x14>;
  1010. bias-disable;
  1011. };
  1012.  
  1013. spdif@0 {
  1014. pins = "PB0";
  1015. function = "spdif";
  1016. drive-strength = <0x14>;
  1017. bias-disable;
  1018. phandle = <0x4c>;
  1019. };
  1020.  
  1021. spdif_sleep@0 {
  1022. pins = "PB0";
  1023. function = "io_disabled";
  1024. drive-strength = <0x14>;
  1025. bias-disable;
  1026. phandle = <0x4d>;
  1027. };
  1028.  
  1029. spi0@0 {
  1030. pins = "PC2\0PC4\0PC5";
  1031. function = "spi0";
  1032. muxsel = <0x02>;
  1033. drive-strength = <0x0a>;
  1034. phandle = <0x21>;
  1035. };
  1036.  
  1037. spi0@1 {
  1038. pins = "PC3\0PC7\0PC6";
  1039. function = "spi0";
  1040. muxsel = <0x02>;
  1041. drive-strength = <0x0a>;
  1042. bias-pull-up;
  1043. phandle = <0x22>;
  1044. };
  1045.  
  1046. spi0@2 {
  1047. pins = "PC2\0PC3\0PC4\0PC5\0PC6\0PC7";
  1048. function = "gpio_in";
  1049. muxsel = <0x00>;
  1050. drive-strength = <0x0a>;
  1051. phandle = <0x23>;
  1052. };
  1053.  
  1054. spi1@0 {
  1055. pins = "PD11\0PD12\0PD13";
  1056. function = "spi1";
  1057. drive-strength = <0x0a>;
  1058. phandle = <0x24>;
  1059. };
  1060.  
  1061. spi1@1 {
  1062. pins = "PD10";
  1063. function = "spi1";
  1064. drive-strength = <0x0a>;
  1065. bias-pull-up;
  1066. };
  1067.  
  1068. spi1@2 {
  1069. pins = "PD11\0PD12";
  1070. function = "gpio_in";
  1071. drive-strength = <0x0a>;
  1072. phandle = <0x25>;
  1073. };
  1074.  
  1075. ledc@0 {
  1076. pins = "PC0";
  1077. function = "ledc";
  1078. drive-strength = <0x0a>;
  1079. phandle = <0x2f>;
  1080. };
  1081.  
  1082. ledc@1 {
  1083. pins = "PC0";
  1084. function = "gpio_in";
  1085. phandle = <0x30>;
  1086. };
  1087.  
  1088. pwm0@0 {
  1089. pins = "PD16";
  1090. function = "pwm0";
  1091. drive-strength = <0x0a>;
  1092. bias-pull-up;
  1093. phandle = <0x5e>;
  1094. };
  1095.  
  1096. pwm0@1 {
  1097. pins = "PD16";
  1098. function = "gpio_in";
  1099. bias-disable;
  1100. phandle = <0x5f>;
  1101. };
  1102.  
  1103. pwm2@0 {
  1104. pins = "PD18";
  1105. function = "pwm2";
  1106. drive-strength = <0x0a>;
  1107. bias-pull-up;
  1108. phandle = <0x60>;
  1109. };
  1110.  
  1111. pwm2@1 {
  1112. pins = "PD18";
  1113. function = "gpio_out";
  1114. phandle = <0x61>;
  1115. };
  1116.  
  1117. s_cir@0 {
  1118. pins = "PB12";
  1119. function = "ir";
  1120. drive-strength = <0x0a>;
  1121. bias-pull-up;
  1122. phandle = <0x16>;
  1123. };
  1124.  
  1125. s_cir@1 {
  1126. pins = "PB12";
  1127. function = "gpio_in";
  1128. phandle = <0x17>;
  1129. };
  1130.  
  1131. ir1@1 {
  1132. pins = "PB0";
  1133. function = "gpio_in";
  1134. phandle = <0x19>;
  1135. };
  1136.  
  1137. backlight_control@0 {
  1138. pins = "PD20";
  1139. function = "gpio_out";
  1140. };
  1141. };
  1142.  
  1143. spi@4025000 {
  1144. #address-cells = <0x01>;
  1145. #size-cells = <0x00>;
  1146. compatible = "allwinner,sun20i-spi";
  1147. device_type = "spi0";
  1148. reg = <0x00 0x4025000 0x00 0x300>;
  1149. interrupts-extended = <0x0a 0x1f 0x04>;
  1150. clocks = <0x01 0x04 0x01 0x4b 0x01 0x4d>;
  1151. clock-names = "pll\0mod\0bus";
  1152. resets = <0x01 0x1e>;
  1153. clock-frequency = <0x5f5e100>;
  1154. pinctrl-names = "default\0sleep";
  1155. spi0_cs_number = <0x01>;
  1156. spi0_cs_bitmap = <0x01>;
  1157. dmas = <0x20 0x16 0x20 0x16>;
  1158. dma-names = "tx\0rx";
  1159. status = "disabled";
  1160. pinctrl-0 = <0x21 0x22>;
  1161. pinctrl-1 = <0x23>;
  1162. spi_slave_mode = <0x00>;
  1163.  
  1164. spi-nand@0 {
  1165. compatible = "spi-nand";
  1166. spi-max-frequency = <0x5f5e100>;
  1167. reg = <0x00>;
  1168. spi-rx-bus-width = <0x04>;
  1169. spi-tx-bus-width = <0x04>;
  1170. status = "disabled";
  1171. };
  1172. };
  1173.  
  1174. spi@4026000 {
  1175. #address-cells = <0x01>;
  1176. #size-cells = <0x00>;
  1177. compatible = "allwinner,sun20i-spi";
  1178. reg = <0x00 0x4026000 0x00 0x1000>;
  1179. interrupts-extended = <0x0a 0x20 0x04>;
  1180. clocks = <0x01 0x04 0x01 0x4c 0x01 0x4e>;
  1181. clock-names = "pll\0mod\0bus";
  1182. resets = <0x01 0x1f>;
  1183. clock-frequency = <0x5f5e100>;
  1184. spi1_cs_number = <0x01>;
  1185. spi1_cs_bitmap = <0x01>;
  1186. dmas = <0x20 0x17 0x20 0x17>;
  1187. dma-names = "tx\0rx";
  1188. status = "disabled";
  1189. pinctrl-0 = <0x24>;
  1190. pinctrl-1 = <0x25>;
  1191. pinctrl-names = "default\0sleep";
  1192. spi_slave_mode = <0x00>;
  1193. spi_dbi_enable = <0x01>;
  1194.  
  1195. spi_board1@0 {
  1196. device_type = "spi-dbi";
  1197. compatible = "sunxi,spidbi";
  1198. spi-max-frequency = <0x5f5e100>;
  1199. reg = <0x00>;
  1200. spi-rx-bus-width = <0x04>;
  1201. spi-tx-bus-width = <0x04>;
  1202. status = "okay";
  1203. };
  1204. };
  1205.  
  1206. twi@2502000 {
  1207. #address-cells = <0x01>;
  1208. #size-cells = <0x00>;
  1209. compatible = "allwinner,sun20i-twi";
  1210. device_type = "twi0";
  1211. reg = <0x00 0x2502000 0x00 0x400>;
  1212. interrupts-extended = <0x0a 0x19 0x04>;
  1213. clocks = <0x01 0x45>;
  1214. resets = <0x01 0x18>;
  1215. clock-names = "bus";
  1216. clock-frequency = <0x61a80>;
  1217. dmas = <0x20 0x2b 0x20 0x2b>;
  1218. dma-names = "tx\0rx";
  1219. status = "okay";
  1220. pinctrl-0 = <0x26>;
  1221. pinctrl-1 = <0x27>;
  1222. pinctrl-names = "default\0sleep";
  1223.  
  1224. pmic@34 {
  1225. interrupt-controller;
  1226. #interrupt-cells = <0x01>;
  1227. compatible = "x-powers,axp221";
  1228. reg = <0x34>;
  1229. interrupt-parent = <0x1d>;
  1230. interrupts = <0x04 0x09 0x08>;
  1231.  
  1232. regulators {
  1233. x-powers,dcdc-freq = <0xbb8>;
  1234.  
  1235. aldo1 {
  1236. regulator-always-on;
  1237. regulator-min-microvolt = <0x325aa0>;
  1238. regulator-max-microvolt = <0x325aa0>;
  1239. regulator-name = "audio-vdd";
  1240. };
  1241.  
  1242. aldo2 {
  1243. regulator-always-on;
  1244. regulator-min-microvolt = <0x325aa0>;
  1245. regulator-max-microvolt = <0x325aa0>;
  1246. regulator-name = "display-vcc";
  1247. };
  1248.  
  1249. aldo3 {
  1250. regulator-always-on;
  1251. regulator-min-microvolt = <0x1b7740>;
  1252. regulator-max-microvolt = <0x1b7740>;
  1253. regulator-name = "wifi-vdd";
  1254. phandle = <0x5b>;
  1255. };
  1256.  
  1257. dldo1 {
  1258. regulator-always-on;
  1259. regulator-min-microvolt = <0x325aa0>;
  1260. regulator-max-microvolt = <0x325aa0>;
  1261. regulator-name = "wifi-vcc1";
  1262. phandle = <0x5a>;
  1263. };
  1264.  
  1265. dldo2 {
  1266. regulator-always-on;
  1267. regulator-min-microvolt = <0x325aa0>;
  1268. regulator-max-microvolt = <0x325aa0>;
  1269. regulator-name = "dldo2";
  1270. };
  1271.  
  1272. dldo3 {
  1273. regulator-always-on;
  1274. regulator-min-microvolt = <0x325aa0>;
  1275. regulator-max-microvolt = <0x325aa0>;
  1276. regulator-name = "dldo3";
  1277. };
  1278.  
  1279. dldo4 {
  1280. regulator-always-on;
  1281. regulator-min-microvolt = <0x325aa0>;
  1282. regulator-max-microvolt = <0x325aa0>;
  1283. regulator-name = "dldo4";
  1284. };
  1285.  
  1286. eldo1 {
  1287. regulator-always-on;
  1288. regulator-min-microvolt = <0x325aa0>;
  1289. regulator-max-microvolt = <0x325aa0>;
  1290. regulator-name = "wifi-vcc2";
  1291. };
  1292.  
  1293. eldo2 {
  1294. regulator-always-on;
  1295. regulator-min-microvolt = <0x325aa0>;
  1296. regulator-max-microvolt = <0x325aa0>;
  1297. regulator-name = "wifi-vcc3";
  1298. };
  1299.  
  1300. eldo3 {
  1301. regulator-always-on;
  1302. regulator-min-microvolt = <0x325aa0>;
  1303. regulator-max-microvolt = <0x325aa0>;
  1304. regulator-name = "wifi-vcc4";
  1305. };
  1306. };
  1307.  
  1308. battery-power-supply {
  1309. compatible = "x-powers,axp221-battery-power-supply";
  1310. monitored-battery = <0x28>;
  1311. };
  1312.  
  1313. ac_power_supply {
  1314. compatible = "x-powers,axp221-ac-power-supply";
  1315. };
  1316. };
  1317. };
  1318.  
  1319. twi@2502400 {
  1320. #address-cells = <0x01>;
  1321. #size-cells = <0x00>;
  1322. compatible = "allwinner,sun20i-twi";
  1323. device_type = "twi1";
  1324. reg = <0x00 0x2502400 0x00 0x400>;
  1325. interrupts-extended = <0x0a 0x1a 0x04>;
  1326. clocks = <0x01 0x46>;
  1327. resets = <0x01 0x19>;
  1328. clock-names = "bus";
  1329. clock-frequency = <0x61a80>;
  1330. dmas = <0x20 0x2c 0x20 0x2c>;
  1331. dma-names = "tx\0rx";
  1332. status = "disabled";
  1333. pinctrl-0 = <0x29>;
  1334. pinctrl-1 = <0x2a>;
  1335. pinctrl-names = "default\0sleep";
  1336. };
  1337.  
  1338. twi@2502800 {
  1339. #address-cells = <0x01>;
  1340. #size-cells = <0x00>;
  1341. compatible = "allwinner,sun20i-twi";
  1342. device_type = "twi2";
  1343. reg = <0x00 0x2502800 0x00 0x400>;
  1344. interrupts-extended = <0x0a 0x1b 0x04>;
  1345. clocks = <0x01 0x47>;
  1346. resets = <0x01 0x1a>;
  1347. clock-names = "bus";
  1348. clock-frequency = <0x61a80>;
  1349. dmas = <0x20 0x2d 0x20 0x2d>;
  1350. dma-names = "tx\0rx";
  1351. status = "disabled";
  1352. pinctrl-0 = <0x2b>;
  1353. pinctrl-1 = <0x2c>;
  1354. pinctrl-names = "default\0sleep";
  1355.  
  1356. gpio@38 {
  1357. compatible = "nxp,pcf8574";
  1358. reg = <0x38>;
  1359. gpio_base = <0x7e4>;
  1360. gpio-controller;
  1361. #gpio-cells = <0x02>;
  1362. interrupt-controller;
  1363. #interrupt-cells = <0x02>;
  1364. interrupt-parent = <0x1d>;
  1365. interrupts = <0x01 0x02 0x02>;
  1366. status = "okay";
  1367. };
  1368.  
  1369. ctp@14 {
  1370. compatible = "allwinner,goodix";
  1371. device_type = "ctp";
  1372. reg = <0x14>;
  1373. status = "disabled";
  1374. ctp_name = "gt9xxnew_ts";
  1375. ctp_twi_id = <0x02>;
  1376. ctp_twi_addr = <0x14>;
  1377. ctp_screen_max_x = <0x320>;
  1378. ctp_screen_max_y = <0x500>;
  1379. ctp_revert_x_flag = <0x00>;
  1380. ctp_revert_y_flag = <0x01>;
  1381. ctp_exchange_x_y_flag = <0x00>;
  1382. ctp_int_port = <0x1d 0x06 0x0e 0x00>;
  1383. ctp_wakeup = <0x1d 0x06 0x0f 0x00>;
  1384. };
  1385. };
  1386.  
  1387. twi@2502c00 {
  1388. #address-cells = <0x01>;
  1389. #size-cells = <0x00>;
  1390. compatible = "allwinner,sun20i-twi";
  1391. device_type = "twi3";
  1392. reg = <0x00 0x2502c00 0x00 0x400>;
  1393. interrupts-extended = <0x0a 0x1c 0x04>;
  1394. clocks = <0x01 0x48>;
  1395. resets = <0x01 0x1b>;
  1396. clock-names = "bus";
  1397. clock-frequency = <0x61a80>;
  1398. dmas = <0x20 0x2e 0x20 0x2e>;
  1399. dma-names = "tx\0rx";
  1400. status = "disabled";
  1401. pinctrl-0 = <0x2d>;
  1402. pinctrl-1 = <0x2e>;
  1403. pinctrl-names = "default\0sleep";
  1404. };
  1405.  
  1406. ledc@2008000 {
  1407. #address-cells = <0x01>;
  1408. #size-cells = <0x00>;
  1409. compatible = "allwinner,sunxi-leds";
  1410. reg = <0x00 0x2008000 0x00 0x400>;
  1411. interrupts-extended = <0x0a 0x24 0x04>;
  1412. interrupt-names = "ledcirq";
  1413. clocks = <0x01 0x7d 0x01 0x7e>;
  1414. clock-names = "clk_ledc\0clk_cpuapb";
  1415. dmas = <0x20 0x2a 0x20 0x2a>;
  1416. dma-names = "rx\0tx";
  1417. resets = <0x01 0x3d>;
  1418. reset-names = "ledc_reset";
  1419. status = "disabled";
  1420. pinctrl-names = "default\0sleep";
  1421. pinctrl-0 = <0x2f>;
  1422. pinctrl-1 = <0x30>;
  1423. led_count = <0x0c>;
  1424. output_mode = "GRB";
  1425. reset_ns = <0x54>;
  1426. t1h_ns = <0x320>;
  1427. t1l_ns = <0x140>;
  1428. t0h_ns = <0x12c>;
  1429. t0l_ns = <0x320>;
  1430. wait_time0_ns = <0x54>;
  1431. wait_time1_ns = <0x54>;
  1432. wait_data_time_ns = <0x927c0>;
  1433. };
  1434.  
  1435. pwm@2000c00 {
  1436. #pwm-cells = <0x03>;
  1437. compatible = "allwinner,sunxi-pwm";
  1438. reg = <0x00 0x2000c00 0x00 0x3ff>;
  1439. clocks = <0x01 0x2f>;
  1440. resets = <0x01 0x0d>;
  1441. pwm-number = <0x08>;
  1442. pwm-base = <0x00>;
  1443. sunxi-pwms = <0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38>;
  1444. phandle = <0x6a>;
  1445. };
  1446.  
  1447. keyboard@2009800 {
  1448. compatible = "allwinner,keyboard_1350mv";
  1449. reg = <0x00 0x2009800 0x00 0x400>;
  1450. interrupts-extended = <0x0a 0x4d 0x01>;
  1451. clocks = <0x01 0x6b>;
  1452. resets = <0x01 0x31>;
  1453. key_cnt = <0x05>;
  1454. key0 = <0xd2 0x160>;
  1455. key1 = <0x19a 0x72>;
  1456. key2 = <0x24e 0x8b>;
  1457. key3 = <0x2ee 0x1c>;
  1458. key4 = <0x370 0xac>;
  1459. status = "okay";
  1460. wakeup-source;
  1461. };
  1462.  
  1463. sid@3006000 {
  1464. compatible = "allwinner,sun20iw1p1-sid\0allwinner,sunxi-sid";
  1465. reg = <0x00 0x3006000 0x00 0x1000>;
  1466. #address-cells = <0x01>;
  1467. #size-cells = <0x01>;
  1468.  
  1469. chipid {
  1470. reg = <0x00 0x00>;
  1471. offset = <0x200>;
  1472. size = <0x10>;
  1473. };
  1474.  
  1475. oem {
  1476. reg = <0x00 0x00>;
  1477. offset = <0x238>;
  1478. size = <0x08>;
  1479. };
  1480.  
  1481. secure_status {
  1482. reg = <0x00 0x00>;
  1483. offset = <0x210>;
  1484. size = <0x04>;
  1485. };
  1486.  
  1487. speedbin@00 {
  1488. reg = <0x00 0x04>;
  1489. phandle = <0x05>;
  1490. };
  1491.  
  1492. cpubin@28 {
  1493. reg = <0x28 0x04>;
  1494. phandle = <0x06>;
  1495. };
  1496.  
  1497. calib@14 {
  1498. reg = <0x14 0x08>;
  1499. phandle = <0x39>;
  1500. };
  1501. };
  1502.  
  1503. gpadc@2009000 {
  1504. compatible = "allwinner,sunxi-gpadc";
  1505. reg = <0x00 0x2009000 0x00 0x400>;
  1506. interrupts-extended = <0x0a 0x49 0x04>;
  1507. clocks = <0x01 0x53>;
  1508. clock-names = "bus";
  1509. resets = <0x01 0x22>;
  1510. status = "disabled";
  1511. channel_num = <0x02>;
  1512. channel_select = <0x03>;
  1513. channel_data_select = <0x03>;
  1514. channel_compare_select = <0x03>;
  1515. channel_cld_select = <0x03>;
  1516. channel_chd_select = <0x03>;
  1517. channel0_compare_lowdata = <0x19f0a0>;
  1518. channel0_compare_higdata = <0x124f80>;
  1519. channel1_compare_lowdata = <0x704e0>;
  1520. channel1_compare_higdata = <0x124f80>;
  1521. };
  1522.  
  1523. ths@02009400 {
  1524. compatible = "allwinner,sun20iw1p1-ths";
  1525. reg = <0x00 0x2009400 0x00 0x400>;
  1526. clocks = <0x01 0x54>;
  1527. clock-names = "bus";
  1528. resets = <0x01 0x23>;
  1529. nvmem-cells = <0x39>;
  1530. nvmem-cell-names = "calibration";
  1531. #thermal-sensor-cells = <0x01>;
  1532. phandle = <0x07>;
  1533. };
  1534.  
  1535. tpadc@2009c00 {
  1536. compatible = "allwinner,tp_key";
  1537. reg = <0x00 0x2009c00 0x00 0x400>;
  1538. interrupts-extended = <0x0a 0x4e 0x04>;
  1539. clocks = <0x01 0x82 0x01 0x83>;
  1540. clock-names = "mod\0bus";
  1541. clock-frequency = <0xf4240>;
  1542. resets = <0x01 0x3f>;
  1543. status = "disabled";
  1544. };
  1545.  
  1546. rtp@2009c00 {
  1547. compatible = "allwinner,sun8i-ts";
  1548. reg = <0x00 0x2009c00 0x00 0x400>;
  1549. clocks = <0x01 0x82 0x01 0x83>;
  1550. clock-names = "mod\0bus";
  1551. clock-frequency = <0xf4240>;
  1552. resets = <0x01 0x3f>;
  1553. interrupts-extended = <0x0a 0x4e 0x04>;
  1554. allwinner,tp-sensitive-adjust = <0x0f>;
  1555. allwinner,filter-type = <0x01>;
  1556. allwinner,ts-attached;
  1557. status = "disabled";
  1558. };
  1559.  
  1560. codec@2030000 {
  1561. #sound-dai-cells = <0x00>;
  1562. compatible = "allwinner,sunxi-internal-codec";
  1563. reg = <0x00 0x2030000 0x00 0x34c>;
  1564. clocks = <0x01 0x0f 0x01 0x14 0x01 0x61 0x01 0x62 0x01 0x63>;
  1565. clock-names = "pll_audio0\0pll_audio1_div5\0audio_clk_dac\0audio_clk_adc\0audio_clk_bus";
  1566. resets = <0x01 0x29>;
  1567. rx_sync_en = <0x00>;
  1568. device_type = "codec";
  1569. status = "okay";
  1570. mic1gain = <0x13>;
  1571. mic2gain = <0x13>;
  1572. mic3gain = <0x13>;
  1573. adcdrc_cfg = <0x00>;
  1574. adchpf_cfg = <0x01>;
  1575. dacdrc_cfg = <0x00>;
  1576. dachpf_cfg = <0x00>;
  1577. digital_vol = <0x00>;
  1578. lineout_vol = <0x1a>;
  1579. headphonegain = <0x03>;
  1580. pa_level = <0x01>;
  1581. pa_pwr_level = <0x01>;
  1582. pa_msleep_time = <0x78>;
  1583. gpio-spk = <0x1d 0x04 0x01 0x00>;
  1584. gpio-spk-pwr = <0x1d 0x01 0x02 0x00>;
  1585. phandle = <0x3a>;
  1586. };
  1587.  
  1588. dummy_cpudai@203034c {
  1589. compatible = "allwinner,sunxi-dummy-cpudai";
  1590. reg = <0x00 0x203034c 0x00 0x04>;
  1591. tx_fifo_size = <0x80>;
  1592. rx_fifo_size = <0x100>;
  1593. dac_txdata = <0x2030020>;
  1594. adc_txdata = <0x2030040>;
  1595. playback_cma = <0x80>;
  1596. capture_cma = <0x100>;
  1597. device_type = "cpudai";
  1598. dmas = <0x20 0x07 0x20 0x07>;
  1599. dma-names = "tx\0rx";
  1600. status = "okay";
  1601. phandle = <0x3b>;
  1602. };
  1603.  
  1604. sound@2030340 {
  1605. compatible = "allwinner,sunxi-codec-machine";
  1606. reg = <0x00 0x2030340 0x00 0x04>;
  1607. interrupts-extended = <0x0a 0x29 0x04>;
  1608. sunxi,audio-codec = <0x3a>;
  1609. sunxi,cpudai-controller = <0x3b>;
  1610. device_type = "sndcodec";
  1611. status = "okay";
  1612. hp_detect_case = <0x01>;
  1613. jack_enable = <0x01>;
  1614. };
  1615.  
  1616. rpaf-dsp@203034c {
  1617. compatible = "allwinner,rpaf-dsp0";
  1618. device_type = "sunxi_rpaf_dsp0";
  1619. dsp_id = <0x00>;
  1620. status = "okay";
  1621. };
  1622.  
  1623. dmic@2031000 {
  1624. #sound-dai-cells = <0x00>;
  1625. compatible = "allwinner,sunxi-dmic";
  1626. reg = <0x00 0x2031000 0x00 0x50>;
  1627. clocks = <0x01 0x0f 0x01 0x5f 0x01 0x60>;
  1628. clock-names = "pll_audio\0dmic\0dmic_bus";
  1629. resets = <0x01 0x28>;
  1630. dmas = <0x20 0x08>;
  1631. dma-names = "rx";
  1632. interrupts-extended = <0x0a 0x28 0x04>;
  1633. clk_parent = <0x01>;
  1634. capture_cma = <0x100>;
  1635. data_vol = <0xb0>;
  1636. rx_chmap = <0x76543210>;
  1637. rx_sync_en = <0x00>;
  1638. device_type = "dmic";
  1639. status = "disabled";
  1640. pinctrl-names = "default\0sleep";
  1641. pinctrl-0 = <0x3c>;
  1642. pinctrl-1 = <0x3d>;
  1643. phandle = <0x3e>;
  1644. };
  1645.  
  1646. sound@2031050 {
  1647. #sound-dai-cells = <0x00>;
  1648. compatible = "dmic-codec";
  1649. reg = <0x00 0x2031050 0x00 0x04>;
  1650. num-channels = <0x08>;
  1651. status = "disabled";
  1652. phandle = <0x3f>;
  1653. };
  1654.  
  1655. sounddmic@2031060 {
  1656. reg = <0x00 0x2031060 0x00 0x04>;
  1657. compatible = "sunxi,simple-audio-card";
  1658. simple-audio-card,name = "snddmic";
  1659. simple-audio-card,capture_only;
  1660. status = "disabled";
  1661.  
  1662. simple-audio-card,cpu {
  1663. sound-dai = <0x3e>;
  1664. };
  1665.  
  1666. simple-audio-card,codec {
  1667. sound-dai = <0x3f>;
  1668. };
  1669. };
  1670.  
  1671. daudio@2032000 {
  1672. #sound-dai-cells = <0x00>;
  1673. compatible = "allwinner,sunxi-daudio";
  1674. reg = <0x00 0x2032000 0x00 0xa0>;
  1675. clocks = <0x01 0x0f 0x01 0x55 0x01 0x59>;
  1676. clock-names = "pll_audio\0i2s0\0i2s0_bus";
  1677. resets = <0x01 0x24>;
  1678. dmas = <0x20 0x03 0x20 0x03>;
  1679. dma-names = "tx\0rx";
  1680. interrupts-extended = <0x0a 0x2a 0x04>;
  1681. sign_extend = <0x00>;
  1682. tx_data_mode = <0x00>;
  1683. rx_data_mode = <0x00>;
  1684. msb_lsb_first = <0x00>;
  1685. pcm_lrck_period = <0x80>;
  1686. slot_width_select = <0x20>;
  1687. frametype = <0x00>;
  1688. tdm_config = <0x01>;
  1689. tdm_num = <0x00>;
  1690. mclk_div = <0x01>;
  1691. clk_parent = <0x01>;
  1692. capture_cma = <0x80>;
  1693. playback_cma = <0x80>;
  1694. tx_num = <0x04>;
  1695. tx_chmap1 = <0x76543210>;
  1696. tx_chmap0 = <0xfedcba98>;
  1697. rx_num = <0x04>;
  1698. rx_chmap3 = <0x3020100>;
  1699. rx_chmap2 = <0x7060504>;
  1700. rx_chmap1 = <0xb0a0908>;
  1701. rx_chmap0 = <0xf0e0d0c>;
  1702. asrc_function_en = <0x00>;
  1703. rx_sync_en = <0x00>;
  1704. device_type = "daudio0";
  1705. status = "disabled";
  1706. pinctrl-names = "default\0sleep";
  1707. pinctrl-0 = <0x40 0x41 0x42>;
  1708. pinctrl-1 = <0x43>;
  1709. pinctrl_used = <0x00>;
  1710. phandle = <0x44>;
  1711. };
  1712.  
  1713. sounddaudio0@20320a0 {
  1714. reg = <0x00 0x20320a0 0x00 0x04>;
  1715. compatible = "sunxi,simple-audio-card";
  1716. simple-audio-card,name = "snddaudio0";
  1717. simple-audio-card,format = "i2s";
  1718. status = "disabled";
  1719.  
  1720. simple-audio-card,cpu {
  1721. sound-dai = <0x44>;
  1722. };
  1723.  
  1724. simple-audio-card,codec {
  1725. };
  1726. };
  1727.  
  1728. daudio@2033000 {
  1729. #sound-dai-cells = <0x00>;
  1730. compatible = "allwinner,sunxi-daudio";
  1731. reg = <0x00 0x2033000 0x00 0xa0>;
  1732. clocks = <0x01 0x0f 0x01 0x56 0x01 0x5a>;
  1733. clock-names = "pll_audio\0i2s1\0i2s1_bus";
  1734. resets = <0x01 0x25>;
  1735. dmas = <0x20 0x04 0x20 0x04>;
  1736. dma-names = "tx\0rx";
  1737. interrupts-extended = <0x0a 0x2b 0x04>;
  1738. sign_extend = <0x00>;
  1739. tx_data_mode = <0x00>;
  1740. rx_data_mode = <0x00>;
  1741. msb_lsb_first = <0x00>;
  1742. pcm_lrck_period = <0x80>;
  1743. slot_width_select = <0x20>;
  1744. frametype = <0x00>;
  1745. tdm_config = <0x01>;
  1746. tdm_num = <0x01>;
  1747. mclk_div = <0x01>;
  1748. clk_parent = <0x01>;
  1749. capture_cma = <0x80>;
  1750. playback_cma = <0x80>;
  1751. tx_num = <0x04>;
  1752. tx_chmap1 = <0x76543210>;
  1753. tx_chmap0 = <0xfedcba98>;
  1754. rx_num = <0x04>;
  1755. rx_chmap3 = <0x3020100>;
  1756. rx_chmap2 = <0x7060504>;
  1757. rx_chmap1 = <0xb0a0908>;
  1758. rx_chmap0 = <0xf0e0d0c>;
  1759. asrc_function_en = <0x00>;
  1760. rx_sync_en = <0x00>;
  1761. device_type = "daudio1";
  1762. status = "disabled";
  1763. pinctrl-names = "default\0sleep";
  1764. pinctrl-0 = <0x45 0x46 0x47>;
  1765. pinctrl-1 = <0x48>;
  1766. pinctrl_used = <0x00>;
  1767. phandle = <0x49>;
  1768. };
  1769.  
  1770. sounddaudio1@20330a0 {
  1771. reg = <0x00 0x20330a0 0x00 0x04>;
  1772. compatible = "sunxi,simple-audio-card";
  1773. simple-audio-card,name = "snddaudio1";
  1774. simple-audio-card,format = "i2s";
  1775. status = "disabled";
  1776.  
  1777. simple-audio-card,cpu {
  1778. sound-dai = <0x49>;
  1779. };
  1780.  
  1781. simple-audio-card,codec {
  1782. };
  1783. };
  1784.  
  1785. daudio@2034000 {
  1786. #sound-dai-cells = <0x00>;
  1787. compatible = "allwinner,sunxi-daudio";
  1788. reg = <0x00 0x2034000 0x00 0xa0>;
  1789. clocks = <0x01 0x0f 0x01 0x57 0x01 0x5b 0x01 0x11 0x01 0x58>;
  1790. resets = <0x01 0x26>;
  1791. dmas = <0x20 0x05 0x20 0x05>;
  1792. dma-names = "tx\0rx";
  1793. interrupts-extended = <0x0a 0x2c 0x04>;
  1794. sign_extend = <0x00>;
  1795. tx_data_mode = <0x00>;
  1796. rx_data_mode = <0x00>;
  1797. msb_lsb_first = <0x00>;
  1798. pcm_lrck_period = <0x20>;
  1799. slot_width_select = <0x20>;
  1800. frametype = <0x00>;
  1801. tdm_config = <0x01>;
  1802. tdm_num = <0x02>;
  1803. mclk_div = <0x00>;
  1804. clk_parent = <0x01>;
  1805. capture_cma = <0x80>;
  1806. playback_cma = <0x80>;
  1807. tx_num = <0x04>;
  1808. tx_chmap1 = <0x76543210>;
  1809. tx_chmap0 = <0xfedcba98>;
  1810. rx_num = <0x04>;
  1811. rx_chmap3 = <0x3020100>;
  1812. rx_chmap2 = <0x7060504>;
  1813. rx_chmap1 = <0xb0a0908>;
  1814. rx_chmap0 = <0xf0e0d0c>;
  1815. asrc_function_en = <0x00>;
  1816. rx_sync_en = <0x00>;
  1817. device_type = "daudio2";
  1818. status = "okay";
  1819. pinctrl-names = "default\0sleep";
  1820. pinctrl-0;
  1821. pinctrl-1;
  1822. pinctrl_used = <0x00>;
  1823. daudio_type = <0x01>;
  1824. phandle = <0x4a>;
  1825. };
  1826.  
  1827. sounddaudio2@20340a0 {
  1828. reg = <0x00 0x20340a0 0x00 0x04>;
  1829. compatible = "sunxi,simple-audio-card";
  1830. simple-audio-card,name = "sndhdmi";
  1831. simple-audio-card,format = "i2s";
  1832. status = "okay";
  1833.  
  1834. simple-audio-card,cpu {
  1835. sound-dai = <0x4a>;
  1836. };
  1837.  
  1838. simple-audio-card,codec {
  1839. sound-dai = <0x4b>;
  1840. };
  1841. };
  1842.  
  1843. hdmiaudio@20340a4 {
  1844. #sound-dai-cells = <0x00>;
  1845. reg = <0x00 0x20340a4 0x00 0x04>;
  1846. compatible = "allwinner,sunxi-hdmiaudio";
  1847. status = "okay";
  1848. phandle = <0x4b>;
  1849. };
  1850.  
  1851. spdif@2036000 {
  1852. #sound-dai-cells = <0x00>;
  1853. compatible = "allwinner,sunxi-spdif";
  1854. reg = <0x00 0x2036000 0x00 0x58>;
  1855. clocks = <0x01 0x11 0x01 0x5c 0x01 0x5e 0x01 0x12 0x01 0x14 0x01 0x04 0x01 0x5d>;
  1856. clock-names = "pll_audio0\0spdif\0spdif_bus\0pll_audio1\0pll_audio1_div5\0pll_periph\0spdif_rx";
  1857. resets = <0x01 0x27>;
  1858. dmas = <0x20 0x02 0x20 0x02>;
  1859. dma-names = "tx\0rx";
  1860. interrupts-extended = <0x0a 0x29 0x04>;
  1861. clk_parent = <0x01>;
  1862. playback_cma = <0x80>;
  1863. capture_cma = <0x80>;
  1864. rx_sync_en = <0x00>;
  1865. device_type = "spdif";
  1866. status = "disabled";
  1867. pinctrl-names = "default\0sleep";
  1868. pinctrl-0 = <0x4c>;
  1869. pinctrl-1 = <0x4d>;
  1870. phandle = <0x4e>;
  1871. };
  1872.  
  1873. soundspdif@2036040 {
  1874. reg = <0x00 0x2036040 0x00 0x04>;
  1875. compatible = "sunxi,simple-audio-card";
  1876. simple-audio-card,name = "sndspdif";
  1877. status = "disabled";
  1878.  
  1879. simple-audio-card,cpu {
  1880. sound-dai = <0x4e>;
  1881. };
  1882.  
  1883. simple-audio-card,codec {
  1884. };
  1885. };
  1886.  
  1887. g2d@5410000 {
  1888. compatible = "allwinner,sunxi-g2d";
  1889. reg = <0x00 0x5410000 0x00 0x3ffff>;
  1890. interrupts-extended = <0x0a 0x69 0x04>;
  1891. clocks = <0x01 0x22 0x01 0x21 0x01 0x37>;
  1892. clock-names = "bus\0g2d\0mbus_g2d";
  1893. resets = <0x01 0x03>;
  1894. iommus = <0x1a 0x03 0x01>;
  1895. status = "okay";
  1896. };
  1897.  
  1898. disp@5000000 {
  1899. compatible = "allwinner,sunxi-disp";
  1900. reg = <0x00 0x5000000 0x00 0x3fffff 0x00 0x5460000 0x00 0xfff 0x00 0x5461000 0x00 0xfff 0x00 0x5470000 0x00 0xfff 0x00 0x5450000 0x00 0x1fff>;
  1901. interrupts-extended = <0x0a 0x6a 0x04 0x0a 0x6b 0x04 0x0a 0x6c 0x04>;
  1902. clocks = <0x01 0x1d 0x01 0x1d 0x01 0x1e 0x01 0x1e 0x01 0x6c 0x01 0x6c 0x01 0x71 0x01 0x72 0x01 0x73 0x01 0x75 0x01 0x74 0x01 0x76 0x01 0x71 0x01 0x72>;
  1903. clock-names = "clk_de0\0clk_de1\0clk_bus_de0\0clk_bus_de1\0clk_bus_dpss_top0\0clk_bus_dpss_top1\0clk_mipi_dsi0\0clk_bus_mipi_dsi0\0clk_tcon0\0clk_tcon1\0clk_bus_tcon0\0clk_bus_tcon1\0clk_mipi_dsi0\0clk_bus_mipi_dsi0";
  1904. resets = <0x01 0x01 0x01 0x01 0x01 0x32 0x01 0x32 0x01 0x35 0x01 0x36 0x01 0x37 0x01 0x38>;
  1905. reset-names = "rst_bus_de0\0rst_bus_de1\0rst_bus_dpss_top0\0rst_bus_dpss_top1\0rst_bus_mipi_dsi0\0rst_bus_tcon0\0rst_bus_tcon1\0rst_bus_lvds0";
  1906. assigned-clocks = <0x01 0x1d 0x01 0x71 0x01 0x73 0x01 0x75>;
  1907. assigned-clock-parents = <0x01 0x05 0x01 0x04 0x01 0x0a 0x01 0x0d>;
  1908. assigned-clock-rates = <0x11e1a300 0x8f0d180 0x00 0x00>;
  1909. boot_disp = <0x00>;
  1910. boot_disp1 = <0x00>;
  1911. boot_disp2 = <0x00>;
  1912. fb_base = <0x00>;
  1913. iommus = <0x1a 0x02 0x00>;
  1914. status = "okay";
  1915. disp_init_enable = <0x01>;
  1916. disp_mode = <0x00>;
  1917. screen0_output_type = <0x01>;
  1918. screen0_output_mode = <0x04>;
  1919. screen1_output_type = <0x03>;
  1920. screen1_output_mode = <0x0a>;
  1921. screen1_output_format = <0x00>;
  1922. screen1_output_bits = <0x00>;
  1923. screen1_output_eotf = <0x04>;
  1924. screen1_output_cs = <0x101>;
  1925. screen1_output_dvi_hdmi = <0x02>;
  1926. screen1_output_range = <0x02>;
  1927. screen1_output_scan = <0x00>;
  1928. screen1_output_aspect_ratio = <0x08>;
  1929. dev0_output_type = <0x01>;
  1930. dev0_output_mode = <0x04>;
  1931. dev0_screen_id = <0x00>;
  1932. dev0_do_hpd = <0x00>;
  1933. dev1_output_type = <0x04>;
  1934. dev1_output_mode = <0x0a>;
  1935. dev1_screen_id = <0x01>;
  1936. dev1_do_hpd = <0x01>;
  1937. def_output_dev = <0x00>;
  1938. hdmi_mode_check = <0x01>;
  1939. fb0_format = <0x00>;
  1940. fb0_width = <0x00>;
  1941. fb0_height = <0x00>;
  1942. fb1_format = <0x00>;
  1943. fb1_width = <0x00>;
  1944. fb1_height = <0x00>;
  1945. chn_cfg_mode = <0x01>;
  1946. disp_para_zone = <0x01>;
  1947. };
  1948.  
  1949. ve@1c0e000 {
  1950. compatible = "allwinner,sunxi-cedar-ve";
  1951. reg = <0x00 0x1c0e000 0x00 0x1000 0x00 0x3000000 0x00 0x10 0x00 0x3001000 0x00 0x1000>;
  1952. interrupts-extended = <0x0a 0x52 0x04>;
  1953. clocks = <0x01 0x26 0x01 0x25 0x01 0x33>;
  1954. clock-names = "bus_ve\0ve\0mbus_ve";
  1955. resets = <0x01 0x05>;
  1956. iommus = <0x1a 0x00 0x01>;
  1957. status = "okay";
  1958. };
  1959.  
  1960. msgbox@0601f000 {
  1961. compatible = "sunxi,msgbox-amp";
  1962. reg = <0x00 0x3003000 0x00 0x1000 0x00 0x1701000 0x00 0x1000 0x00 0x601f000 0x00 0x1000>;
  1963. interrupts-extended = <0x0a 0x90 0x04 0x0a 0x66 0x04 0x0a 0x8c 0x04>;
  1964. clocks = <0x01 0x2a>;
  1965. rpmsg_id = "sunxi,dsp-msgbox\0sunxi,dsp-power-msgbox";
  1966. resets = <0x01 0x09>;
  1967. reset-names = "rst";
  1968. msgbox_amp_counts = <0x03>;
  1969. msgbox_amp_local = <0x02>;
  1970. rpmsg_amp_remote-0 = <0x01>;
  1971. rpmsg_read_channel-0 = <0x02>;
  1972. rpmsg_write_channel-0 = <0x02>;
  1973. rpmsg_amp_remote-1 = <0x01>;
  1974. rpmsg_read_channel-1 = <0x00>;
  1975. rpmsg_write_channel-1 = <0x00>;
  1976. };
  1977.  
  1978. lcd0@1c0c000 {
  1979. compatible = "allwinner,sunxi-lcd0";
  1980. reg = <0x00 0x1c0c000 0x00 0x00>;
  1981. pinctrl-names = "active\0sleep";
  1982. status = "okay";
  1983. lcd_used = <0x01>;
  1984. lcd_driver_name = "cwu50";
  1985. lcd_backlight = <0x32>;
  1986. lcd_if = <0x04>;
  1987. lcd_x = <0x2d0>;
  1988. lcd_y = <0x500>;
  1989. lcd_width = <0x5a>;
  1990. lcd_height = <0xa0>;
  1991. lcd_dclk_freq = <0x3e>;
  1992. lcd_pwm_used = <0x01>;
  1993. lcd_pwm_ch = <0x02>;
  1994. lcd_pwm_freq = <0x3e8>;
  1995. lcd_pwm_pol = <0x00>;
  1996. lcd_pwm_max_limit = <0xff>;
  1997. lcd_hbp = <0x28>;
  1998. lcd_ht = <0x316>;
  1999. lcd_hspw = <0x14>;
  2000. lcd_vbp = <0x12>;
  2001. lcd_vt = <0x51a>;
  2002. lcd_vspw = <0x02>;
  2003. lcd_dsi_if = <0x00>;
  2004. lcd_dsi_lane = <0x04>;
  2005. lcd_lvds_if = <0x00>;
  2006. lcd_lvds_colordepth = <0x00>;
  2007. lcd_lvds_mode = <0x00>;
  2008. lcd_frm = <0x00>;
  2009. lcd_hv_clk_phase = <0x00>;
  2010. lcd_hv_sync_polarity = <0x00>;
  2011. lcd_io_phase = <0x00>;
  2012. lcd_gamma_en = <0x00>;
  2013. lcd_bright_curve_en = <0x00>;
  2014. lcd_cmap_en = <0x00>;
  2015. lcd_fsync_en = <0x00>;
  2016. lcd_fsync_act_time = <0x3e8>;
  2017. lcd_fsync_dis_time = <0x3e8>;
  2018. lcd_fsync_pol = <0x00>;
  2019. deu_mode = <0x00>;
  2020. lcdgamma4iep = <0x16>;
  2021. smart_color = <0x5a>;
  2022. lcd_gpio_0 = <0x1d 0x03 0x13 0x00>;
  2023. pinctrl-0 = <0x4f>;
  2024. pinctrl-1 = <0x50>;
  2025. };
  2026.  
  2027. sdmmc@4022000 {
  2028. compatible = "allwinner,sunxi-mmc-v4p6x";
  2029. device_type = "sdc2";
  2030. reg = <0x00 0x4022000 0x00 0x1000>;
  2031. interrupts-extended = <0x0a 0x3a 0x04>;
  2032. clocks = <0x0b 0x01 0x05 0x01 0x3b 0x01 0x3e>;
  2033. clock-names = "osc24m\0pll_periph\0mmc\0ahb";
  2034. resets = <0x01 0x11>;
  2035. reset-names = "rst";
  2036. pinctrl-names = "default\0sleep";
  2037. pinctrl-0 = <0x51>;
  2038. pinctrl-1 = <0x52>;
  2039. bus-width = <0x04>;
  2040. req-page-count = <0x02>;
  2041. cap-mmc-highspeed;
  2042. cap-cmd23;
  2043. mmc-cache-ctrl;
  2044. non-removable;
  2045. max-frequency = <0x8f0d180>;
  2046. cap-erase;
  2047. mmc-high-capacity-erase-size;
  2048. no-sdio;
  2049. no-sd;
  2050. sdc_tm4_sm0_freq0 = <0x00>;
  2051. sdc_tm4_sm0_freq1 = <0x00>;
  2052. sdc_tm4_sm1_freq0 = <0x00>;
  2053. sdc_tm4_sm1_freq1 = <0x00>;
  2054. sdc_tm4_sm2_freq0 = <0x00>;
  2055. sdc_tm4_sm2_freq1 = <0x00>;
  2056. sdc_tm4_sm3_freq0 = <0x5000000>;
  2057. sdc_tm4_sm3_freq1 = <0x05>;
  2058. sdc_tm4_sm4_freq0 = <0x50000>;
  2059. sdc_tm4_sm4_freq1 = <0x04>;
  2060. sdc_tm4_sm4_freq0_cmd = <0x00>;
  2061. sdc_tm4_sm4_freq1_cmd = <0x00>;
  2062. mmc-ddr-1_8v;
  2063. mmc-hs200-1_8v;
  2064. ctl-spec-caps = <0x308>;
  2065. sunxi-power-save-mode;
  2066. sunxi-dis-signal-vol-sw;
  2067. mmc-bootpart-noacc;
  2068. status = "disabled";
  2069. };
  2070.  
  2071. sdmmc@4020000 {
  2072. compatible = "allwinner,sunxi-mmc-v5p3x";
  2073. device_type = "sdc0";
  2074. reg = <0x00 0x4020000 0x00 0x1000>;
  2075. interrupts-extended = <0x0a 0x38 0x04>;
  2076. clocks = <0x0b 0x01 0x05 0x01 0x39 0x01 0x3c>;
  2077. clock-names = "osc24m\0pll_periph\0mmc\0ahb";
  2078. resets = <0x01 0x0f>;
  2079. reset-names = "rst";
  2080. pinctrl-names = "default\0mmc_1v8\0sleep\0uart_jtag";
  2081. pinctrl-0 = <0x53>;
  2082. pinctrl-1 = <0x54>;
  2083. pinctrl-2 = <0x55>;
  2084. pinctrl-3 = <0x56 0x57>;
  2085. max-frequency = <0x8f0d180>;
  2086. bus-width = <0x04>;
  2087. req-page-count = <0x02>;
  2088. cap-sd-highspeed;
  2089. cap-wait-while-busy;
  2090. no-sdio;
  2091. no-mmc;
  2092. status = "okay";
  2093. cd-gpios = <0x1d 0x05 0x06 0x11>;
  2094. non-removable;
  2095. cd-inverted;
  2096. cd-used-24M;
  2097. sunxi-power-save-mode;
  2098. ctl-spec-caps = <0x08>;
  2099. };
  2100.  
  2101. sdmmc@4021000 {
  2102. compatible = "allwinner,sunxi-mmc-v5p3x";
  2103. device_type = "sdc1";
  2104. reg = <0x00 0x4021000 0x00 0x1000>;
  2105. interrupts-extended = <0x0a 0x39 0x04>;
  2106. clocks = <0x0b 0x01 0x05 0x01 0x3a 0x01 0x3d>;
  2107. clock-names = "osc24m\0pll_periph\0mmc\0ahb";
  2108. resets = <0x01 0x10>;
  2109. reset-names = "rst";
  2110. pinctrl-names = "default\0sleep";
  2111. pinctrl-0 = <0x58>;
  2112. pinctrl-1 = <0x59>;
  2113. max-frequency = <0x8f0d180>;
  2114. bus-width = <0x04>;
  2115. cap-sd-highspeed;
  2116. no-mmc;
  2117. keep-power-in-suspend;
  2118. sunxi-dly-52M-ddr4 = <0x01 0x00 0x00 0x00 0x02>;
  2119. sunxi-dly-104M = <0x01 0x00 0x00 0x00 0x01>;
  2120. sunxi-dly-208M = <0x01 0x00 0x00 0x00 0x01>;
  2121. status = "okay";
  2122. vmmc-supply = <0x5a>;
  2123. vqmmc-supply = <0x5b>;
  2124. mmc-pwrseq = <0x5c>;
  2125. no-sd;
  2126. cap-sdio-irq;
  2127. ignore-pm-notify;
  2128. ctl-spec-caps = <0x08>;
  2129.  
  2130. sdio-wifi@1 {
  2131. reg = <0x01>;
  2132. interrupt-parent = <0x1d>;
  2133. interrupts = <0x06 0x0a 0x08>;
  2134. interrupt-names = "host-wake";
  2135. };
  2136. };
  2137.  
  2138. hdmi@5500000 {
  2139. compatible = "allwinner,sunxi-hdmi";
  2140. reg = <0x00 0x5500000 0x00 0xfffff>;
  2141. interrupts-extended = <0x0a 0x5d 0x04>;
  2142. clocks = <0x01 0x70 0x01 0x6d 0x01 0x6e 0x01 0x75>;
  2143. clock-names = "clk_bus_hdmi\0clk_ddc\0clk_cec\0clk_tcon_tv";
  2144. resets = <0x01 0x33 0x01 0x34>;
  2145. reset-names = "rst_bus_sub\0rst_bus_main";
  2146. assigned-clocks = <0x01 0x6e>;
  2147. assigned-clock-parents = <0x01 0x6f>;
  2148. assigned-clock-rates = <0x00>;
  2149. status = "okay";
  2150. hdmi_used = <0x01>;
  2151. hdmi_power_cnt = <0x00>;
  2152. hdmi_cts_compatibility = <0x01>;
  2153. hdmi_hdcp_enable = <0x01>;
  2154. hdmi_hdcp22_enable = <0x00>;
  2155. hdmi_cec_support = <0x01>;
  2156. hdmi_cec_super_standby = <0x00>;
  2157. ddc_en_io_ctrl = <0x00>;
  2158. power_io_ctrl = <0x00>;
  2159. };
  2160.  
  2161. usbc0@0 {
  2162. device_type = "usbc0";
  2163. compatible = "allwinner,sunxi-otg-manager";
  2164. usb_port_type = <0x00>;
  2165. usb_detect_type = <0x01>;
  2166. usb_id_gpio = <0x1d 0x03 0x15 0x00>;
  2167. usb_det_vbus_gpio;
  2168. usb_regulator_io = "nocare";
  2169. usb_wakeup_suspend = <0x00>;
  2170. usb_luns = <0x03>;
  2171. usb_serial_unique = <0x00>;
  2172. usb_serial_number = "20080411";
  2173. rndis_wceis = <0x01>;
  2174. status = "okay";
  2175. usb_detect_mode = <0x00>;
  2176. enable-active-high;
  2177. };
  2178.  
  2179. udc-controller@0x04100000 {
  2180. compatible = "allwinner,sunxi-udc";
  2181. reg = <0x00 0x4100000 0x00 0x1000 0x00 0x00 0x00 0x100>;
  2182. interrupts-extended = <0x0a 0x2d 0x04>;
  2183. clocks = <0x01 0x6a>;
  2184. clock-names = "bus_otg";
  2185. resets = <0x01 0x30 0x01 0x2a>;
  2186. reset-names = "otg\0phy";
  2187. status = "okay";
  2188. };
  2189.  
  2190. ehci0-controller@0x04101000 {
  2191. compatible = "allwinner,sunxi-ehci0";
  2192. reg = <0x00 0x4101000 0x00 0xfff 0x00 0x00 0x00 0x100 0x00 0x4100000 0x00 0x1000>;
  2193. interrupts-extended = <0x0a 0x2e 0x04>;
  2194. clocks = <0x01 0x68>;
  2195. clock-names = "bus_hci";
  2196. resets = <0x01 0x2e 0x01 0x2a>;
  2197. reset-names = "hci\0phy";
  2198. hci_ctrl_no = <0x00>;
  2199. status = "okay";
  2200. drvvbus-supply = <0x5d>;
  2201. };
  2202.  
  2203. ohci0-controller@0x04101400 {
  2204. compatible = "allwinner,sunxi-ohci0";
  2205. reg = <0x00 0x4101400 0x00 0xfff 0x00 0x00 0x00 0x100 0x00 0x4100000 0x00 0x1000>;
  2206. interrupts-extended = <0x0a 0x2f 0x04>;
  2207. clocks = <0x01 0x66 0x01 0x64>;
  2208. clock-names = "bus_hci\0ohci";
  2209. resets = <0x01 0x2c 0x01 0x2a>;
  2210. reset-names = "hci\0phy";
  2211. hci_ctrl_no = <0x00>;
  2212. status = "okay";
  2213. drvvbus-supply = <0x5d>;
  2214. };
  2215.  
  2216. usbc1@0 {
  2217. device_type = "usbc1";
  2218. usb_regulator_io = "nocare";
  2219. usb_wakeup_suspend = <0x00>;
  2220. status = "okay";
  2221. };
  2222.  
  2223. ehci1-controller@0x04200000 {
  2224. compatible = "allwinner,sunxi-ehci1";
  2225. reg = <0x00 0x4200000 0x00 0xfff 0x00 0x00 0x00 0x100 0x00 0x4100000 0x00 0x1000>;
  2226. interrupts-extended = <0x0a 0x31 0x04>;
  2227. clocks = <0x01 0x69>;
  2228. clock-names = "bus_hci";
  2229. resets = <0x01 0x2f 0x01 0x2b>;
  2230. reset-names = "hci\0phy";
  2231. hci_ctrl_no = <0x01>;
  2232. status = "okay";
  2233. };
  2234.  
  2235. ohci1-controller@0x04200400 {
  2236. compatible = "allwinner,sunxi-ohci1";
  2237. reg = <0x00 0x4200400 0x00 0xfff 0x00 0x00 0x00 0x100 0x00 0x4100000 0x00 0x1000>;
  2238. interrupts-extended = <0x0a 0x32 0x04>;
  2239. clocks = <0x01 0x67 0x01 0x65>;
  2240. clock-names = "bus_hci\0ohci";
  2241. resets = <0x01 0x2d 0x01 0x2b>;
  2242. reset-names = "hci\0phy";
  2243. hci_ctrl_no = <0x01>;
  2244. status = "okay";
  2245. };
  2246.  
  2247. pwm0@2000c10 {
  2248. compatible = "allwinner,sunxi-pwm0";
  2249. reg = <0x00 0x2000c10 0x00 0x04>;
  2250. reg_base = <0x2000c00>;
  2251. pinctrl-names = "active\0sleep";
  2252. pinctrl-0 = <0x5e>;
  2253. pinctrl-1 = <0x5f>;
  2254. status = "okay";
  2255. phandle = <0x31>;
  2256. };
  2257.  
  2258. pwm1@2000c11 {
  2259. compatible = "allwinner,sunxi-pwm1";
  2260. reg = <0x00 0x2000c11 0x00 0x04>;
  2261. reg_base = <0x2000c00>;
  2262. phandle = <0x32>;
  2263. };
  2264.  
  2265. pwm2@2000c12 {
  2266. compatible = "allwinner,sunxi-pwm2";
  2267. reg = <0x00 0x2000c12 0x00 0x04>;
  2268. reg_base = <0x2000c00>;
  2269. pinctrl-names = "active\0sleep";
  2270. pinctrl-0 = <0x60>;
  2271. pinctrl-1 = <0x61>;
  2272. status = "okay";
  2273. phandle = <0x33>;
  2274. };
  2275.  
  2276. pwm3@2000c13 {
  2277. compatible = "allwinner,sunxi-pwm3";
  2278. reg = <0x00 0x2000c13 0x00 0x04>;
  2279. reg_base = <0x2000c00>;
  2280. phandle = <0x34>;
  2281. };
  2282.  
  2283. pwm4@2000c14 {
  2284. compatible = "allwinner,sunxi-pwm4";
  2285. reg = <0x00 0x2000c14 0x00 0x04>;
  2286. reg_base = <0x2000c00>;
  2287. phandle = <0x35>;
  2288. };
  2289.  
  2290. pwm5@2000c15 {
  2291. compatible = "allwinner,sunxi-pwm5";
  2292. reg = <0x00 0x2000c15 0x00 0x04>;
  2293. reg_base = <0x2000c00>;
  2294. phandle = <0x36>;
  2295. };
  2296.  
  2297. pwm6@2000c16 {
  2298. compatible = "allwinner,sunxi-pwm6";
  2299. reg = <0x00 0x2000c16 0x00 0x04>;
  2300. reg_base = <0x2000c00>;
  2301. phandle = <0x37>;
  2302. };
  2303.  
  2304. pwm7@2000c17 {
  2305. compatible = "allwinner,sunxi-pwm7";
  2306. reg = <0x00 0x2000c17 0x00 0x04>;
  2307. reg_base = <0x2000c00>;
  2308. phandle = <0x38>;
  2309. };
  2310.  
  2311. lcd_fb0@0 {
  2312. compatible = "allwinner,sunxi-lcd_fb0";
  2313. pinctrl-names = "active\0sleep";
  2314. status = "disabled";
  2315. };
  2316.  
  2317. vind@5800800 {
  2318. compatible = "allwinner,sunxi-vin-media\0simple-bus";
  2319. #address-cells = <0x02>;
  2320. #size-cells = <0x02>;
  2321. ranges;
  2322. device_id = <0x00>;
  2323. csi_top = <0x1406f400>;
  2324. csi_isp = <0x137d9fc0>;
  2325. reg = <0x00 0x5800800 0x00 0x200 0x00 0x5800000 0x00 0x800>;
  2326. clocks = <0x01 0x7f 0x01 0x0c 0x01 0x80 0x0b 0x01 0x0b 0x01 0x81 0x01 0x36>;
  2327. clock-names = "csi_top\0csi_top_src\0csi_mclk0\0csi_mclk0_24m\0csi_mclk0_pll\0csi_bus\0csi_mbus";
  2328. resets = <0x01 0x3e>;
  2329. reset-names = "csi_ret";
  2330. pinctrl-names = "mclk0-default\0mclk0-sleep";
  2331. pinctrl-0 = <0x62>;
  2332. pinctrl-1 = <0x63>;
  2333. status = "okay";
  2334.  
  2335. csi@5801000 {
  2336. compatible = "allwinner,sunxi-csi";
  2337. reg = <0x00 0x5801000 0x00 0x1000>;
  2338. interrupts-extended = <0x0a 0x74 0x04>;
  2339. pinctrl-names = "default\0sleep";
  2340. pinctrl-0 = <0x64>;
  2341. pinctrl-1 = <0x65>;
  2342. device_id = <0x00>;
  2343. iommus = <0x1a 0x01 0x01>;
  2344. status = "okay";
  2345. };
  2346.  
  2347. isp@5809410 {
  2348. compatible = "allwinner,sunxi-isp";
  2349. reg = <0x00 0x5809410 0x00 0x10>;
  2350. device_id = <0xfe>;
  2351. status = "okay";
  2352. };
  2353.  
  2354. isp@5809420 {
  2355. compatible = "allwinner,sunxi-isp";
  2356. reg = <0x00 0x5809420 0x00 0x10>;
  2357. device_id = <0xff>;
  2358. status = "okay";
  2359. };
  2360.  
  2361. scaler@5809430 {
  2362. compatible = "allwinner,sunxi-scaler";
  2363. reg = <0x00 0x5809430 0x00 0x10>;
  2364. device_id = <0xfe>;
  2365. status = "okay";
  2366. };
  2367.  
  2368. scaler@5809440 {
  2369. compatible = "allwinner,sunxi-scaler";
  2370. reg = <0x00 0x5809440 0x00 0x10>;
  2371. device_id = <0xff>;
  2372. status = "okay";
  2373. };
  2374.  
  2375. actuator@5809450 {
  2376. compatible = "allwinner,sunxi-actuator";
  2377. device_type = "actuator0";
  2378. reg = <0x00 0x5809450 0x00 0x10>;
  2379. actuator0_name = "ad5820_act";
  2380. actuator0_slave = <0x18>;
  2381. actuator0_af_pwdn;
  2382. actuator0_afvdd = "afvcc-csi";
  2383. actuator0_afvdd_vol = <0x2ab980>;
  2384. status = "disabled";
  2385. phandle = <0x67>;
  2386. };
  2387.  
  2388. flash@5809460 {
  2389. device_type = "flash0";
  2390. compatible = "allwinner,sunxi-flash";
  2391. reg = <0x00 0x5809460 0x00 0x10>;
  2392. flash0_type = <0x02>;
  2393. flash0_en;
  2394. flash0_mode;
  2395. flash0_flvdd = [00];
  2396. flash0_flvdd_vol;
  2397. device_id = <0x00>;
  2398. status = "disabled";
  2399. phandle = <0x66>;
  2400. };
  2401.  
  2402. sensor@5809470 {
  2403. reg = <0x00 0x5809470 0x00 0x10>;
  2404. device_type = "sensor0";
  2405. compatible = "allwinner,sunxi-sensor";
  2406. sensor0_mname = "ov5640";
  2407. sensor0_twi_cci_id = <0x02>;
  2408. sensor0_twi_addr = <0x78>;
  2409. sensor0_mclk_id = <0x00>;
  2410. sensor0_pos = "rear";
  2411. sensor0_isp_used = <0x00>;
  2412. sensor0_fmt = <0x00>;
  2413. sensor0_stby_mode = <0x00>;
  2414. sensor0_vflip = <0x00>;
  2415. sensor0_hflip = <0x00>;
  2416. sensor0_iovdd-supply;
  2417. sensor0_iovdd_vol;
  2418. sensor0_avdd-supply;
  2419. sensor0_avdd_vol;
  2420. sensor0_dvdd-supply;
  2421. sensor0_dvdd_vol;
  2422. sensor0_power_en;
  2423. sensor0_reset = <0x1d 0x04 0x09 0x01>;
  2424. sensor0_pwdn = <0x1d 0x04 0x08 0x01>;
  2425. sensor0_sm_vs;
  2426. flash_handle = <0x66>;
  2427. act_handle = <0x67>;
  2428. device_id = <0x00>;
  2429. status = "okay";
  2430. };
  2431.  
  2432. sensor@5809480 {
  2433. reg = <0x00 0x5809480 0x00 0x10>;
  2434. device_type = "sensor1";
  2435. compatible = "allwinner,sunxi-sensor";
  2436. sensor1_mname = "ov5647";
  2437. sensor1_twi_cci_id = <0x03>;
  2438. sensor1_twi_addr = <0x6c>;
  2439. sensor1_mclk_id = <0x01>;
  2440. sensor1_pos = "front";
  2441. sensor1_isp_used = <0x00>;
  2442. sensor1_fmt = <0x00>;
  2443. sensor1_stby_mode = <0x00>;
  2444. sensor1_vflip = <0x00>;
  2445. sensor1_hflip = <0x00>;
  2446. sensor1_iovdd-supply;
  2447. sensor1_iovdd_vol;
  2448. sensor1_avdd-supply;
  2449. sensor1_avdd_vol;
  2450. sensor1_dvdd-supply;
  2451. sensor1_dvdd_vol;
  2452. sensor1_power_en;
  2453. sensor1_reset = <0x1d 0x04 0x07 0x01>;
  2454. sensor1_pwdn = <0x1d 0x04 0x06 0x01>;
  2455. sensor1_sm_vs;
  2456. flash_handle;
  2457. act_handle;
  2458. device_id = <0x01>;
  2459. status = "okay";
  2460. };
  2461.  
  2462. vinc@5809000 {
  2463. compatible = "allwinner,sunxi-vin-core";
  2464. device_type = "vinc0";
  2465. reg = <0x00 0x5809000 0x00 0x200>;
  2466. interrupts-extended = <0x0a 0x6f 0x04>;
  2467. vinc0_csi_sel = <0x00>;
  2468. vinc0_mipi_sel = <0xff>;
  2469. vinc0_isp_sel = <0x00>;
  2470. vinc0_tdm_rx_sel = <0xff>;
  2471. vinc0_rear_sensor_sel = <0x00>;
  2472. vinc0_front_sensor_sel = <0x00>;
  2473. vinc0_sensor_list = <0x00>;
  2474. device_id = <0x00>;
  2475. iommus = <0x1a 0x01 0x01>;
  2476. status = "okay";
  2477. };
  2478.  
  2479. vinc@5809200 {
  2480. device_type = "vinc1";
  2481. compatible = "allwinner,sunxi-vin-core";
  2482. reg = <0x00 0x5809200 0x00 0x200>;
  2483. interrupts-extended = <0x0a 0x70 0x04>;
  2484. vinc1_csi_sel = <0x00>;
  2485. vinc1_mipi_sel = <0xff>;
  2486. vinc1_isp_sel = <0x01>;
  2487. vinc1_tdm_rx_sel = <0xff>;
  2488. vinc1_rear_sensor_sel = <0x00>;
  2489. vinc1_front_sensor_sel = <0x00>;
  2490. vinc1_sensor_list = <0x00>;
  2491. device_id = <0x01>;
  2492. iommus = <0x1a 0x01 0x01>;
  2493. status = "okay";
  2494. };
  2495. };
  2496.  
  2497. tvd@05c00000 {
  2498. compatible = "allwinner,sunxi-tvd";
  2499. reg = <0x00 0x5c00000 0x00 0x10000>;
  2500. interrupts-extended = <0x0a 0x7b 0x04>;
  2501. clocks = <0x01 0x7c 0x01 0x35>;
  2502. clock-names = "clk_bus_tvd_top\0clk_mbus_tvd";
  2503. resets = <0x01 0x3c>;
  2504. reset-names = "rst_bus_tvd_top";
  2505. tvd-number = <0x01>;
  2506. tvds = <0x68>;
  2507. status = "okay";
  2508. tvd_sw = <0x01>;
  2509. tvd_interface = <0x00>;
  2510. tvd_format = <0x00>;
  2511. tvd_system = <0x01>;
  2512. tvd_row = <0x01>;
  2513. tvd_column = <0x01>;
  2514. tvd_channel0_en = <0x01>;
  2515. tvd_channel1_en = <0x00>;
  2516. tvd_channel2_en = <0x00>;
  2517. tvd_channel3_en = <0x00>;
  2518. };
  2519.  
  2520. tvd0@05c01000 {
  2521. compatible = "allwinner,sunxi-tvd0";
  2522. reg = <0x00 0x5c01000 0x00 0x10000>;
  2523. interrupts-extended = <0x0a 0x7b 0x04>;
  2524. clocks = <0x01 0x7a 0x01 0x7b>;
  2525. clock-names = "clk_tvd0\0clk_bus_tvd0";
  2526. resets = <0x01 0x3b>;
  2527. reset-names = "rst_bus_tvd0";
  2528. assigned-clocks = <0x01 0x7a>;
  2529. assigned-clock-parents = <0x01 0x0b>;
  2530. tvd_used = <0x01>;
  2531. tvd_if = <0x00>;
  2532. status = "okay";
  2533. used = <0x01>;
  2534. agc_auto_enable = <0x01>;
  2535. agc_manual_value = <0x40>;
  2536. cagc_enable = <0x01>;
  2537. fliter_used = <0x01>;
  2538. phandle = <0x68>;
  2539. };
  2540.  
  2541. card0_boot_para@2 {
  2542. reg = <0x00 0x02 0x00 0x00>;
  2543. device_type = "card0_boot_para";
  2544. card_ctrl = <0x00>;
  2545. card_high_speed = <0x01>;
  2546. card_line = <0x04>;
  2547. pinctrl-0 = <0x53>;
  2548. };
  2549.  
  2550. card2_boot_para@3 {
  2551. reg = <0x00 0x03 0x00 0x00>;
  2552. device_type = "card2_boot_para";
  2553. card_ctrl = <0x02>;
  2554. card_high_speed = <0x01>;
  2555. card_line = <0x04>;
  2556. pinctrl-0 = <0x51>;
  2557. sdc_io_1v8 = <0x01>;
  2558. sdc_tm4_hs200_max_freq = <0x96>;
  2559. sdc_tm4_hs400_max_freq = <0x64>;
  2560. sdc_ex_dly_used = <0x02>;
  2561. };
  2562.  
  2563. rfkill@0 {
  2564. compatible = "allwinner,sunxi-rfkill";
  2565. chip_en;
  2566. power_en;
  2567. status = "okay";
  2568.  
  2569. wlan@0 {
  2570. compatible = "allwinner,sunxi-wlan";
  2571. wlan_busnum = <0x01>;
  2572. wakeup-source;
  2573. };
  2574.  
  2575. bt@0 {
  2576. compatible = "allwinner,sunxi-bt";
  2577. bt_rst_n = <0x1d 0x06 0x12 0x01>;
  2578. status = "okay";
  2579. };
  2580. };
  2581.  
  2582. btlpm@0 {
  2583. compatible = "allwinner,sunxi-btlpm";
  2584. uart_index = <0x01>;
  2585. bt_wake = <0x1d 0x06 0x10 0x00>;
  2586. bt_hostwake = <0x1d 0x06 0x11 0x00>;
  2587. status = "okay";
  2588. };
  2589.  
  2590. addr_mgt@0 {
  2591. compatible = "allwinner,sunxi-addr_mgt";
  2592. type_addr_wifi = <0x00>;
  2593. type_addr_bt = <0x00>;
  2594. type_addr_eth = <0x00>;
  2595. status = "okay";
  2596. };
  2597.  
  2598. battery@0 {
  2599. compatible = "simple-battery";
  2600. constant-charge-current-max-microamp = <0x200b20>;
  2601. voltage-min-design-microvolt = <0x325aa0>;
  2602. phandle = <0x28>;
  2603. };
  2604.  
  2605. wifi-pwrseq {
  2606. compatible = "mmc-pwrseq-simple";
  2607. clocks = <0x69 0x01>;
  2608. clock-names = "ext_clock";
  2609. reset-gpios = <0x1d 0x06 0x0b 0x01>;
  2610. post-power-on-delay-ms = <0xc8>;
  2611. phandle = <0x5c>;
  2612. };
  2613. };
  2614.  
  2615. dsp0 {
  2616. compatible = "allwinner,sun20iw1-dsp";
  2617. status = "okay";
  2618. };
  2619.  
  2620. dsp0_gpio_int {
  2621. compatible = "allwinner,sun20iw1-dsp-gpio-int";
  2622. pin-group = "PB\0PC\0PD\0PE";
  2623. status = "disabled";
  2624. };
  2625.  
  2626. vdd-cpu {
  2627. compatible = "sunxi-pwm-regulator";
  2628. pwms = <0x6a 0x00 0x1388 0x01>;
  2629. regulator-name = "vdd_cpu";
  2630. regulator-min-microvolt = <0xc5c10>;
  2631. regulator-max-microvolt = <0x11b340>;
  2632. regulator-ramp-delay = <0x19>;
  2633. regulator-always-on;
  2634. regulator-boot-on;
  2635. status = "okay";
  2636. phandle = <0x04>;
  2637. };
  2638.  
  2639. usb1-vbus {
  2640. compatible = "regulator-fixed";
  2641. regulator-name = "usb1-vbus";
  2642. regulator-min-microvolt = <0x4c4b40>;
  2643. regulator-max-microvolt = <0x4c4b40>;
  2644. regulator-enable-ramp-delay = <0x3e8>;
  2645. enable-active-high;
  2646. phandle = <0x5d>;
  2647. };
  2648.  
  2649. backlight@0 {
  2650. compatible = "ocp8178-backlight";
  2651. backlight-control-gpios = <0x1d 0x03 0x14 0x00>;
  2652. default-brightness = <0x05>;
  2653. };
  2654. };
  2655.  
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