testbench

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-- Company:
-- Engineer:
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-- Create Date: 04/24/2019 03:09:56 PM
-- Design Name:
-- Module Name: TB_tanh - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TB_tanh is
--  Port ( );
end TB_tanh;

architecture Behavioral of TB_tanh is
COMPONENT tanh
  PORT (
    aclock : IN STD_LOGIC;
      in_valid : IN STD_LOGIC;
      in_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
      out_valid : OUT STD_LOGIC;
      out_data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
  );
END COMPONENT;

signal clock :  STD_LOGIC:='0' ;
signal invalid : STD_LOGIC := '0' ;
signal input :  STD_LOGIC_VECTOR (15 downto 0 ) :="0010000000000000" ;
signal output :  STD_LOGIC_VECTOR (15 downto 0 ) ;
signal outvalid : STD_LOGIC ;

begin
unit_under_test :tanh
PORT MAP (
aclock => clock ,
in_valid => invalid ,
in_data => input,
out_valid => outvalid,
out_data => output
);

WAIT_PROC: process
begin

input <= "0000000000000000" ;
clock <= not clock after 5ns ;

invalid <= '1' ;
wait for 1000ns ;
invalid <= '0' ;

-- -1.5?
end process WAIT_PROC ;

end behavioral;