module deserTest;

	// Inputs
	reg [6:0] dataIn;
	reg clkIn;
	reg clkToOut;

	// Outputs
	wire [23:0] dataOut;
	wire clkOut;

	// Instantiate the Unit Under Test (UUT)
	deser7_24 uut (
		.dataIn(dataIn),
		.clkIn(clkIn),
		.clkToOut(clkToOut),
		.dataOut(dataOut),
		.clkOut(clkOut)
	);

	initial begin
		// Initialize Inputs
		dataIn = 7'b1100111;
		clkIn = 1;
		clkToOut = 0;

		// Wait 100 ns for global reset to finish
		#100;

		// Add stimulus here

	end
	always begin #7 clkIn = ~clkIn; end
	always begin #24 clkToOut = ~clkToOut; end
	always begin #203 dataIn = 7'b1100111;end


endmodule