dec_iX0.s

| Assembly Source File
| Created 8/16/09; 23:26:32

|Handlers for x=0

_hX0:
	move.b d7, d0
	and.b #7, d0
	goLUT _X0ZLUT

_hX0Z0:
	btst.b #5, d7
	beq _hX0Z0JRCC	|set bit 5 here is always conditional relative jump
	|otherwise use the LUT
	move.b d7, d0
	lsr.b #3, d0
	andi.b #3, d0
	goLUT _X0Z0LUT

|00000000 - NOP
|No operation
_hX0Z0NOP:
	move.b #4, d7
	rts
|00001000 - EX AF, AF'
|Exchange AF with its shadow
|No flags affected
_hX0Z0EXAF:
	lea reg_AF(a6), a0
	lea reg_SHADOW_AF(a6), a1
	move.w (a0), d0
	move.w (a1), (a0)
	move.w (a1), d0
	move.b #4, d7
	rts
|00010000:nnnnnnnn - DJNZ ofs8
|Decrement B and jump to ofs8 if B does not become zero
|No flags affected
_hX0Z0DJNZ:
	subq.b #1, reg_B(a6)
	beq _hX0Z0DJNZ_nj
	|should loop back
	move.b (a5), d0
	subq.l #1, a5	|return to opcode
	ext.w d0	|sign-extend the offset so we can add it
	adda.w d0, a5
	move.b #13, d7
	rts
_hX0Z0DJNZ_nj:
	addq #1, a5
	move.b #8, d7
	rts
|00011000:nnnnnnnn - JR ofs8
|Jump to ofs8
_hX0Z0JR:
	move.b (a5), d0
	subq #1, a5
	ext.w d0
	adda.w d0, a5
	move.b #12, d7
	rts
|001cc000:nnnnnnnn - JR cc, ofs8
|Jump to ofs8 if cc is true
_hX0Z0JRCC:
	lsr #4, d7
	and.b #3, d7
	jsr checkCondition
	bne _hX0Z0JR	|just like a plain jr if condition is true
	move.b #7, d7
	rts

|16-bit load/add
_hX0Z1:
	btst.b #3, d7
	beq _hX0Z1LDimm16
|00rr1001 - ADD HL, r16
|Add r16 to HL
|C affected as defined, H set if carry from bit 11, N reset
|TODO: implement H and N flags
_hX0Z1ADDHL:
	lsr.b #3, d7
	bclr #0, d7			|Register to grab
	move.w (a6, d7.b), d0
	add.w d0, reg_HL(a6)
	move.b #11, d7
	|TODO: copy carry from 68k to z80
	rts
|00rr0001:nnnnnnnn:nnnnnnnn - LD r16, imm16
|Set r16 to imm16
_hX0Z1LDimm16:
	lsr.b #3, d7
	adda.w d7, a0		|Safe not to mask, since only other possible set bit is 0
	move.b 1(a5), (a6, d7.b)	|MSB
	move.b (a5), 1(a6, d7.b)	|LSB
	addq.l #2, a5			|Next instruction
	move.b #10, d7
	rts

|00nnn010[:nnnnnnnn:nnnnnnnn] - various 16-bit indirect loads
_hX0Z2:
	clr.l d0
	move.b 1(a5), d0
	lsl.w #8, d0
	move.b (a5), d0
	movea.l addrSpace(a6), a1
	adda.l d0, a1	|a1 points to (imm16) if needed
	move.b d7, d0
	lsr.b #3, d0
	and.b #7, d0	|bits 3-5 for index
	goLUT _hX0Z2LUT
_hX0Z2bc2a:
_hX0Z2de2a:	|save a bit of code space with these
_hX0Z2a2bc:
_hX0Z2a2de:
	lsr.b #1, d0	|this could break (horribly) if goLUT ever changes
	and.b #2, d0	|offset from a6 to read
	clr.l d1
	move.b 1(a6, d0.b), d1
	lsl.w #8, d1
	move.b (a6, d0.b), d1	|emulated address to read
	movea.l addrSpace(a6), a0
	adda.l d1, a0	|effective address to read
	|jump according to bit 3 now
	btst.b #3, d7
	bne _hX0Z2a2r16
_hX0Z2r162a:
	move.b (a0), reg_A(a6)
	move.b #7, d7
	rts
_hX0Z2a2r16:
	move.b reg_A(a6), (a0)
	move.b #7, d7
	rts

_hX0Z2LUT:
	.word _hX0Z2bc2a
	.word _hX0Z2de2a
	.word _hX0Z2i2hl
	.word _hX0Z2i2a
	.word _hX0Z2a2bc
	.word _hX0Z2a2de
	.word _hX0Z2hl2i
	.word _hX0Z2a2i