`timescale 1ns/1ps

module LineDecoder_1x2(m0, m1, i0);
input i0;
output m0, m1;

not (m0, i0);
buf (m1, i0);
endmodule;

module LineDecoder_2x4(m0, m1, m2, m3, i0, i1);
input i0, i1;
output m0, m1, m2, m3;

wire ld1m0, ld1m1;
wire ld2m0, ld2m1;

LineDecoder_1x2 ld0(.m0(ld0m0), .m1(ld0m1), .i0(i0));

LineDecoder_1x2 ld1(.m0(ld1m0), .m1(ld1m1), .i0(i1));

and and_inst_m0 (m0, ld0m0, ld1m0);
and and_inst_m1 (m1, ld0m1, ld1m0);
and and_inst_m2 (m2, ld0m0, ld1m1);
and and_inst_m3 (m3, ld0m1, ld1m1);

endmodule;

module MUX2x1_1bit(out, in1, in0, s0);

input in1, in0, s0;
output out;

wire ld0m0, ld0m1;
wire am0, am1;

LineDecoder_1x2 ld0(.m0(ld0m0), .m1(ld0m1), .i0(s0));

and and_inst0(am0, ld0m0, in0);

and and_inst1(am1, ld0m1, in1);
or or_inst0(out, am0, am1);


endmodule;

module MUX2x1_4bit(out, in0, in1, s0);
input [3:0] in0, in1;
input s0;
output [3:0] out;

MUX2x1_1bit mx2x1_1b_0 (.out(out[0]), .in1(in1[0]), .in0(in0[0]), .s0(s0));
MUX2x1_1bit mx2x1_1b_1 (.out(out[1]), .in1(in1[1]), .in0(in0[1]), .s0(s0));
MUX2x1_1bit mx2x1_1b_2 (.out(out[2]), .in1(in1[2]), .in0(in0[2]), .s0(s0));
MUX2x1_1bit mx2x1_1b_3 (.out(out[3]), .in1(in1[3]), .in0(in0[3]), .s0(s0));


endmodule;

module MUX4x1_1bit(out, in3, in2, in1, in0, s1, s0);
input in3, in2, in1, in0, s1, s0;
output out;

wire ldm0, ldm1, ldm2, ldm3;
wire am0, am1, am2, am3;
LineDecoder_2x4 ld2x4_inst0(.m0(ldm0), .m1(ldm1), .m2(ldm2), .m3(ldm3), .i0(s0), .i1(s1));

and and_inst0(am0,ldm0,in0);
and and_inst1(am1,ldm1,in1);
and and_inst2(am2,ldm2,in2);
and and_inst3(am3,ldm3,in3);

or or_inst0(out, am0, am1, am2, am3);
endmodule;

module MUX4x1_4bit(out, in3, in2, in1, in0, s1, s0);
input [3:0] in3, in2, in1, in0;
input s1, s0;
output [3:0] out;

MUX4x1_1bit mx4x1_0(.out(out[0]), .in3(in3[0]),.in2(in2[0]),.in1(in1[0]),.in0(in0[0]),.s1(s1), .s0(s0));

MUX4x1_1bit mx4x1_1(.out(out[1]), .in3(in3[1]),.in2(in2[1]),.in1(in1[1]),.in0(in0[1]),.s1(s1), .s0(s0));

MUX4x1_1bit mx4x1_2(.out(out[2]), .in3(in3[2]),.in2(in2[2]),.in1(in1[2]),.in0(in0[2]),.s1(s1), .s0(s0));

MUX4x1_1bit mx4x1_3(.out(out[3]), .in3(in3[3]),.in2(in2[3]),.in1(in1[3]),.in0(in0[3]),.s1(s1), .s0(s0));


endmodule;

module LeftBarrelShifter_4bit(out, in, shamt);
input [3:0] in;
input [1:0] shamt;
output [3:0] out;
/*
wire [3:0] stage1;
MUX2x1_1bit mx2x1_lb_00(.out(stage1[0]), .in1(1'b0), .in0(in[0]), .s0(shamt[0]));
MUX2x1_1bit mx2x1_lb_01(.out(stage1[1]), .in1(in[1]), .in0(in[0]), .s0(shamt[0]));
MUX2x1_1bit mx2x1_lb_02(.out(stage1[2]), .in1(in[2]), .in0(in[0]), .s0(shamt[0]));
MUX2x1_1bit mx2x1_lb_03(.out(stage1[3]), .in1(in[3]), .in0(in[0]), .s0(shamt[0]));

*/

endmodule;

module RightBarrelShifter_4bit(out, in, shamt);
input [3:0] in;
input [1:0] shamt;
output [3:0] out;


endmodule;

module BarrelShifter_4bit(out, in, shamt, LnR);
input [3:0] in;
input [1:0] shamt;
input LnR;
output [3:0] out;


endmodule;