0001-Nordic-nRF24L01P-board-support-code.patch

From 2348f5c073711adb9376c97873867955b8153226 Mon Sep 17 00:00:00 2001
From: Daniel Hilst SellI <danielhilst@gmail.com>
Date: Wed, 27 Aug 2014 14:09:52 -0300
Subject: [PATCH] Nordic nRF24L01P board support code

---
 arch/arm/mach-mx6/board-mx6q_var_som.c | 35 ++++++++++++++++++++++++++++++++++
 arch/arm/mach-mx6/board-mx6q_var_som.h | 13 +++++++++++--
 include/linux/spi/Kbuild               |  1 +
 include/linux/spi/nrf24.h              | 35 ++++++++++++++++++++++++++++++++++
 4 files changed, 82 insertions(+), 2 deletions(-)
 create mode 100644 include/linux/spi/nrf24.h

diff --git a/arch/arm/mach-mx6/board-mx6q_var_som.c b/arch/arm/mach-mx6/board-mx6q_var_som.c
index c869038..915c063 100644
--- a/arch/arm/mach-mx6/board-mx6q_var_som.c
+++ b/arch/arm/mach-mx6/board-mx6q_var_som.c
@@ -31,6 +31,7 @@
 #include <linux/fsl_devices.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
+#include <linux/spi/nrf24.h>
 #include <linux/i2c.h>
 #include <linux/i2c/pca953x.h>
 #include <linux/ata.h>
@@ -85,6 +86,7 @@
  */
 //#define ANDROID_NAND_RECOVERY

+#define VAR_SOM_ECSPI1_CS0      IMX_GPIO_NR(4, 9)
 #define VAR_SOM_ECSPI3_CS0      IMX_GPIO_NR(4, 24)
 #define VAR_SOM_ADS7846_INT     IMX_GPIO_NR(4, 25)
 #define VAR_SOM_ADS7846_PD      IMX_GPIO_NR(4, 25)
@@ -111,6 +113,10 @@

 #define VAR_SOM_TSC_CTW6120_IRQ_GPIO IMX_GPIO_NR(3, 7)

+/* Needed by nRF2424L01P module */
+#define VAR_SOM_NRF24L01P_IRQ_GPIO IMX_GPIO_NR(5, 26)
+#define VAR_SOM_NRF24L01P_CE_GPIO IMX_GPIO_NR(5, 27)
+
 static struct clk *sata_clk;
 static struct clk *clko;
 static int enable_lcd_ldb;
@@ -368,10 +374,19 @@ static struct fec_platform_data fec_data __initdata = {
    .phy = PHY_INTERFACE_MODE_RGMII,
 };

+static int mx6q_var_som_ecspi1_cs[] = {
+   VAR_SOM_ECSPI1_CS0,
+};
+
 static int mx6q_var_som_spi_cs[] = {
    VAR_SOM_ECSPI3_CS0,
 };

+static const struct spi_imx_master mx6q_var_som_ecspi1_data __initconst = {
+   .chipselect     = mx6q_var_som_ecspi1_cs,
+   .num_chipselect = ARRAY_SIZE(mx6q_var_som_ecspi1_cs),
+};
+
 static const struct spi_imx_master mx6q_var_som_spi_data __initconst = {
    .chipselect     = mx6q_var_som_spi_cs,
    .num_chipselect = ARRAY_SIZE(mx6q_var_som_spi_cs),
@@ -404,12 +419,31 @@ static struct spi_board_info mx6_var_som_spi_ts_device[] __initdata = {
    },
 };

+static struct nrf24_platform_data nrf24_config = {
+        .gpio_ce  = VAR_SOM_NRF24L01P_CE_GPIO,
+        .gpio_irq = VAR_SOM_NRF24L01P_IRQ_GPIO,
+};
+
+static struct spi_board_info mx6_var_som_spi_nrf24[] __initdata = {
+        {
+                .modalias = "nrf24", /* nRF24L01+ */
+                .max_speed_hz = 8000000,
+                .bus_num = 0,
+                .chip_select = 0,
+                .platform_data = &nrf24_config,
+                .mode = SPI_MODE_0,
+        },
+};
+
 static void spi_device_init(void)
 {
    if (var_lcd_index != VAR_LCD_CTW6120) {
        spi_register_board_info(mx6_var_som_spi_ts_device,
                ARRAY_SIZE(mx6_var_som_spi_ts_device));
    }
+
+        spi_register_board_info(mx6_var_som_spi_nrf24,
+                               ARRAY_SIZE(mx6_var_som_spi_nrf24));
 }

 /* Audio
@@ -1150,6 +1184,7 @@ static void __init mx6_var_som_board_init(void)
    gpio_direction_output(VAR_SOM_BACKLIGHT_EN, 1);

    /* SPI */
+   imx6q_add_ecspi(0, &mx6q_var_som_ecspi1_data);
    imx6q_add_ecspi(2, &mx6q_var_som_spi_data);
    spi_device_init();

diff --git a/arch/arm/mach-mx6/board-mx6q_var_som.h b/arch/arm/mach-mx6/board-mx6q_var_som.h
index dc78c15..9eb7d07 100644
--- a/arch/arm/mach-mx6/board-mx6q_var_som.h
+++ b/arch/arm/mach-mx6/board-mx6q_var_som.h
@@ -58,6 +58,15 @@ static iomux_v3_cfg_t mx6q_var_som_pads[] = {
    MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS,
    MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD,

+        /* SPI1 (nRF24L01P) */
+        MX6Q_PAD_KEY_COL1__ECSPI1_MISO,
+        MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI,
+        MX6Q_PAD_KEY_COL0__ECSPI1_SCLK,
+
+        MX6Q_PAD_KEY_ROW1__GPIO_4_9, /* nRF24L01P SS0 */
+        MX6Q_PAD_CSI0_DAT9__GPIO_5_27, /* nRF24L01P CE  */
+        MX6Q_PAD_CSI0_DAT8__GPIO_5_26, /* nRF24L01P IRQ */
+
    /* SPI3 (ads7846) */
    MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO,
    MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI,
@@ -125,8 +134,8 @@ static iomux_v3_cfg_t mx6q_var_som_pads[] = {
    MX6Q_PAD_GPIO_17__GPIO_7_12,

    /* I2C1 */
-   MX6Q_PAD_CSI0_DAT8__I2C1_SDA,
-   MX6Q_PAD_CSI0_DAT9__I2C1_SCL,
+   /* MX6Q_PAD_CSI0_DAT8__I2C1_SDA, */
+   /* MX6Q_PAD_CSI0_DAT9__I2C1_SCL, */

    /* I2C2 */
    MX6Q_PAD_KEY_COL3__I2C2_SCL,
diff --git a/include/linux/spi/Kbuild b/include/linux/spi/Kbuild
index d375a08..b244544 100644
--- a/include/linux/spi/Kbuild
+++ b/include/linux/spi/Kbuild
@@ -1 +1,2 @@
 header-y += spidev.h
+header-y += nrf24.h
diff --git a/include/linux/spi/nrf24.h b/include/linux/spi/nrf24.h
new file mode 100644
index 0000000..71c2664
--- /dev/null
+++ b/include/linux/spi/nrf24.h
@@ -0,0 +1,35 @@
+#ifndef __LINUX_SPI_NRF24L01P_H
+#define __LINUX_SPI_NRF24L01P_H
+
+/* linux/spi/nRF24L01P */
+
+struct nrf24_platform_data {
+        unsigned int gpio_irq;
+        unsigned int gpio_ce;            /* Chip Enable */
+};
+
+
+#include <linux/ioctl.h>
+
+#define NRF24_MAGIC 'r'
+#define NRF24_IOCBASE  0x20
+#define NRF24_IOCSAA     _IOW(NRF24_MAGIC, NRF24_IOCBASE +  0, unsigned char)   /* Autoack, 7 bits, 0 = off, 1 = on */
+#define NRF24_IOCGAA     _IOR(NRF24_MAGIC, NRF24_IOCBASE +  1, unsigned char *)
+#define NRF24_IOCSCRC    _IOW(NRF24_MAGIC, NRF24_IOCBASE +  2, unsigned char)   /* CRC, 2 bits, bits 2 and 3 of CONFIG register */
+#define NRF24_IOCGCRC    _IOR(NRF24_MAGIC, NRF24_IOCBASE +  3, unsigned char *)
+#define NRF24_IOCSCH     _IOW(NRF24_MAGIC, NRF24_IOCBASE +  4, unsigned char) /* Channel, 7 bits, from 0 to 127 */
+#define NRF24_IOCGCH     _IOR(NRF24_MAGIC, NRF24_IOCBASE +  5, unsigned char *)
+#define NRF24_IOCSPW     _IOW(NRF24_MAGIC, NRF24_IOCBASE +  6, unsigned char) /* (RX) Payload width, 5 bits, from 0 to 32 */
+#define NRF24_IOCGPW     _IOR(NRF24_MAGIC, NRF24_IOCBASE +  7, unsigned char *)
+#define NRF24_IOCSTXADDR _IOW(NRF24_MAGIC, NRF24_IOCBASE +  8, unsigned char *) /* TX ADDR, from 3 to 5 bytes, depending on address width, see below */
+#define NRF24_IOCGTXADDR _IOR(NRF24_MAGIC, NRF24_IOCBASE +  9, unsigned char *)
+#define NRF24_IOCSRXADDR _IOW(NRF24_MAGIC, NRF24_IOCBASE + 10, unsigned char *) /* RX ADDR, same as TX ADDR */
+#define NRF24_IOCGRXADDR _IOR(NRF24_MAGIC, NRF24_IOCBASE + 11, unsigned char *)
+#define NRF24_IOCSAW     _IOW(NRF24_MAGIC, NRF24_IOCBASE + 12, unsigned char) /* Address Width, 2 bits, bits 0 and 1 of SETUP_AW register */
+#define NRF24_IOCGAW     _IOR(NRF24_MAGIC, NRF24_IOCBASE + 13, unsigned char *)
+#define NRF24_IOCSRETR   _IOW(NRF24_MAGIC, NRF24_IOCBASE + 14, unsigned char) /* Auto Retransmit, 7 bits from SETUP_RETR register */
+#define NRF24_IOCGRETR   _IOR(NRF24_MAGIC, NRF24_IOCBASE + 15, unsigned char *)
+#define NRF24_IOCSRF     _IOW(NRF24_MAGIC, NRF24_IOCBASE + 16, unsigned char) /* RF_SETUP, 7 bits from RF_SETUP register */
+#define NRF24_IOCGRF     _IOR(NRF24_MAGIC, NRF24_IOCBASE + 17, unsigned char *)
+
+#endif
--
2.0.3