----------------------------------------------
-- Uruchomienie na płytce DE1:
-- Set As Top-Level Entity na plik za_de1.vhd.
-- W komentarzach znajduje się opis przypisania sygnałów do przełączników i diod.
-----------------------------------------------


library ieee;
use ieee.std_logic_1164.all;

--zad. 1, cw2
entity automat is
port(
clk, clrn : in std_logic;
sclr : in std_logic;
x1, x2 : in std_logic;
c : out std_logic;
me : out std_logic_vector(1 downto 0);
mo1, mo0: out std_logic;
ST : out std_logic_vector(2 downto 0)
);
end entity;

architecture arch of automat is
type tauto is (S0, S1, S2, S3, S4);
signal auto_r, auto_n : tauto;
attribute syn_encoding: string;
attribute syn_encoding of tauto: type is "one-hot";

begin

p1:
process(clk, clrn)
begin
if(clrn = '0') then
 auto_r <= S0;
elsif(rising_edge(clk)) then
 auto_r <= auto_n;
end if;
end process p1;

p2:
process(auto_r,sclr, x1, x2)
begin
me <= "00";
case auto_r is
 when S0 =>
  if(x2 = '0' or x1 = '1') then
	auto_n <= S0;
  else
	auto_n <= S1;
  end if;
 when S1 =>
  if(x2 = '1' and x1 = '1') then
	auto_n <= S2;
  else
	auto_n <= S1;
  end if;
 when S2 =>
  if(x2 = '1' and x1 = '1') then
	auto_n <= S3;
  elsif(x2 = '1' and x1 = '0') then
	auto_n <= S1;
	me <= "01";
  else
	auto_n <= S2;
  end if;
 when S3 =>
  if(x2 = '1' and x1 = '1') then
	auto_n <= S0;
  elsif(x2 = '1' and x1 = '0') then
	auto_n <= S4;
	me <= "11";
  else
	auto_n <= S3;
  end if;
 when S4 =>
  if(x2 = '1' and x1 = '1') then
	auto_n <= S0;
	me <= "01";
  elsif(x2 = '1' and x1 = '0') then
	auto_n <= S1;
  else
	auto_n <= S4;
  end if;
end case;
if(sclr = '1') then
 auto_n <= S0;
end if;
end process p2;

p3:
process(auto_r)
begin
case auto_r is
when S0 =>
 mo1 <= '0'; mo0 <= '0';
 ST <= "000";
when S1 =>
 mo1 <= '0'; mo0 <= '1';
 ST <= "001";
when S2 =>
 mo1 <= '0'; mo0 <= '1';
 ST <= "010";
when S3 =>
 mo1 <= '0'; mo0 <= '1';
 ST <= "011";
when S4 =>
 mo1 <= '1'; mo0 <= '1';
 ST <= "100";
end case;
end process p3;

c <= '1' when auto_r = S3 and x2 = '1' and x1 = '0' else '0';
end arch;




Licznik

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--zad. 1, cw2
entity licz_rej is
port(
clk, clrn : in std_logic;
sclr : in std_logic;
cnt, ld : in std_logic;
L : out std_logic_vector(3 downto 0);
R : out std_logic_vector(3 downto 0)
);
end entity;

architecture arch of licz_rej is
signal reg : std_logic_vector(3 downto 0);
signal l_r, l_n : unsigned(3 downto 0);
begin

p1:
process(clk, clrn)
begin
if(clrn = '0') then
 reg <= (others => '0');
 l_r <= (others => '0');
elsif(rising_edge(clk)) then
 if(sclr = '1') then
  reg <= (others => '0');
 elsif(ld = '1') then
  reg <= std_logic_vector(l_r);
 end if;
 l_r <= l_n;
end if;
end process p1;

l_n <= (others => '0') when sclr = '1' else
		l_r + 1 when cnt = '1' else
		l_r;
L <= std_logic_vector(l_r);
R <= reg;
end arch;