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  1. // Standard C Included Files
  2. #include <stdio.h>
  3. // SDK Included Files
  4. #include "fsl_lptmr_driver.h"
  5. #include "board.h"
  6. #include "fsl_debug_console.h"
  7. //#include <cstddef>
  8. //#include "gpio_pins.h"
  9.  
  10.  
  11. extern void asm_pit1_irq(void);
  12. extern void config(void);
  13.     PRESERVE8
  14.     AREA MyCode,CODE,READONLY
  15.     EXPORT config
  16.     IMPORT my_fprint
  17.     EXPORT asm_pit1_irq
  18. PIT1_IRQHandler EQU asm_pit1_irq+1
  19.     EXPORT PIT1_IRQHandler      ;the vector table must contain odd addresses for the Cortex processor
  20. my_SIM_SCGC5 EQU    0x40048038      ;Address for SIM_SCGC5
  21. my_GPIOC_clken EQU  0x00000800      ;Clock gate enable for port A
  22. my_PORTC_PCR0 EQU   0x4004B000
  23. PORTC_PCR_VAL EQU   0x00000140
  24. ;my_GPIOA_PDOR EQU  0x400FF000
  25. my_GPIOC_PDDR EQU   0x400FF094
  26. my_GPIOC_PDOR EQU   0x400FF080
  27. my_GPIOC_PCOR EQU   0x400FF088
  28. my_GPIOC_PSOR EQU   0x400FF084
  29. ;GPIOA_PDOR_VAL EQU 0x30000800
  30. GPIOC_PDDR_VAL EQU  0x000007FF
  31. ;my_GPIOA_PCOR EQU  0x400FF008
  32. ;my_GPIOA_PSOR EQU  0x400FF004
  33. my_SIM_SCGC6 EQU    0x4004803C
  34. my_SCGC6_value EQU  0x00800000
  35.    
  36. my_PIT_MCR EQU      0x40037000
  37. my_PIT_LDVAL1 EQU   0x40037110
  38. my_LDVAL1_value EQU 0x0000C34F
  39. my_PIT_TFLG1 EQU    0x4003711C
  40. my_PIT_TCTRL1 EQU   0x40037118
  41.    
  42. my_NVIC_addr EQU    0xE000E108
  43. my_NVIC_value EQU   0x00000020
  44. config
  45.  
  46. ;write 1 to bit {11} of SIM_SCGC5, enable Port C clock gate
  47.     LDR     r2, =my_SIM_SCGC5       ;0x40048038
  48.     LDR     r1, =my_GPIOC_clken     ;0x00000800
  49.     LDR     r3, [r2]
  50.     ORR     r3, r3, r1
  51.     STR     r3, [r2]                ;enable GPIO_PORTC
  52.  
  53. ;For PortC PCR0-PCR10:
  54. ;write 1 to bit {6}, DSE, high drive strength
  55. ;write 001 to bits {8-10}, MUX, alternative 1 GPIO
  56.     MOV     r4, #0
  57.     LDR     r2, =my_PORTC_PCR0      ;0x4004B000 address PortC PCR0
  58.     LDR     r1, =PORTC_PCR_VAL      ;0x00000140
  59. next_portc
  60.     STR r1,[r2], #4
  61.     ADD r4,r4,#1
  62.     CMP r4,#11
  63.     BNE next_portc
  64.    
  65. ;set PDDR PCR bits 0-10 to logic 1 - set them as outputs
  66. ;bits 0-10 set to 1 (= 0x07ff)
  67.     LDR     r2, =my_GPIOC_PDDR      ;0x4000FF094
  68.     LDR     r1, =GPIOC_PDDR_VAL     ;0x0000007FF
  69.     STR     r1, [r2]
  70.    
  71. ;initializing off at reset
  72.     LDR r2, =my_GPIOC_PDOR
  73.     LDR r5, =0x000000FF
  74.     STR r5,[r2]
  75.    
  76. ;Set PIT timer by writing 1 to bit {23} of SIM_SCGC6
  77.     LDR      r2,=my_SIM_SCGC6       ;0x4004803C
  78.     LDR      r1,=my_SCGC6_value     ;0x00800000
  79.     LDR      r0,[r2]
  80.     ORR      r0,r0,r1
  81.     STR      r0,[r2]                ;enable clock to PIT1
  82.  
  83. ;enable the PIT module (0 to bits {0-1} of the MCR)
  84.     LDR      r2,=my_PIT_MCR         ;0x40037000, memory address for PCR
  85.     MOV      r0,#0
  86.     STR      r0,[r2]                ;stores 0x0 into PCR
  87.    
  88. ;sets the timer to interrupt every 2s by writing LDVAL1
  89.     LDR      r2,=my_PIT_LDVAL1      ;0x40037110, memory address for PIT_LDVAL1
  90. ;want it to trigger every 2s
  91. ;1ms/20ns - 1 =50e3 - 1 =0xC34F
  92.     LDR      r1,=my_LDVAL1_value    ;0xC34F
  93.     STR      r1,[r2]                ;load the count value to generate interrupt periodically
  94.  
  95. ;store 1 in bits {0,1} of TCTRL1, enable timer and interrupts
  96.     LDR      r2,=my_PIT_TCTRL1      ;0x40037118, memory address for PIT_TCTRL1
  97.     MOV      r0,#0x3
  98.     STR      r0,[r2]                ;set TIE and TEN bits
  99.  
  100. ;NVIC CONVIG
  101.     LDR      r2,=my_NVIC_value      ;0x00000020 sets IRQ 69
  102.     LDR      r1,=my_NVIC_addr       ;0xE000E108
  103.     STR      r2, [r1]
  104.    
  105.    
  106.     LDR      r5, =value             ;loads address of value for 7seg
  107.    
  108.    
  109. loop B loop
  110.    
  111. asm_pit1_irq
  112.     PUSH     {lr}                   ;store LR
  113.     LDR      r2,=my_PIT_TFLG1       ;load memory address of TFLG1
  114.     MOV      r3,#0x01               ;1 to clear flag
  115.     STR      r3,[r2]                ;store 1 to the memory to clear flags
  116.     LDR      r2, =irqcounter        ;load memory address of counter
  117.     LDRB     r3,[r2]                ;loads value from counter into r3
  118.     B        sevSeg
  119.  
  120. sevSeg
  121.     LDR      r7, =sevSegTable       ;loads address of lookup table
  122.     LDR      r6, [r5], #4           ;loads first value to be printed
  123.     LSL      r6, r6, #2             ;multiply value by 4
  124.     ADD      r6, r6, r7             ;add shift value to memory address
  125.     LDR      r8, [r6]               ;load value from lookup table
  126.     LDR      R9, =my_GPIOC_PDOR     ;load PDOR address to output
  127.     CMP      r3, #1                 ;branch to correct digit #
  128.     BEQ      dig_one
  129.     BGT      dig_two
  130.    
  131. dig_zero
  132.     ADD      r3,#1                  ;increment counter 
  133.     STRB     r3,[r2]                ;updating counter in memory
  134.     add      r8, r8, #0x400         ;0x400 turns on MS digit PTC10
  135.     ldr      r11, [r5]              ;check if next value is period
  136.     cmp      r11, #0x2E             ;print to 7seg and update address if true
  137.     subeq    r8, r8, #0x80
  138.     addeq    r5, r5, #4
  139.     str      r8, [r9]               ;store value in PDOR
  140.     pop      {pc}                   ;restore program
  141.    
  142. dig_one
  143.     ADD      r3,#1                  ;increment counter 
  144.     STRB     r3,[r2]                ;updating counter in memory
  145.     add      r8, r8, #0x200         ;0x200 turns on middle digit PTC9
  146.     ldr      r11, [r5]              ;check if next value is period
  147.     cmp      r11, #0x2E             ;print to 7seg and update address if true
  148.     subeq    r8, r8, #0x80
  149.     addeq    r5, r5, #4
  150.     str      r8, [r9]               ;store value in PDOR
  151.     POP      {pc}                   ;restore program
  152. dig_two
  153.     mov      r3, #0x0               ;reset counter (limit between 0 and 2)
  154.     strb     r3, [r2]               ;store 0 in counter memory
  155.     add      r8, r8, #0x100         ;0x100 turns on LS digit PTC8
  156.     ldr      r11, [r5]              ;check if next value is period
  157.     cmp      r11, #0x2E             ;print to 7seg and update address if true
  158.     subeq    r8, r8, #0x80
  159.     addeq    r5, r5, #4
  160.     STR      r8, [r9]               ;store value in PDOR
  161.     LDR      r5, =value             ;restart from first digit
  162.     POP      {pc}                   ;restore program
  163.    
  164.    
  165.     ALIGN
  166.     AREA MyData, DATA, READWRITE
  167. irqcounter  DCD 0x00
  168. value       DCD 0x07
  169.             dcd 0x2E
  170.             DCD 0x01
  171.             DCD 0x2E
  172.             DCD 0x02
  173.             dcd 0x2e
  174. sevSegTable DCD 0xC0
  175.             DCD 0xF9
  176.             DCD 0xA4
  177.             DCD 0xB0
  178.             DCD 0x99
  179.             DCD 0x92
  180.             DCD 0x82
  181.             DCD 0xF8
  182.             DCD 0x98
  183.             DCD 0xFF    ;period
  184.                
  185.            
  186.        
  187. DCD
  188.  
  189.     END
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