/* USER CODE BEGIN Header */
/**
  ******************************************************************************
  * @file           : main.c
  * @brief          : Main program body
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under BSD 3-Clause license,
  * the "License"; You may not use this file except in compliance with the
  * License. You may obtain a copy of the License at:
  *                        opensource.org/licenses/BSD-3-Clause
  *
  ******************************************************************************
  */
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/

#include "main.h"
#include <stdint.h>

 int RxBuff_inline[4];
 int TxBuff_inline[4];

uint8_t I2S1_TC = 0;
uint8_t I2S1_HC = 0;

void INIT_DMA(void);
void INIT_CLOCK(void);

void INIT_CLOCK() {
	//Obtaining 480 MHz
		//DIVM1: 4
		//DIVN1: 60
		//DIVP1: 2
		//D1CPRE: 1

		// FLASH_ACR
		// MASKING: FLASH_ACR
		// RESET Value: 0x37
		FLASH -> ACR &= ~FLASH_ACR_LATENCY;
		FLASH -> ACR &= ~FLASH_ACR_WRHIGHFREQ;
		// WRITING: FLASH_ACR
		FLASH -> ACR |= FLASH_ACR_LATENCY_4WS;
		FLASH -> ACR |= FLASH_ACR_WRHIGHFREQ_2;
		// CHECKING:
		if (((FLASH -> ACR) & (FLASH_ACR_LATENCY_4WS)) == FLASH_ACR_LATENCY_4WS){

		} else{
				//NO
		}


		// PWR_C3R
		// MASKING:
		   PWR -> CR3 &= ~PWR_CR3_LDOEN;
		// WRITING:
		   PWR -> CR3 |= PWR_CR3_LDOEN;


		// PWR_D3CR
		// MASKING:
	    // PWR -> D3CR &= ~PWR_D3CR_VOS;
		// WRITING:
		   PWR -> D3CR |=  PWR_D3CR_VOS1;

		// RCC_APB4ENR
		// MASKING:
		   RCC -> APB4ENR &= ~RCC_APB4ENR_SYSCFGEN;
		// WRITING:
		   RCC -> APB4ENR |= RCC_APB4ENR_SYSCFGEN;

		// SYSCFG_PWRCR
		// MASKING:
		   SYSCFG -> PWRCR &= ~SYSCFG_PWRCR_ODEN;
		// WRITING:
		   SYSCFG -> PWRCR |= SYSCFG_PWRCR_ODEN;

		// PWR_D3CR
		// WAITING:
		   while (((PWR -> D3CR) & (PWR_D3CR_VOSRDY)) == 0){};

		// RCC_CFGR
		// MASKING:
		RCC -> CFGR &= ~RCC_CFGR_SW;
		// WRITING:
		RCC -> CFGR |= RCC_CFGR_SW_PLL1;

		// RCC_PLL1DIVR
		// MASKING:
		RCC -> PLL1DIVR &= ~RCC_PLL1DIVR_P1;
		RCC -> PLL1DIVR &= ~RCC_PLL1DIVR_N1;
		// WRITING:
		RCC -> PLL1DIVR |= RCC_PLL1DIVR_P1_2;
		RCC -> PLL1DIVR |= RCC_PLL1DIVR_N1_60;

		// RCC_PLLCKSELR
		// MASKING:
		RCC -> PLLCKSELR &= ~RCC_PLLCKSELR_DIVM1;
		RCC -> PLLCKSELR &= ~RCC_PLLCKSELR_PLLSRC;
		// WRITING:
		RCC -> PLLCKSELR |= RCC_PLLCKSELR_DIVM1_4;
		RCC -> PLLCKSELR |= RCC_PLLCKSELR_PLLSRC_HSI;

		// RCC_D1CFGR
		// MASKING:
		RCC -> D1CFGR &= ~RCC_D1CFGR_D1CPRE;
		RCC -> D1CFGR &= ~RCC_D1CFGR_HPRE;
		RCC -> D1CFGR &= ~RCC_D1CFGR_D1PPRE;
		// Writing:
		RCC -> D1CFGR |= RCC_D1CFGR_D1CPRE_DIV1;
		RCC -> D1CFGR |= RCC_D1CFGR_HPRE_DIV2;
		RCC -> D1CFGR |= RCC_D1CFGR_D1PPRE_2;


		// RCC_D2CFGR
		// MASKING:
		RCC -> D2CFGR &= ~RCC_D2CFGR_D2PPRE1;
		RCC -> D2CFGR &= ~RCC_D2CFGR_D2PPRE2;
		// WRITING:
		RCC -> D2CFGR |= RCC_D2CFGR_D2PPRE1_DIV2;
		RCC -> D2CFGR |= RCC_D2CFGR_D2PPRE2_DIV2;

		// RCC_D3CFGR
		// MASKING:
		RCC -> D3CFGR &= ~RCC_D3CFGR_D3PPRE;
		// WRITING:
		RCC -> D3CFGR |= RCC_D3CFGR_D3PPRE_DIV2;

		// RCC_PLLCFGR
		// MASKING:
		RCC -> PLLCFGR &= ~RCC_PLLCFGR_PLL1RGE;
		RCC -> PLLCFGR &= ~RCC_PLLCFGR_PLL1VCOSEL;
		// WRITING:
		RCC -> PLLCFGR |= RCC_PLLCFGR_PLL1RGE_8_16;
		RCC -> PLLCFGR |= RCC_PLLCFGR_Wide_VCO_Range;
		RCC -> PLLCFGR |= RCC_PLLCFGR_DIVP1EN;

		// RCC_CR
		// MASKING:
		RCC -> CR &= ~RCC_CR_PLLON;
		// WRITING:
		RCC -> CR |= RCC_CR_PLLON;
		// WAITING:
		while (((RCC -> CR) & (RCC_CR_PLL1RDY)) == 0){};
}

void INIT_DMA() {

	//Setting Clock for 192kHz
		//N = 122
		//P = 4
		//M = 10
		//FRACT = 7209

		// RCC_PLL2DIVR
		// MASKING:
		RCC -> PLL2DIVR &= ~RCC_PLL2DIVR_P2;
		RCC -> PLL2DIVR &= ~RCC_PLL2DIVR_N2;
		// WRITING:
		RCC -> PLL2DIVR |= RCC_PLL2DIVR_P2_DIV8; // P
		RCC -> PLL2DIVR |= RCC_PLL2DIVR_N2_MULT122; // N

		// RCC_PLLCKSELR
		// MASKING:
		RCC -> PLLCKSELR &= ~RCC_PLLCKSELR_DIVM2;
		// WRITING:
		RCC -> PLLCKSELR |= RCC_PLLCKSELR_DIVM2_DIV10; // M

		// RCC_PLL2FRACR
		// MASKING:
		RCC -> PLL2FRACR &= ~RCC_PLL2FRACR_FRACN2;
		// WRITING:
		RCC -> PLL2FRACR |= RCC_PLL2FRACR_FRACN_7209; // FRAC

		// RCC_PLLCFGR
		// MASKING:
		RCC -> PLLCFGR &= ~RCC_PLLCFGR_DIVP2EN;
		RCC -> PLLCFGR &= ~RCC_PLLCFGR_PLL2RGE;
		RCC -> PLLCFGR &= ~RCC_PLLCFGR_PLL2VCOSEL;
		RCC -> PLLCFGR &= ~RCC_PLLCFGR_PLL2FRACEN;
		// WRITING:
		RCC -> PLLCFGR |= RCC_PLLCFGR_DIVP2EN;
		RCC -> PLLCFGR |= RCC_PLLCFGR_PLL2RGE_4_8;
		RCC -> PLLCFGR |= RCC_PLLCFGR_PLL2VCOSEL_192_836;
		RCC -> PLLCFGR |= RCC_PLLCFGR_PLL2FRACEN;

		// RCC_CR
		// MASKING:
		RCC -> CR &= ~RCC_CR_PLL2ON;
		// WRITING:
		RCC -> CR |= RCC_CR_PLL2ON;
		// WAITING:
		while (((RCC -> CR) & (RCC_CR_PLL2RDY)) == 0){};

		// ENALBING CLOCKS

		// RCC_AHB4ENR
		// MASKING:
		RCC -> AHB4ENR &= ~ RCC_AHB4ENR_GPIOAEN;
		RCC -> AHB4ENR &= ~ RCC_AHB4ENR_GPIOCEN;
		// WRITING:
		RCC -> AHB4ENR |= RCC_AHB4ENR_GPIOAEN;
	    RCC -> AHB4ENR |= RCC_AHB4ENR_GPIOCEN;

	    // RCC_APB2ENR
	    // MASKING:
	    RCC -> APB2ENR &= ~RCC_APB2ENR_SPI1EN;
	    // WRITING:
	    RCC -> APB2ENR |= RCC_APB2ENR_SPI1EN;

	    // CHANGING CLOCKS OF PERIPHERALS
	    // RCC_D2CCIP1R
	    // MASKING;
	    RCC -> D2CCIP1R &= ~RCC_D2CCIP1R_SPI123SEL;
	    // WRITING:
	    RCC -> D2CCIP1R |=  RCC_D2CCIP1R_SPI123SEL_PLL2_P_CK;

	    // CHANGING GPIO PINS TO ALETERNATIVE
	    // GPIOx_MODER
	    // MASKING
	    GPIOA -> MODER &= ~GPIO_MODER_MODE4;
	    GPIOA -> MODER &= ~GPIO_MODER_MODE5;
	    GPIOA -> MODER &= ~GPIO_MODER_MODE6;
	    GPIOA -> MODER &= ~GPIO_MODER_MODE7;
	    GPIOC -> MODER &= ~GPIO_MODER_MODE4;
	    // WRITING:
	    GPIOA -> MODER |= GPIO_MODER_MODE4_ALT;
	    GPIOA -> MODER |= GPIO_MODER_MODE5_ALT;
	    GPIOA -> MODER |= GPIO_MODER_MODE6_ALT;
	    GPIOA -> MODER |= GPIO_MODER_MODE7_ALT;
	    GPIOC -> MODER |= GPIO_MODER_MODE4_ALT;


	   GPIOA -> OSPEEDR &= ~GPIO_OSPEEDR_OSPEED7;
	    GPIOA -> OSPEEDR |= GPIO_OSPEEDR_OSPEED7_VERY_HIGH;

	    //SETTING ALT FUNCTIONS TO PINS
	    // GPIOx_AFRL
	    // MASKING:
	    GPIOA -> AFR[0] &= ~GPIO_AFRL_AFSEL4;
	    GPIOA -> AFR[0] &= ~GPIO_AFRL_AFSEL5;
	    GPIOA -> AFR[0] &= ~GPIO_AFRL_AFSEL6;
	    GPIOA -> AFR[0] &= ~GPIO_AFRL_AFSEL7;
	    GPIOC -> AFR[0] &= ~GPIO_AFRL_AFSEL4;
	    // WRITING;
	    GPIOA -> AFR[0] |= GPIO_AFRL_AFSEL4_AF5;
	    GPIOA -> AFR[0] |= GPIO_AFRL_AFSEL5_AF5;
	    GPIOA -> AFR[0] |= GPIO_AFRL_AFSEL6_AF5;
	    GPIOA -> AFR[0] |= GPIO_AFRL_AFSEL7_AF5;
	    GPIOC -> AFR[0] |= GPIO_AFRL_AFSEL4_AF5;

	    RCC -> AHB1ENR &= ~RCC_AHB1ENR_DMA1EN;
	       // WRITING:
	       RCC -> AHB1ENR |= RCC_AHB1ENR_DMA1EN;

	    // ENABLING DMA1
	    // RCC_AHB1ENR
	    // MASKING:
	    // MASKING:


	        // DMA1_Stream0_CR
	        // DMA1_Stream1_CR
	        // MASKING:
	        DMA1_Stream0 -> CR &= ~DMA_SxCR_CT;
	        DMA1_Stream0 -> CR &= ~DMA_SxCR_PL;
	        DMA1_Stream0 -> CR &= ~DMA_SxCR_MSIZE;
	        DMA1_Stream0 -> CR &= ~DMA_SxCR_PSIZE;
	        DMA1_Stream0 -> CR &= ~DMA_SxCR_MINC;
	        DMA1_Stream0 -> CR &= ~DMA_SxCR_CIRC;
	        DMA1_Stream0 -> CR &= ~DMA_SxCR_DIR;
	        DMA1_Stream0 -> CR &= ~DMA_SxCR_PFCTRL;
	        DMA1_Stream0 -> CR &= ~DMA_SxCR_TCIE;
	        DMA1_Stream0 -> CR &= ~DMA_SxCR_HTIE;

	        DMA1_Stream1 -> CR &= ~DMA_SxCR_CT;
	        DMA1_Stream1 -> CR &= ~DMA_SxCR_PL;
	        DMA1_Stream1 -> CR &= ~DMA_SxCR_MSIZE;
	        DMA1_Stream1 -> CR &= ~DMA_SxCR_PSIZE;
	        DMA1_Stream1 -> CR &= ~DMA_SxCR_MINC;
	        DMA1_Stream1 -> CR &= ~DMA_SxCR_CIRC;
	        DMA1_Stream1 -> CR &= ~DMA_SxCR_DIR;
	        DMA1_Stream1 -> CR &= ~DMA_SxCR_PFCTRL;
	        // WRITING:
	        DMA1_Stream0 -> CR |= DMA_SxCR_CT_MEM0;
	        DMA1_Stream0 -> CR |= DMA_SxCR_PL_Very_High;
	        DMA1_Stream0 -> CR |= DMA_SxCR_MSIZE_32BIT;
	        DMA1_Stream0 -> CR |= DMA_SxCR_PSIZE_32BIT;
	        DMA1_Stream0 -> CR |= DMA_SxCR_MINC;
	        DMA1_Stream0 -> CR |= DMA_SxCR_CIRC;
	        DMA1_Stream0 -> CR |= DMA_SxCR_DIR_P_TO_M;
	        DMA1_Stream0 -> CR |= DMA_SxCR_PFCTRL_DMAFLOW;
	        DMA1_Stream0 -> CR |= DMA_SxCR_TCIE;
	        DMA1_Stream0 -> CR |= DMA_SxCR_HTIE;

	        DMA1_Stream1 -> CR |= DMA_SxCR_CT_MEM0;
	        DMA1_Stream1 -> CR |= DMA_SxCR_PL_Very_High;
	        DMA1_Stream1 -> CR |= DMA_SxCR_MSIZE_32BIT;
	        DMA1_Stream1 -> CR |= DMA_SxCR_PSIZE_32BIT;
	        DMA1_Stream1 -> CR |= DMA_SxCR_MINC;
	        DMA1_Stream1 -> CR |= DMA_SxCR_CIRC;
	        DMA1_Stream1 -> CR |= DMA_SxCR_DIR_M_TO_P;
	        DMA1_Stream1 -> CR |= DMA_SxCR_PFCTRL_DMAFLOW;

	        // DMA_SxNDTR
	        // WRITING:
	        DMA1_Stream0 -> NDTR = 0x4;
	        DMA1_Stream1 -> NDTR = 0x4;

	        // DMA_SxPAR
	        // WRITING:
	        DMA1_Stream0 -> PAR = (uint32_t) & SPI1 -> RXDR;
	        DMA1_Stream1 -> PAR = (uint32_t) & SPI1 -> TXDR;

	        // DMA_SxM0AR
	        // WRITING:
	        DMA1_Stream0 -> M0AR = (uint32_t) RxBuff_inline;
	        DMA1_Stream1 -> M0AR = (uint32_t) TxBuff_inline;

	      // DMA_SxCR
	      // WRITING:
	     DMA1_Stream0 -> CR |= DMA_SxCR_EN;
	     DMA1_Stream1 -> CR |= DMA_SxCR_EN;

	                DMAMUX1_Channel0 -> CCR &= ~DMAMUX_CxCR_DMAREQ_ID;
	    	        DMAMUX1_Channel1 -> CCR &= ~DMAMUX_CxCR_DMAREQ_ID;
	    	        // WRITING:
	    	        DMAMUX1_Channel0 -> CCR |= DMAMUX_CxCR_DMAREQ_ID_SPI1_Rx; //Rx
	    	        DMAMUX1_Channel1 -> CCR |= DMAMUX_CxCR_DMAREQ_ID_SPI1_Tx; //Tx

	    // Setting up the SPI/I2S Peripheral
	    // MASKING:
	      SPI1->I2SCFGR = 0x00;
	      SPI1 -> CFG1 |= SPI_CFG1_RXDMAEN;
	      SPI1 -> CFG1 |= SPI_CFG1_TXDMAEN |
	    		  (SPI_CFG1_FTHLV_4_Data);
	      		             SPI1->I2SCFGR |= (SPI_I2SCFGR_MCKOE)              |
	      							          (SPI_I2SCFGR_I2SDIV_2)           |
	      							          (SPI_I2SCFGR_I2SSTD_I2STAND)        |
											  (SPI_I2SCFGR_DATFMT_LAlign) |
 	      							          (SPI_I2SCFGR_I2SCFG_MASTER_FULLDUPLEX) |
	      							          (SPI_I2SCFGR_I2SMOD_I2S_PCM_MODE);
	      		           SPI1->I2SCFGR |= (SPI_I2SCFGR_CHNEL_32BIT_WIDE);
	      		           SPI1->I2SCFGR |= (SPI_I2SCFGR_DATALEN_24BIT);
	      		           		 SPI1->CR1 |= SPI_CR1_SPE;
	      		           			 SPI1->CR1 |= SPI_CR1_CSTART;

		NVIC_EnableIRQ(DMA1_Stream0_IRQn);
		NVIC_SetPriority(DMA1_Stream0_IRQn,0);
}


int main (void) {

INIT_CLOCK();
INIT_DMA();

while (1) {




			if (I2S1_HC == 1) {
				for (int i = 0; i < 2; i++) {
					TxBuff_inline[i] = RxBuff_inline[i];
				}
				I2S1_HC = 0;
			}

			if (I2S1_TC == 1) {
				for (int i = 2; i < 4; i++) {
									TxBuff_inline[i] = RxBuff_inline[i];
								}
				I2S1_TC = 0;
			}


}


}


void DMA1_Stream0_IRQHandler() {

	if (((DMA1->LISR) & (DMA_LISR_HTIF0)) != 0) {
	      DMA1->LIFCR |= DMA_LIFCR_CHTIF0;

		  I2S1_HC = 1;
	}

	if (((DMA1->LISR) & (DMA_LISR_TCIF0)) != 0) {
		  DMA1->LIFCR |= DMA_LIFCR_CTCIF0;

		  I2S1_TC = 1;
	}
}