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  1. From 4193f89a33bd8231164ff20c4e02cda69a3a616c Mon Sep 17 00:00:00 2001
  2. From: =?UTF-8?q?Bj=C3=B6rn=20Sch=C3=A4pers?= <[email protected]>
  3. Date: Wed, 11 Sep 2024 22:48:27 +0200
  4. Subject: [PATCH] =?UTF-8?q?SvdParser:=20Korrigiere=20ADC-Register=20f?=
  5. =?UTF-8?q?=C3=BCr=20STM32H743?=
  6. MIME-Version: 1.0
  7. Content-Type: text/plain; charset=UTF-8
  8. Content-Transfer-Encoding: 8bit
  9.  
  10. Issue: LIB-41
  11. Change-Id: Ib78b18cfafc73197f92d493d3dc2804255c16e47
  12. ---
  13. module-providers/SvdParser/STM32H743.svd | 79 ++++++++++++++----------
  14. 1 file changed, 46 insertions(+), 33 deletions(-)
  15.  
  16. diff --git a/module-providers/SvdParser/STM32H743.svd b/module-providers/SvdParser/STM32H743.svd
  17. index 12cb53c..bbea80f 100644
  18. --- a/module-providers/SvdParser/STM32H743.svd
  19. +++ b/module-providers/SvdParser/STM32H743.svd
  20. @@ -40583,6 +40583,12 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
  21. <access>read-write</access>
  22. <resetValue>0x00000000</resetValue>
  23. <fields>
  24. + <field>
  25. + <name>LDORDY</name>
  26. + <description>LDO ready</description>
  27. + <bitOffset>12</bitOffset>
  28. + <bitWidth>1</bitWidth>
  29. + </field>
  30. <field>
  31. <name>JQOVF</name>
  32. <description>ADC group injected contexts queue
  33. @@ -40752,7 +40758,7 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
  34. <addressOffset>0x8</addressOffset>
  35. <size>0x20</size>
  36. <access>read-write</access>
  37. - <resetValue>0x00000000</resetValue>
  38. + <resetValue>0x20000000</resetValue>
  39. <fields>
  40. <field>
  41. <name>ADCAL</name>
  42. @@ -40832,7 +40838,7 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
  43. <name>BOOST</name>
  44. <description>Boost mode control</description>
  45. <bitOffset>8</bitOffset>
  46. - <bitWidth>1</bitWidth>
  47. + <bitWidth>2</bitWidth>
  48. </field>
  49. <field>
  50. <name>JADSTP</name>
  51. @@ -40883,7 +40889,7 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
  52. <addressOffset>0xC</addressOffset>
  53. <size>0x20</size>
  54. <access>read-write</access>
  55. - <resetValue>0x00000000</resetValue>
  56. + <resetValue>0x80000000</resetValue>
  57. <fields>
  58. <field>
  59. <name>JQDIS</name>
  60. @@ -41074,7 +41080,7 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
  61. <bitWidth>1</bitWidth>
  62. </field>
  63. <field>
  64. - <name>OSR</name>
  65. + <name>OVSR</name>
  66. <description>Oversampling ratio</description>
  67. <bitOffset>16</bitOffset>
  68. <bitWidth>10</bitWidth>
  69. @@ -41159,6 +41165,13 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
  70. <bitOffset>3</bitOffset>
  71. <bitWidth>3</bitWidth>
  72. </field>
  73. + <field>
  74. + <name>SMP0</name>
  75. + <description>ADC channel 0 sampling time
  76. + selection</description>
  77. + <bitOffset>0</bitOffset>
  78. + <bitWidth>3</bitWidth>
  79. + </field>
  80. </fields>
  81. </register>
  82. <register>
  83. @@ -41250,7 +41263,7 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
  84. <addressOffset>0x20</addressOffset>
  85. <size>0x20</size>
  86. <access>read-write</access>
  87. - <resetValue>0x0FFF0000</resetValue>
  88. + <resetValue>0x00000000</resetValue>
  89. <fields>
  90. <field>
  91. <name>LTR1</name>
  92. @@ -41262,18 +41275,18 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
  93. </fields>
  94. </register>
  95. <register>
  96. - <name>LHTR1</name>
  97. - <displayName>LHTR1</displayName>
  98. - <description>ADC analog watchdog 2 threshold
  99. + <name>HTR1</name>
  100. + <displayName>HTR1</displayName>
  101. + <description>ADC analog watchdog 1 threshold
  102. register</description>
  103. <addressOffset>0x24</addressOffset>
  104. <size>0x20</size>
  105. <access>read-write</access>
  106. - <resetValue>0x0FFF0000</resetValue>
  107. + <resetValue>0x03FFFFFF</resetValue>
  108. <fields>
  109. <field>
  110. - <name>LHTR1</name>
  111. - <description>ADC analog watchdog 2 threshold
  112. + <name>HTR1</name>
  113. + <description>ADC analog watchdog 1 threshold
  114. low</description>
  115. <bitOffset>0</bitOffset>
  116. <bitWidth>26</bitWidth>
  117. @@ -41319,7 +41332,7 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
  118. <bitWidth>5</bitWidth>
  119. </field>
  120. <field>
  121. - <name>L3</name>
  122. + <name>L</name>
  123. <description>L3</description>
  124. <bitOffset>0</bitOffset>
  125. <bitWidth>4</bitWidth>
  126. @@ -41537,19 +41550,19 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
  127. <fields>
  128. <field>
  129. <name>SSATE</name>
  130. - <description>ADC offset number 1 enable</description>
  131. + <description>ADC offset number 1 enable</description> <!-- Enable is not the correct description, but I don't care. -->
  132. <bitOffset>31</bitOffset>
  133. <bitWidth>1</bitWidth>
  134. </field>
  135. <field>
  136. - <name>OFFSET1_CH</name>
  137. + <name>OFFSET_CH</name>
  138. <description>ADC offset number 1 channel
  139. selection</description>
  140. <bitOffset>26</bitOffset>
  141. <bitWidth>5</bitWidth>
  142. </field>
  143. <field>
  144. - <name>OFFSET1</name>
  145. + <name>OFFSET</name>
  146. <description>ADC offset number 1 offset
  147. level</description>
  148. <bitOffset>0</bitOffset>
  149. @@ -41568,20 +41581,20 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
  150. <fields>
  151. <field>
  152. <name>SSATE</name>
  153. - <description>ADC offset number 1 enable</description>
  154. + <description>ADC offset number 2 enable</description>
  155. <bitOffset>31</bitOffset>
  156. <bitWidth>1</bitWidth>
  157. </field>
  158. <field>
  159. - <name>OFFSET1_CH</name>
  160. - <description>ADC offset number 1 channel
  161. + <name>OFFSET_CH</name>
  162. + <description>ADC offset number 2 channel
  163. selection</description>
  164. <bitOffset>26</bitOffset>
  165. <bitWidth>5</bitWidth>
  166. </field>
  167. <field>
  168. - <name>OFFSET1</name>
  169. - <description>ADC offset number 1 offset
  170. + <name>OFFSET</name>
  171. + <description>ADC offset number 2 offset
  172. level</description>
  173. <bitOffset>0</bitOffset>
  174. <bitWidth>26</bitWidth>
  175. @@ -41599,20 +41612,20 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
  176. <fields>
  177. <field>
  178. <name>SSATE</name>
  179. - <description>ADC offset number 1 enable</description>
  180. + <description>ADC offset number 3 enable</description>
  181. <bitOffset>31</bitOffset>
  182. <bitWidth>1</bitWidth>
  183. </field>
  184. <field>
  185. - <name>OFFSET1_CH</name>
  186. - <description>ADC offset number 1 channel
  187. + <name>OFFSET_CH</name>
  188. + <description>ADC offset number 3 channel
  189. selection</description>
  190. <bitOffset>26</bitOffset>
  191. <bitWidth>5</bitWidth>
  192. </field>
  193. <field>
  194. - <name>OFFSET1</name>
  195. - <description>ADC offset number 1 offset
  196. + <name>OFFSET</name>
  197. + <description>ADC offset number 3 offset
  198. level</description>
  199. <bitOffset>0</bitOffset>
  200. <bitWidth>26</bitWidth>
  201. @@ -41630,20 +41643,20 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
  202. <fields>
  203. <field>
  204. <name>SSATE</name>
  205. - <description>ADC offset number 1 enable</description>
  206. + <description>ADC offset number 4 enable</description>
  207. <bitOffset>31</bitOffset>
  208. <bitWidth>1</bitWidth>
  209. </field>
  210. <field>
  211. - <name>OFFSET1_CH</name>
  212. - <description>ADC offset number 1 channel
  213. + <name>OFFSET_CH</name>
  214. + <description>ADC offset number 4 channel
  215. selection</description>
  216. <bitOffset>26</bitOffset>
  217. <bitWidth>5</bitWidth>
  218. </field>
  219. <field>
  220. - <name>OFFSET1</name>
  221. - <description>ADC offset number 1 offset
  222. + <name>OFFSET</name>
  223. + <description>ADC offset number 4 offset
  224. level</description>
  225. <bitOffset>0</bitOffset>
  226. <bitWidth>26</bitWidth>
  227. @@ -41855,7 +41868,7 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
  228. <addressOffset>0xB4</addressOffset>
  229. <size>0x20</size>
  230. <access>read-write</access>
  231. - <resetValue>0x00000000</resetValue>
  232. + <resetValue>0x03FFFFFF</resetValue>
  233. <fields>
  234. <field>
  235. <name>HTR2</name>
  236. @@ -41893,7 +41906,7 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
  237. <addressOffset>0xBC</addressOffset>
  238. <size>0x20</size>
  239. <access>read-write</access>
  240. - <resetValue>0x00000000</resetValue>
  241. + <resetValue>0x03FFFFFF</resetValue>
  242. <fields>
  243. <field>
  244. <name>HTR3</name>
  245. @@ -42154,7 +42167,7 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
  246. <bitWidth>1</bitWidth>
  247. </field>
  248. <field>
  249. - <name>VSENSEEN</name>
  250. + <name>TSEN</name>
  251. <description>Temperature sensor enable</description>
  252. <bitOffset>23</bitOffset>
  253. <bitWidth>1</bitWidth>
  254. --
  255. 2.46.0
  256.  
  257.  
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