library ieee; use ieee.std_logic_1164.all;
    entity Controller is port(
        S: in std_logic;
        IR: in std_logic_vector (1 downto 0);
        IR_LD: out std_logic;
        MSA: out std_logic_vector (1 downto 0);
        MSB: out std_logic_vector (1 downto 0);
        MSC: out std_logic_vector (2 downto 0)
    );
    end Controller;
    architecture behavior of Controller is
    begin
        IR_LD <=
                (NOT S);
        MSC(2) <=
                (S AND IR(1));
        MSC(1) <=
                (S AND IR(1) AND IR(0));
        MSC(0) <=
                (S AND IR(1));
        MSB(1) <=
                ((NOT S) OR IR(1) OR IR(0));
        MSB(0) <=
                (S AND (NOT IR(1)) AND (NOT IR(0)));
        MSA(1) <=
                (S AND IR(1));
        MSA(0) <=
                ((NOT S) OR IR(1) OR (NOT IR(0)));
    end behavior;