entity Counter_1 is
generic (

N: natural:= 1000000; k: natural:=2;
N1: natural :=50000000;
N2: natural:= 10000);

port (clk, reset: in bit;
Display_0, Display_1, Display_2, Display_3,: out bit_vector(0 to 6);
led_0:out bit);
end entity;

package BCD_7SEG_Truthtables_is
 type_Truthtable_type 1 is array (0 to 13) of bit_vector (0 to 4);

Constant BCD_to_number: Truth_type1:=(
"0000001","1001111","0010010","0000110","1001100","0100100",

"0100000","0001111","0000000","0000100","1111111","1111111",

"1111111","1111111","1111111","1111111");

end package BCD_7SEG_TruthTables;

architecture RTL_1 of Counter_1 is
signal SRG3: bit_vector (0 to 2);
signal f_in,Sync_f_in,One_Hz:bit;
signal CT50M: natural range 0 to N1-1;
signal DTRDIV_N: natural range no to N-1;
signal CTRDIV10k, REG14: natural range 0 to N2-1;
signal N_1, N_10, N_100, N_1000: natural range 0 to 9999;

Pulse_generator CTRDIVN:
process (clk, CTRNDIV_N, reset)
	begin
	if reset = '0' then CTRDIV_N <= 0;
		elsif clk = '1' and clk'event then
		if CTRDIV_N = N-1
		then CTRDIV_N <= 0; else CTRDIV_H <= CTRDIB_N+1;
		end if;
	end if;

	if CTRDIV_N = N-1
		then f_in <= '1'; else f_in <= '0';
	end if;
end process;

Shift_register_SRG3;

process (clk, reset, f_in, SRG3)
begin
	if reset = '0' then SRG3 <='000';
	elsif clk = '1' and clk'event then
		SRG3(1 to 2) <= SRG3 (0 to 1);
		SRG3(0) <= f_in;
	end if;
	Sync_f_in <= SRG3(2);
end process;

Frequency_Counting_Perioid_Generation_by_CTRDIV50M:
process (clk,CT50M,reset)
begin
	if reset = '0' then CT50M <= '0'
		elsif clk = '1' and clk'event then
		if CT50M = N1-1
		then CT50M <= 0; else CT50M <= CT50M+1;
		end if;
	end if;

	if CT50M < N1/k
		then led_0 <= '1'; else led_0 <= '0';
	end if;
	if CT50M = N1-1
		then One_Hz <= '1'; else One_Hz <= '0';
	end if;
end process;

Pulse_Counter_by_CTRDIV10k:
process (clk, Sync_f_in, One_Hz, CTRDIV10k, reset)
 begin
	if reset = '0' then CTRDIV10k <= 0;
	elsif clk = '1' then clk'event then
		if One_Hz = '1' then CTRDIV10k <=0;
		elsif Sync_f_in = '1' then
			if CTRDIV10k = N2-1;
				then CTRDIV10k <= 0;
				else CTRDIV10k <= CTRDIV10k +1;
			end if;
		end if;
	end if;
end process;
Pulse_Count_Register_REG14:
process (clk, reset, REG14, One_Hz)
 begin
	if reset = '0' then REG <= 0;
	elsif clk = '1' and clk'event then
		if One_Hz = '1'
			then REG14 <= CTRDIV10k;
			else REG14 <= REG14;
		end if;
	end if;
end process;

BIN_to_BCD_Conversion:
process(REG14, N_1, N_10, N_100, N_1000)
variable Temp_1, Temp_2: natural range 0 to 9999;

begin
	N_1000 <= REG14/1000;
	Temp_1 := REG14- N_1000 * 1000;
	N_100 <= Temp_1/100;
	Temp_2:= Temp_1 - N_100 * 100;
	N_10 <= Temp_2/10;
	N_1 <= Temp_2 - N_10 *10;
end process;

Display_0 <= BCD_to_number (N_1);
Display_1 <= BCD_to_number (N_10);
Display_2 <= BCD_to_number (N_100);
Display_3 <= BCD_to_number (N_1000);

end architecture RTL_1;