start:
; r24 and r25 are input
    ldi r20, 16         ; Amount of times to loop
loop:
; PORTB |= B00000100;
    sbi PORTB, 2        ; 2cc           Set bit 2 in PORTB, after this instruction we start counting
; __builtin_avr_delay_cycles
    nop             ; 1cc       1   Wait a cycle
; PORTB &=  (data << 2) | B11111011;
    lsr r24         ; 1cc       2       r24 >> 1, puts bit 0 into carry flag
    ror r25         ; 1cc       3       r25 >> 1, puts carry flag into bit 7
    ldi r18, 255        ; 1cc       4   r18 is going to be data[0] << 2, alternative instruction: ser r18
    rol r18         ; 1cc       5       r18 is 11111111 if bit in data set, 11111110 otherwise
    rol r18         ; 1cc       5       r18 << 1 + C, r18 is 11111111 if bit in data set, 11111101 otherwise
    rol r18         ; 1cc       7       r18 << 1 + C, r18 is 11111111 if bit in data set, 11111011 otherwise
    in  r19, PORTB      ; 1cc       8   Read the value of PORTB to "and" with
    and r18, r19        ; 1cc       9   Do the "and"
    out PORTB, r18      ; 1cc       10  Write the value back to PORTB <- here we are at the 625ns
; __builtin_avr_delay_cycles
    lpm r18, Z          ; 3cc       13  Do some dumb things to wait 8 cycles
    lpm r18, Z          ; 3cc       16
    nop             ; 1cc       17  Delay again 2 cycles
    nop             ; 1cc       18
; PORTB &= B11111011;
    cbi PORTB, 2        ; 2cc       20  Clear the bit in PORTB again <- here we are at the 1250ns
; __builtin_avr_delay_cycles
    nop             ; 1cc       21  Wait 2 cycles
    nop             ; 1cc       22
; for (int i = 0; i < 16; i++) {
    dec r20         ; 1cc       23  Loop 16 times
    brne    loop            ; 2cc/1cc   25/24   Jump if not zero yet (+2 cycles from the sbi PORTB, 25+2 makes 27)
    nop             ; 1cc       25  Wait 3 cycles for the last one
    nop             ; 1cc       26
    nop             ; 1cc       27