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Nov 6th, 2022
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  1.  
  2.  
  3. [NOTE ] coreboot-4.18-156-g8a76e170c64-MrChromebox-4.18.1 Thu Oct 27 13:24:50 UTC 2022 bootblock starting (log level: 7)...
  4. [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x604000.
  5. [DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 6
  6. [DEBUG] FMAP: area COREBOOT found @ 604200 (2080256 bytes)
  7. [INFO ] CBFS: mcache @0xfe002e00 built for 17 files, used 0x374 of 0x4000 bytes
  8. [INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x65d0 in mcache @0xfe002e2c
  9. [DEBUG] BS: bootblock times (exec / console): total (unknown) / 1 ms
  10.  
  11.  
  12. [NOTE ] coreboot-4.18-156-g8a76e170c64-MrChromebox-4.18.1 Thu Oct 27 13:24:50 UTC 2022 romstage starting (log level: 7)...
  13. [DEBUG] Enabling VR PS2 mode: VNN VCC
  14. [DEBUG] FMAP: area COREBOOT found @ 604200 (2080256 bytes)
  15. [INFO ] CBFS: Found 'spd.bin' @0x39c00 size 0x400 in mcache @0xfe002f98
  16. [DEBUG] ram_id=3, total_spds: 4
  17. [DEBUG] pm1_sts: 2900 pm1_en: 0000 pm1_cnt: 00000000
  18. [DEBUG] gpe0_sts: 00000000 gpe0_en: 00000000 tco_sts: 00000000
  19. [DEBUG] prsts: 04450900 gen_pmcon1: 00001038 gen_pmcon2: 00000200
  20. [DEBUG] prev_sleep_state = S0
  21. [DEBUG] FMAP: area RW_MRC_CACHE found @ 5b0000 (65536 bytes)
  22. [INFO ] CBFS: Found 'mrc.bin' @0x19adc0 size 0x11218 in mcache @0xfe0030f0
  23. BayTrail-MD MRC wrapper v5
  24. Training for Memory Down designs.
  25. Applying weaker ODT settings. DRAM ODT is 120.
  26. [DEBUG] CBMEM:
  27. [DEBUG] IMD: root @ 0x7afff000 254 entries.
  28. [DEBUG] IMD: root @ 0x7affec00 62 entries.
  29. [DEBUG] FMAP: area RO_VPD found @ 600000 (16384 bytes)
  30. [ERROR] init_vpd_rdev: No RW_VPD FMAP section.
  31. [DEBUG] External stage cache:
  32. [DEBUG] IMD: root @ 0x7b7ff000 254 entries.
  33. [DEBUG] IMD: root @ 0x7b7fec00 62 entries.
  34. [INFO ] MRC v0.97
  35. [INFO ] 2 channels of DDR3 @ 1333MHz
  36. [DEBUG] CBMEM entry for DIMM info: 0x7afdb000
  37. [DEBUG] MRC Wrapper returned 0
  38. [DEBUG] MRC data at 0xfe00965f 5719 bytes
  39. [DEBUG] SMM Memory Map
  40. [DEBUG] SMRAM : 0x7b000000 0x800000
  41. [DEBUG] Subregion 0: 0x7b000000 0x700000
  42. [DEBUG] Subregion 1: 0x7b700000 0x100000
  43. [DEBUG] Subregion 2: 0x7b800000 0x0
  44. [DEBUG] Normal boot
  45. [INFO ] CBFS: Found 'fallback/postcar' @0x51580 size 0x566c in mcache @0xfe003080
  46. [DEBUG] Loading module at 0x7afcd000 with entry 0x7afcd031. filesize: 0x52e0 memsize: 0xb618
  47. [DEBUG] Processing 211 relocs. Offset value of 0x78fcd000
  48. [DEBUG] BS: romstage times (exec / console): total (unknown) / 1 ms
  49.  
  50.  
  51. [NOTE ] coreboot-4.18-156-g8a76e170c64-MrChromebox-4.18.1 Thu Oct 27 13:24:50 UTC 2022 postcar starting (log level: 7)...
  52. [DEBUG] Normal boot
  53. [DEBUG] FMAP: area COREBOOT found @ 604200 (2080256 bytes)
  54. [INFO ] CBFS: Found 'fallback/ramstage' @0x1ff40 size 0x1937f in mcache @0x7afdd0dc
  55. [DEBUG] Loading module at 0x7af7a000 with entry 0x7af7a000. filesize: 0x3a978 memsize: 0x51390
  56. [DEBUG] Processing 3521 relocs. Offset value of 0x76f7a000
  57. [DEBUG] BS: postcar times (exec / console): total (unknown) / 0 ms
  58.  
  59.  
  60. [NOTE ] coreboot-4.18-156-g8a76e170c64-MrChromebox-4.18.1 Thu Oct 27 13:24:50 UTC 2022 ramstage starting (log level: 7)...
  61. [DEBUG] Normal boot
  62. [DEBUG] FMAP: area COREBOOT found @ 604200 (2080256 bytes)
  63. [INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x6700 size 0x19800 in mcache @0x7afdd0ac
  64. [DEBUG] microcode: sig=0x30678 pf=0x8 revision=0x838
  65. [DEBUG] BYT: cpuid 00030678 cpus 2 rid 0e step C0
  66. [DEBUG] msr(17) = 000c000090341f4e
  67. [DEBUG] msr(ce) = 0000060000001a00
  68. [DEBUG] ModPHY init entry
  69. [DEBUG] SOC B0 and later ModPhy Table programming
  70. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  71. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  72. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  73. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  74. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  75. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  76. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  77. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  78. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  79. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  80. [DEBUG] ModPHY init done
  81. [DEBUG] Tri-state TDO and TMS
  82. [DEBUG] Initializing sideband SCC registers.
  83. [DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 2 / 0 ms
  84. [INFO ] Enumerating buses...
  85. [DEBUG] Root Device scanning...
  86. [DEBUG] CPU_CLUSTER: 0 enabled
  87. [DEBUG] DOMAIN: 0000 enabled
  88. [DEBUG] DOMAIN: 0000 scanning...
  89. [DEBUG] PCI: pci_scan_bus for bus 00
  90. [DEBUG] PCI: 00:00.0 [8086/0f00] enabled
  91. [DEBUG] PCI: 00:02.0 [8086/0f31] enabled
  92. [DEBUG] PCI: 00:10.0: Disabling device: 10.0
  93. [DEBUG] Power management CAP offset 0x80.
  94. [DEBUG] PCI: 00:11.0: Disabling device: 11.0
  95. [DEBUG] Power management CAP offset 0x80.
  96. [DEBUG] PCI: 00:12.0 [8086/0f16] enabled
  97. [INFO ] PCI: Static device PCI: 00:13.0 not found, disabling it.
  98. [DEBUG] PCI: 00:14.0 [8086/0f35] enabled
  99. [DEBUG] PCI: 00:15.0 [8086/0f28] enabled
  100. [DEBUG] PCI: 00:17.0 [8086/0f50] enabled
  101. [DEBUG] PCI: 00:18.0 [8086/0f40] enabled
  102. [DEBUG] PCI: 00:18.1 [8086/0f41] enabled
  103. [DEBUG] PCI: 00:18.2 [8086/0f42] enabled
  104. [DEBUG] PCI: 00:18.3: Disabling device: 18.3
  105. [DEBUG] Power management CAP offset 0x80.
  106. [DEBUG] PCI: 00:18.4: Disabling device: 18.4
  107. [DEBUG] Power management CAP offset 0x80.
  108. [DEBUG] PCI: 00:18.5: Disabling device: 18.5
  109. [DEBUG] Power management CAP offset 0x80.
  110. [DEBUG] PCI: 00:18.5 [8086/0f45] disabled
  111. [DEBUG] PCI: 00:18.6: Disabling device: 18.6
  112. [DEBUG] Power management CAP offset 0x80.
  113. [DEBUG] PCI: 00:18.6 [8086/0f46] disabled
  114. [DEBUG] PCI: 00:18.7: Disabling device: 18.7
  115. [DEBUG] Power management CAP offset 0x80.
  116. [DEBUG] PCI: 00:1a.0: Disabling device: 1a.0
  117. [DEBUG] PCI: 00:1b.0 [8086/0f04] enabled
  118. [DEBUG] PCI: 00:1c.0 [8086/0f48] enabled
  119. [DEBUG] No PCIe device present.
  120. [WARN ] reg_script_run_step: POLL timeout waiting for 0x328 to be 0x1000000, got 0x0
  121. [DEBUG] PCI: 00:1c.1: Disabling device: 1c.1
  122. [DEBUG] Power management CAP offset 0xa0.
  123. [DEBUG] PCI: 00:1c.1 [8086/0f4a] disabled
  124. [DEBUG] PCI: 00:1c.2: Disabling device: 1c.2
  125. [DEBUG] Power management CAP offset 0xa0.
  126. [DEBUG] PCI: 00:1c.3: Disabling device: 1c.3
  127. [DEBUG] Power management CAP offset 0xa0.
  128. [DEBUG] PCI: 00:1d.0 [8086/0f34] enabled
  129. [DEBUG] PCI: 00:1e.0 [8086/0f06] enabled
  130. [DEBUG] PCI: 00:1e.1: Disabling device: 1e.1
  131. [DEBUG] Power management CAP offset 0x80.
  132. [DEBUG] PCI: 00:1e.2: Disabling device: 1e.2
  133. [DEBUG] Power management CAP offset 0x80.
  134. [DEBUG] PCI: 00:1e.3: Disabling device: 1e.3
  135. [DEBUG] Power management CAP offset 0x80.
  136. [DEBUG] PCI: 00:1e.4: Disabling device: 1e.4
  137. [DEBUG] Power management CAP offset 0x80.
  138. [DEBUG] PCI: 00:1e.4 [8086/0f0c] disabled
  139. [DEBUG] PCI: 00:1e.5: Disabling device: 1e.5
  140. [DEBUG] Power management CAP offset 0x80.
  141. [DEBUG] PCI: 00:1e.5 [8086/0f0e] disabled
  142. [DEBUG] PCI: 00:1f.0 [8086/0f1c] enabled
  143. [DEBUG] PCI: 00:1f.3: Disabling device: 1f.3
  144. [DEBUG] Power management CAP offset 0x50.
  145. [WARN ] PCI: Leftover static devices:
  146. [WARN ] PCI: 00:10.0
  147. [WARN ] PCI: 00:11.0
  148. [WARN ] PCI: 00:13.0
  149. [WARN ] PCI: 00:18.3
  150. [WARN ] PCI: 00:18.4
  151. [WARN ] PCI: 00:18.7
  152. [WARN ] PCI: 00:1a.0
  153. [WARN ] PCI: 00:1c.2
  154. [WARN ] PCI: 00:1c.3
  155. [WARN ] PCI: 00:1e.1
  156. [WARN ] PCI: 00:1e.2
  157. [WARN ] PCI: 00:1e.3
  158. [WARN ] PCI: 00:1f.3
  159. [WARN ] PCI: Check your devicetree.cb.
  160. [DEBUG] PCI: 00:1c.0 scanning...
  161. [DEBUG] PCI: pci_scan_bus for bus 01
  162. [DEBUG] PCI: 01:00.0 [8086/08b1] enabled
  163. [INFO ] Enabling Common Clock Configuration
  164. [INFO ] ASPM: Enabled L1
  165. [INFO ] PCIe: Max_Payload_Size adjusted to 128
  166. [DEBUG] scan_bus: bus PCI: 00:1c.0 finished in 0 msecs
  167. [DEBUG] PCI: 00:1f.0 scanning...
  168. [DEBUG] PNP: 0c31.0 enabled
  169. [DEBUG] PNP: 00ff.1 enabled
  170. [DEBUG] PNP: 00ff.0 enabled
  171. [DEBUG] PNP: 00ff.0 scanning...
  172. [DEBUG] scan_bus: bus PNP: 00ff.0 finished in 0 msecs
  173. [DEBUG] scan_bus: bus PCI: 00:1f.0 finished in 0 msecs
  174. [DEBUG] scan_bus: bus DOMAIN: 0000 finished in 50 msecs
  175. [DEBUG] scan_bus: bus Root Device finished in 50 msecs
  176. [INFO ] done
  177. [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 51 / 0 ms
  178. [DEBUG] FMAP: area RW_MRC_CACHE found @ 5b0000 (65536 bytes)
  179. [DEBUG] FMAP: area RW_MRC_CACHE found @ 5b0000 (65536 bytes)
  180. [DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
  181. [INFO ] Manufacturer: ef
  182. [INFO ] SF: Detected ef 6017 with sector size 0x1000, total 0x800000
  183. [DEBUG] MRC: 'RW_MRC_CACHE' does not need update.
  184. [DEBUG] found VGA at PCI: 00:02.0
  185. [DEBUG] Setting up VGA for PCI: 00:02.0
  186. [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
  187. [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
  188. [INFO ] Allocating resources...
  189. [INFO ] Reading resources...
  190. [INFO ] Available memory above 4GB: 2048M
  191. [ERROR] PNP: 00ff.1 missing read_resources
  192. [INFO ] Done reading resources.
  193. [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
  194. [DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
  195. [DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done
  196. [DEBUG] PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  197. [DEBUG] PCI: 01:00.0 10 * [0x0 - 0x1fff] mem
  198. [DEBUG] PCI: 00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
  199. [DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
  200. [DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
  201. [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
  202. [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
  203. [DEBUG] update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
  204. [DEBUG] update_constraints: PNP: 00ff.0 00 base 00000800 limit 000009fe io (fixed)
  205. [INFO ] DOMAIN: 0000: Resource ranges:
  206. [INFO ] * Base: 1000, Size: f000, Tag: 100
  207. [DEBUG] PCI: 00:02.0 20 * [0x1000 - 0x1007] limit: 1007 io
  208. [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
  209. [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff
  210. [DEBUG] update_constraints: PCI: 00:00.0 27 base e0000000 limit efffffff mem (fixed)
  211. [DEBUG] update_constraints: PCI: 00:00.0 00 base 00000000 limit 0009ffff mem (fixed)
  212. [DEBUG] update_constraints: PCI: 00:00.0 01 base 000c0000 limit 7affffff mem (fixed)
  213. [DEBUG] update_constraints: PCI: 00:00.0 02 base 7b000000 limit 7b7fffff mem (fixed)
  214. [DEBUG] update_constraints: PCI: 00:00.0 03 base 7b800000 limit 7fffffff mem (fixed)
  215. [DEBUG] update_constraints: PCI: 00:00.0 04 base 100000000 limit 17fffffff mem (fixed)
  216. [DEBUG] update_constraints: PCI: 00:00.0 05 base 000a0000 limit 000bffff mem (fixed)
  217. [DEBUG] update_constraints: PCI: 00:00.0 06 base 000c0000 limit 000fffff mem (fixed)
  218. [DEBUG] update_constraints: PCI: 00:15.0 a8 base 20000000 limit 200fffff mem (fixed)
  219. [DEBUG] update_constraints: PCI: 00:1f.0 feb base feb00000 limit febfffff mem (fixed)
  220. [DEBUG] update_constraints: PCI: 00:1f.0 44 base fed03000 limit fed033ff mem (fixed)
  221. [DEBUG] update_constraints: PCI: 00:1f.0 4c base fed0c000 limit fed0ffff mem (fixed)
  222. [DEBUG] update_constraints: PCI: 00:1f.0 50 base fed08000 limit fed083ff mem (fixed)
  223. [DEBUG] update_constraints: PCI: 00:1f.0 54 base fed01000 limit fed013ff mem (fixed)
  224. [DEBUG] update_constraints: PCI: 00:1f.0 58 base fef00000 limit feffffff mem (fixed)
  225. [DEBUG] update_constraints: PCI: 00:1f.0 5c base fed05000 limit fed057ff mem (fixed)
  226. [DEBUG] update_constraints: PCI: 00:1f.0 f0 base fed1c000 limit fed1c3ff mem (fixed)
  227. [DEBUG] update_constraints: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed)
  228. [INFO ] DOMAIN: 0000: Resource ranges:
  229. [INFO ] * Base: 80000000, Size: 60000000, Tag: 200
  230. [INFO ] * Base: f0000000, Size: eb00000, Tag: 200
  231. [INFO ] * Base: fec00000, Size: 101000, Tag: 200
  232. [INFO ] * Base: fed02000, Size: 1000, Tag: 200
  233. [INFO ] * Base: fed04000, Size: 1000, Tag: 200
  234. [INFO ] * Base: fed06000, Size: 2000, Tag: 200
  235. [INFO ] * Base: fed09000, Size: 3000, Tag: 200
  236. [INFO ] * Base: fed10000, Size: c000, Tag: 200
  237. [INFO ] * Base: fed1d000, Size: 23000, Tag: 200
  238. [INFO ] * Base: fed45000, Size: 1bb000, Tag: 200
  239. [INFO ] * Base: ff000000, Size: 1000000, Tag: 200
  240. [INFO ] * Base: 180000000, Size: e80000000, Tag: 100200
  241. [DEBUG] PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
  242. [DEBUG] PCI: 00:02.0 10 * [0x90000000 - 0x903fffff] limit: 903fffff mem
  243. [DEBUG] PCI: 00:15.0 10 * [0x90400000 - 0x905fffff] limit: 905fffff mem
  244. [DEBUG] PCI: 00:1c.0 20 * [0x90600000 - 0x906fffff] limit: 906fffff mem
  245. [DEBUG] PCI: 00:14.0 10 * [0x90700000 - 0x9070ffff] limit: 9070ffff mem
  246. [DEBUG] PCI: 00:18.0 10 * [0x90710000 - 0x90713fff] limit: 90713fff mem
  247. [DEBUG] PCI: 00:1b.0 10 * [0x90714000 - 0x90717fff] limit: 90717fff mem
  248. [DEBUG] PCI: 00:1e.0 10 * [0x90718000 - 0x9071bfff] limit: 9071bfff mem
  249. [DEBUG] PCI: 00:12.0 10 * [0x9071c000 - 0x9071cfff] limit: 9071cfff mem
  250. [DEBUG] PCI: 00:12.0 14 * [0x9071d000 - 0x9071dfff] limit: 9071dfff mem
  251. [DEBUG] PCI: 00:15.0 14 * [0x9071e000 - 0x9071efff] limit: 9071efff mem
  252. [DEBUG] PCI: 00:17.0 10 * [0x9071f000 - 0x9071ffff] limit: 9071ffff mem
  253. [DEBUG] PCI: 00:17.0 14 * [0x90720000 - 0x90720fff] limit: 90720fff mem
  254. [DEBUG] PCI: 00:18.0 14 * [0x90721000 - 0x90721fff] limit: 90721fff mem
  255. [DEBUG] PCI: 00:18.1 10 * [0x90722000 - 0x90722fff] limit: 90722fff mem
  256. [DEBUG] PCI: 00:18.1 14 * [0x90723000 - 0x90723fff] limit: 90723fff mem
  257. [DEBUG] PCI: 00:18.2 10 * [0x90724000 - 0x90724fff] limit: 90724fff mem
  258. [DEBUG] PCI: 00:18.2 14 * [0x90725000 - 0x90725fff] limit: 90725fff mem
  259. [DEBUG] PCI: 00:1e.0 14 * [0x90726000 - 0x90726fff] limit: 90726fff mem
  260. [DEBUG] PCI: 00:1d.0 10 * [0x90727000 - 0x907273ff] limit: 907273ff mem
  261. [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done
  262. [DEBUG] PCI: 00:1c.0 mem: base: 90600000 size: 100000 align: 20 gran: 20 limit: 906fffff
  263. [INFO ] PCI: 00:1c.0: Resource ranges:
  264. [INFO ] * Base: 90600000, Size: 100000, Tag: 200
  265. [DEBUG] PCI: 01:00.0 10 * [0x90600000 - 0x90601fff] limit: 90601fff mem
  266. [DEBUG] PCI: 00:1c.0 mem: base: 90600000 size: 100000 align: 20 gran: 20 limit: 906fffff done
  267. [INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
  268. [ERROR] PCI: 00:00.0 missing set_resources
  269. [DEBUG] PCI: 00:02.0 10 <- [0x0000000090000000 - 0x00000000903fffff] size 0x00400000 gran 0x16 mem
  270. [DEBUG] PCI: 00:02.0 18 <- [0x0000000080000000 - 0x000000008fffffff] size 0x10000000 gran 0x1c prefmem
  271. [DEBUG] PCI: 00:02.0 20 <- [0x0000000000001000 - 0x0000000000001007] size 0x00000008 gran 0x03 io
  272. [DEBUG] PCI: 00:12.0 10 <- [0x000000009071c000 - 0x000000009071cfff] size 0x00001000 gran 0x0c mem
  273. [DEBUG] PCI: 00:12.0 14 <- [0x000000009071d000 - 0x000000009071dfff] size 0x00001000 gran 0x0c mem
  274. [DEBUG] PCI: 00:14.0 10 <- [0x0000000090700000 - 0x000000009070ffff] size 0x00010000 gran 0x10 mem64
  275. [DEBUG] PCI: 00:15.0 10 <- [0x0000000090400000 - 0x00000000905fffff] size 0x00200000 gran 0x15 mem
  276. [DEBUG] PCI: 00:15.0 14 <- [0x000000009071e000 - 0x000000009071efff] size 0x00001000 gran 0x0c mem
  277. [DEBUG] PCI: 00:17.0 10 <- [0x000000009071f000 - 0x000000009071ffff] size 0x00001000 gran 0x0c mem
  278. [DEBUG] PCI: 00:17.0 14 <- [0x0000000090720000 - 0x0000000090720fff] size 0x00001000 gran 0x0c mem
  279. [DEBUG] PCI: 00:18.0 10 <- [0x0000000090710000 - 0x0000000090713fff] size 0x00004000 gran 0x0e mem
  280. [DEBUG] PCI: 00:18.0 14 <- [0x0000000090721000 - 0x0000000090721fff] size 0x00001000 gran 0x0c mem
  281. [DEBUG] PCI: 00:18.1 10 <- [0x0000000090722000 - 0x0000000090722fff] size 0x00001000 gran 0x0c mem
  282. [DEBUG] PCI: 00:18.1 14 <- [0x0000000090723000 - 0x0000000090723fff] size 0x00001000 gran 0x0c mem
  283. [DEBUG] PCI: 00:18.2 10 <- [0x0000000090724000 - 0x0000000090724fff] size 0x00001000 gran 0x0c mem
  284. [DEBUG] PCI: 00:18.2 14 <- [0x0000000090725000 - 0x0000000090725fff] size 0x00001000 gran 0x0c mem
  285. [DEBUG] PCI: 00:1b.0 10 <- [0x0000000090714000 - 0x0000000090717fff] size 0x00004000 gran 0x0e mem64
  286. [DEBUG] PCI: 00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 01 io
  287. [DEBUG] PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
  288. [DEBUG] PCI: 00:1c.0 20 <- [0x0000000090600000 - 0x00000000906fffff] size 0x00100000 gran 0x14 bus 01 mem
  289. [DEBUG] PCI: 01:00.0 10 <- [0x0000000090600000 - 0x0000000090601fff] size 0x00002000 gran 0x0d mem64
  290. [DEBUG] PCI: 00:1d.0 10 <- [0x0000000090727000 - 0x00000000907273ff] size 0x00000400 gran 0x0a mem
  291. [DEBUG] PCI: 00:1e.0 10 <- [0x0000000090718000 - 0x000000009071bfff] size 0x00004000 gran 0x0e mem
  292. [DEBUG] PCI: 00:1e.0 14 <- [0x0000000090726000 - 0x0000000090726fff] size 0x00001000 gran 0x0c mem
  293. [INFO ] Done setting resources.
  294. [INFO ] Done allocating resources.
  295. [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 1 / 0 ms
  296. [INFO ] Enabling resources...
  297. [DEBUG] PCI: 00:02.0 subsystem <- 8086/0f31
  298. [DEBUG] PCI: 00:02.0 cmd <- 03
  299. [DEBUG] PCI: 00:12.0 subsystem <- 8086/0f16
  300. [DEBUG] PCI: 00:12.0 cmd <- 106
  301. [DEBUG] PCI: 00:14.0 subsystem <- 8086/0f35
  302. [DEBUG] PCI: 00:14.0 cmd <- 102
  303. [DEBUG] PCI: 00:15.0 subsystem <- 8086/0f28
  304. [DEBUG] PCI: 00:15.0 cmd <- 102
  305. [DEBUG] PCI: 00:17.0 subsystem <- 8086/0f50
  306. [DEBUG] PCI: 00:17.0 cmd <- 106
  307. [DEBUG] PCI: 00:18.0 subsystem <- 8086/0f40
  308. [DEBUG] PCI: 00:18.0 cmd <- 106
  309. [DEBUG] PCI: 00:18.1 subsystem <- 8086/0f41
  310. [DEBUG] PCI: 00:18.1 cmd <- 102
  311. [DEBUG] PCI: 00:18.2 subsystem <- 8086/0f42
  312. [DEBUG] PCI: 00:18.2 cmd <- 102
  313. [DEBUG] PCI: 00:1b.0 subsystem <- 8086/0f04
  314. [DEBUG] PCI: 00:1b.0 cmd <- 102
  315. [DEBUG] PCI: 00:1c.0 bridge ctrl <- 0013
  316. [DEBUG] PCI: 00:1c.0 subsystem <- 8086/0f48
  317. [DEBUG] PCI: 00:1c.0 cmd <- 106
  318. [DEBUG] PCI: 00:1d.0 subsystem <- 8086/0f34
  319. [DEBUG] PCI: 00:1d.0 cmd <- 102
  320. [DEBUG] PCI: 00:1e.0 subsystem <- 8086/0f06
  321. [DEBUG] PCI: 00:1e.0 cmd <- 106
  322. [DEBUG] PCI: 01:00.0 cmd <- 02
  323. [INFO ] done.
  324. [DEBUG] Applying SOC Thermal settings for DPTF.
  325. [INFO ] Initializing devices...
  326. [DEBUG] Root Device init
  327. [DEBUG] mainboard_ec_init
  328. [DEBUG] Chrome EC: Set SMI mask to 0x0000000000000001
  329. [DEBUG] Chrome EC: UHEPI not supported
  330. [DEBUG] Chrome EC: Set WAKE mask to 0x0000000000000000
  331. [DEBUG] Root Device init finished in 1 msecs
  332. [DEBUG] CPU_CLUSTER: 0 init
  333. [DEBUG] MTRR: Physical address space:
  334. [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
  335. [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
  336. [DEBUG] 0x00000000000c0000 - 0x000000007b7fffff size 0x7b740000 type 6
  337. [DEBUG] 0x000000007b800000 - 0x000000007fffffff size 0x04800000 type 0
  338. [DEBUG] 0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 1
  339. [DEBUG] 0x0000000090000000 - 0x00000000ffffffff size 0x70000000 type 0
  340. [DEBUG] 0x0000000100000000 - 0x000000017fffffff size 0x80000000 type 6
  341. [DEBUG] MTRR: Fixed MSR 0x250 0x0606060606060606
  342. [DEBUG] MTRR: Fixed MSR 0x258 0x0606060606060606
  343. [DEBUG] MTRR: Fixed MSR 0x259 0x0000000000000000
  344. [DEBUG] MTRR: Fixed MSR 0x268 0x0606060606060606
  345. [DEBUG] MTRR: Fixed MSR 0x269 0x0606060606060606
  346. [DEBUG] MTRR: Fixed MSR 0x26a 0x0606060606060606
  347. [DEBUG] MTRR: Fixed MSR 0x26b 0x0606060606060606
  348. [DEBUG] MTRR: Fixed MSR 0x26c 0x0606060606060606
  349. [DEBUG] MTRR: Fixed MSR 0x26d 0x0606060606060606
  350. [DEBUG] MTRR: Fixed MSR 0x26e 0x0606060606060606
  351. [DEBUG] MTRR: Fixed MSR 0x26f 0x0606060606060606
  352. [DEBUG] CPU physical address size: 36 bits
  353. [DEBUG] MTRR: default type WB/UC MTRR counts: 6/5.
  354. [DEBUG] MTRR: UC selected as default type.
  355. [DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
  356. [DEBUG] MTRR: 1 base 0x000000007b800000 mask 0x0000000fff800000 type 0
  357. [DEBUG] MTRR: 2 base 0x000000007c000000 mask 0x0000000ffc000000 type 0
  358. [DEBUG] MTRR: 3 base 0x0000000080000000 mask 0x0000000ff0000000 type 1
  359. [DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000000f80000000 type 6
  360.  
  361. [DEBUG] MTRR check
  362. [DEBUG] Fixed MTRRs : Enabled
  363. [DEBUG] Variable MTRRs: Enabled
  364.  
  365. [INFO ] Turbo is available but hidden
  366. [INFO ] Turbo is available and visible
  367. [DEBUG] Setting up SMI for CPU
  368. [INFO ] Will perform SMM setup.
  369. [INFO ] CPU: Intel(R) Celeron(R) CPU N2840 @ 2.16GHz.
  370. [INFO ] LAPIC 0x0 in XAPIC mode.
  371. [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
  372. [DEBUG] Processing 18 relocs. Offset value of 0x00030000
  373. [DEBUG] Attempting to start 1 APs
  374. [DEBUG] Waiting for 10ms after sending INIT.
  375. [DEBUG] Waiting for SIPI to complete...
  376. [DEBUG] done.
  377. [DEBUG] Waiting for SIPI to complete...
  378. [DEBUG] done.
  379. [INFO ] LAPIC 0x2 in XAPIC mode.
  380. [INFO ] AP: slot 1 apic_id 2, MCU rev: 0x00000838
  381. [DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e0 memsize: 0x1e0
  382. [DEBUG] Processing 11 relocs. Offset value of 0x00038000
  383. [DEBUG] smm_module_setup_stub: stack_top = 0x7b001000
  384. [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
  385. [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c
  386. [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
  387. [DEBUG] SMM Module: stub loaded at 38000. Will call 0x7af91cd6
  388. [DEBUG] Installing permanent SMM handler to 0x7b000000
  389. [DEBUG] FX_SAVE [0x7b6ffc00-0x7b700000]
  390. [DEBUG] HANDLER [0x7b6fb000-0x7b6ff048]
  391.  
  392. [DEBUG] CPU 0
  393. [DEBUG] ss0 [0x7b6fac00-0x7b6fb000]
  394. [DEBUG] stub0 [0x7b6f3000-0x7b6f31e0]
  395.  
  396. [DEBUG] CPU 1
  397. [DEBUG] ss1 [0x7b6fa800-0x7b6fac00]
  398. [DEBUG] stub1 [0x7b6f2c00-0x7b6f2de0]
  399.  
  400. [DEBUG] stacks [0x7b000000-0x7b001000]
  401. [DEBUG] Loading module at 0x7b6fb000 with entry 0x7b6fbaff. filesize: 0x3f38 memsize: 0x4048
  402. [DEBUG] Processing 236 relocs. Offset value of 0x7b6fb000
  403. [DEBUG] Loading module at 0x7b6f3000 with entry 0x7b6f3000. filesize: 0x1e0 memsize: 0x1e0
  404. [DEBUG] Processing 11 relocs. Offset value of 0x7b6f3000
  405. [DEBUG] smm_module_setup_stub: stack_top = 0x7b001000
  406. [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
  407. [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c
  408. [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x700000
  409. [DEBUG] SMM Module: placing smm entry code at 7b6f2c00, cpu # 0x1
  410. [DEBUG] SMM Module: stub loaded at 7b6f3000. Will call 0x7b6fbaff
  411. [DEBUG] Initializing Southbridge SMI...SMI_STS: PM1
  412. [DEBUG] USB PRBTNOR PWRBTN GPE0a_STS: SUS_GPIO_1
  413. [DEBUG] ALT_GPIO_SMI: SUS_GPIO_1
  414. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b6eb000, cpu = 0
  415. [DEBUG] Relocation complete.
  416. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b6eac00, cpu = 1
  417. [INFO ] microcode: Update skipped, already up-to-date
  418. [DEBUG] Relocation complete.
  419. [INFO ] microcode: Update skipped, already up-to-date
  420. [INFO ] Initializing CPU #0
  421. [DEBUG] CPU: vendor Intel device 30678
  422. [DEBUG] CPU: family 06, model 37, stepping 08
  423. [DEBUG] Init BayTrail core.
  424. [DEBUG] VMX status: enabled
  425. [DEBUG] IA32_FEATURE_CONTROL status: locked
  426. [INFO ] CPU #0 initialized
  427. [INFO ] Initializing CPU #1
  428. [DEBUG] CPU: vendor Intel device 30678
  429. [DEBUG] CPU: family 06, model 37, stepping 08
  430. [DEBUG] Init BayTrail core.
  431. [INFO ] Turbo is available and visible
  432. [DEBUG] VMX status: enabled
  433. [DEBUG] IA32_FEATURE_CONTROL status: locked
  434. [INFO ] CPU #1 initialized
  435. [INFO ] bsp_do_flight_plan done after 0 msecs.
  436. [DEBUG] Enabling SMIs.
  437. [DEBUG] GPIO_ROUT = 00024000
  438. [DEBUG] ALT_GPIO_SMI = 00000080
  439. [DEBUG] CPU_CLUSTER: 0 init finished in 10 msecs
  440. [DEBUG] PCI: 00:02.0 init
  441. [INFO ] CBFS: Found 'vbt.bin' @0x50d40 size 0x48e in mcache @0x7afdd228
  442. [INFO ] Found a VBT of 4608 bytes after decompression
  443. [INFO ] GMA: Found VBT in CBFS
  444. [INFO ] GMA: Found valid VBT in CBFS
  445. [INFO ] GFX: Pre VBIOS Init
  446. [INFO ] GFX: Power Management Init
  447. [INFO ] GFX: Initialize PIPEA
  448. [INFO ] GFX: Post VBIOS Init
  449. [DEBUG] PCI: 00:02.0 init finished in 1 msecs
  450. [DEBUG] PCI: 00:12.0 init
  451. [DEBUG] Overriding SD Card controller caps.
  452. [DEBUG] PCI: 00:12.0 init finished in 0 msecs
  453. [DEBUG] PCI: 00:14.0 init
  454. [INFO ] USB: Route ports to XHCI controller
  455. [DEBUG] PCI: 00:14.0 init finished in 0 msecs
  456. [DEBUG] PCI: 00:15.0 init
  457. [DEBUG] LPE Audio codec clock set to 25MHz.
  458. [DEBUG] PCI: 00:15.0 init finished in 0 msecs
  459. [DEBUG] PCI: 00:17.0 init
  460. [DEBUG] eMMC init
  461. [DEBUG] PCI: 00:17.0 init finished in 0 msecs
  462. [DEBUG] PCI: 00:18.0 init
  463. [DEBUG] PCI: 00:18.0 init finished in 0 msecs
  464. [DEBUG] PCI: 00:18.1 init
  465. [DEBUG] Releasing I2C device from reset.
  466. [DEBUG] PCI: 00:18.1 init finished in 0 msecs
  467. [DEBUG] PCI: 00:18.2 init
  468. [DEBUG] Releasing I2C device from reset.
  469. [DEBUG] PCI: 00:18.2 init finished in 0 msecs
  470. [DEBUG] PCI: 00:1b.0 init
  471. [DEBUG] codec mask = 4
  472. [DEBUG] HDA: Initializing codec #2
  473. [DEBUG] HDA: codec viddid: 80862882
  474. [DEBUG] HDA: verb loaded.
  475. [DEBUG] PCI: 00:1b.0 init finished in 3 msecs
  476. [DEBUG] PCI: 00:1c.0 init
  477. [DEBUG] PCI: 00:1c.0 init finished in 0 msecs
  478. [DEBUG] PCI: 00:1d.0 init
  479. [DEBUG] PCI: 00:1d.0: Disabling device: 1d.0
  480. [DEBUG] Power management CAP offset 0x70.
  481. [DEBUG] PCI: 00:1d.0 init finished in 0 msecs
  482. [DEBUG] PCI: 00:1e.0 init
  483. [DEBUG] PCI: 00:1e.0 init finished in 0 msecs
  484. [DEBUG] PCI: 00:1f.0 init
  485. [DEBUG] RTC Init
  486. [DEBUG] Disabling slp_x stretching.
  487. [DEBUG] PCI: 00:1f.0 init finished in 0 msecs
  488. [DEBUG] PCI: 01:00.0 init
  489. [DEBUG] PCI: 01:00.0 init finished in 0 msecs
  490. [DEBUG] PNP: 00ff.0 init
  491. [DEBUG] Google Chrome EC: Initializing
  492. [DEBUG] Google Chrome EC: version:
  493. [DEBUG] ro: swanky_v1.6.197-c5a86fe
  494. [DEBUG] rw: swanky_v1.6.205-92b7845
  495. [DEBUG] running image: 2
  496. [INFO ] CBFS: Found 'ecrw.hash' @0x50cc0 size 0x20 in mcache @0x7afdd204
  497. [DEBUG] ChromeEC SW Sync: Expected hash: 4439807613e3c0d01e43ed9468f5d96bd644cab9ac0b9e3eb38549b1d2373f3d
  498. [DEBUG] ChromeEC: Getting hash:
  499. [DEBUG] ChromeEC SW Sync: current EC_RW hash: 4439807613e3c0d01e43ed9468f5d96bd644cab9ac0b9e3eb38549b1d2373f3d
  500. [DEBUG] ChromeEC SW Sync: EC_RW is up to date
  501. [DEBUG] PNP: 00ff.0 init finished in 3 msecs
  502. [INFO ] Devices initialized
  503. [DEBUG] BS: BS_DEV_INIT run times (exec / console): 21 / 0 ms
  504. [DEBUG] FMAP: area SMMSTORE found @ 5c0000 (262144 bytes)
  505. [DEBUG] smm store: 4 # blocks with size 0x10000
  506. [INFO ] SMMSTORE: Setting up SMI handler
  507. [INFO ] Found TPM SLB9635 TT 1.2 by Infineon
  508. [DEBUG] TPM: Startup
  509. [DEBUG] TPM: command 0x99 returned 0x0
  510. [DEBUG] TPM: Asserting physical presence
  511. [DEBUG] TPM: command 0x4000000a returned 0x0
  512. [DEBUG] TPM: command 0x65 returned 0x0
  513. [DEBUG] TPM: flags disable=0, deactivated=0, nvlocked=1
  514. [INFO ] TPM: setup succeeded
  515. [DEBUG] BS: BS_DEV_INIT exit times (exec / console): 9 / 0 ms
  516. [INFO ] Finalize devices...
  517. [INFO ] Devices finalized
  518. [INFO ] CBFS: Found 'fallback/dsdt.aml' @0x3a040 size 0x3eca in mcache @0x7afdd1b8
  519. [WARN ] CBFS: 'fallback/slic' not found.
  520. [INFO ] ACPI: Writing ACPI tables at 7af2a000.
  521. [DEBUG] ACPI: * FACS
  522. [DEBUG] ACPI: * DSDT
  523. [DEBUG] ACPI: * FADT
  524. [DEBUG] SCI is IRQ9
  525. [DEBUG] ACPI: added table 1/32, length now 40
  526. [DEBUG] ACPI: * SSDT
  527. [INFO ] Turbo is available and visible
  528. [DEBUG] PSS: 2167MHz power 7000 control 0x1f4e status 0x1f4e
  529. [DEBUG] PSS: 2166MHz power 7000 control 0x1a45 status 0x1a45
  530. [DEBUG] PSS: 1999MHz power 6312 control 0x1843 status 0x1843
  531. [DEBUG] PSS: 1833MHz power 5649 control 0x163f status 0x163f
  532. [DEBUG] PSS: 1666MHz power 5016 control 0x143c status 0x143c
  533. [DEBUG] PSS: 1499MHz power 4412 control 0x1239 status 0x1239
  534. [DEBUG] PSS: 1333MHz power 3827 control 0x1035 status 0x1035
  535. [DEBUG] PSS: 1166MHz power 3268 control 0xe32 status 0xe32
  536. [DEBUG] PSS: 999MHz power 2733 control 0xc2f status 0xc2f
  537. [DEBUG] PSS: 833MHz power 2220 control 0xa2b status 0xa2b
  538. [DEBUG] PSS: 666MHz power 1729 control 0x828 status 0x828
  539. [DEBUG] PSS: 499MHz power 1263 control 0x624 status 0x624
  540. [INFO ] Turbo is available and visible
  541. [DEBUG] PSS: 2167MHz power 7000 control 0x1f4e status 0x1f4e
  542. [DEBUG] PSS: 2166MHz power 7000 control 0x1a45 status 0x1a45
  543. [DEBUG] PSS: 1999MHz power 6312 control 0x1843 status 0x1843
  544. [DEBUG] PSS: 1833MHz power 5649 control 0x163f status 0x163f
  545. [DEBUG] PSS: 1666MHz power 5016 control 0x143c status 0x143c
  546. [DEBUG] PSS: 1499MHz power 4412 control 0x1239 status 0x1239
  547. [DEBUG] PSS: 1333MHz power 3827 control 0x1035 status 0x1035
  548. [DEBUG] PSS: 1166MHz power 3268 control 0xe32 status 0xe32
  549. [DEBUG] PSS: 999MHz power 2733 control 0xc2f status 0xc2f
  550. [DEBUG] PSS: 833MHz power 2220 control 0xa2b status 0xa2b
  551. [DEBUG] PSS: 666MHz power 1729 control 0x828 status 0x828
  552. [DEBUG] PSS: 499MHz power 1263 control 0x624 status 0x624
  553. [DEBUG] PPI: Pending OS request: 0x9c50801c (0x127c2645)
  554. [DEBUG] PPI: OS response: CMD 0xa41ce184 = 0xf085a5b6
  555. [INFO ] \_SB_.PCI0.TPM: LPC TPM PNP: 0c31.0
  556. [ERROR] PS2K: Bad resp from EC. Vivaldi disabled!
  557. [DEBUG] ACPI: added table 2/32, length now 44
  558. [DEBUG] ACPI: * MCFG
  559. [DEBUG] ACPI: added table 3/32, length now 48
  560. [DEBUG] ACPI: * TCPA
  561. [DEBUG] TCPA log created at 0x7af1a000
  562. [DEBUG] ACPI: added table 4/32, length now 52
  563. [DEBUG] ACPI: * MADT
  564. [DEBUG] ACPI: added table 5/32, length now 56
  565. [DEBUG] current = 7af2f2f0
  566. [DEBUG] ACPI: * HPET
  567. [DEBUG] ACPI: added table 6/32, length now 60
  568. [INFO ] ACPI: done.
  569. [DEBUG] ACPI tables: 21296 bytes.
  570. [DEBUG] smbios_write_tables: 7af12000
  571. [DEBUG] BIOS version set to CONFIG_LOCALVERSION: 'MrChromebox-4.18.1'
  572. [INFO ] Create SMBIOS type 16
  573. [INFO ] Create SMBIOS type 17
  574. [INFO ] Create SMBIOS type 20
  575. [INFO ] Root Device (Google Swanky)
  576. [INFO ] PCI: 01:00.0 (unknown)
  577. [DEBUG] SMBIOS tables: 978 bytes.
  578. [DEBUG] Writing table forward entry at 0x00000500
  579. [DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum a4e9
  580. [DEBUG] Writing coreboot table at 0x7af4e000
  581. [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
  582. [DEBUG] 1. 0000000000001000-000000000009ffff: RAM
  583. [DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED
  584. [DEBUG] 3. 0000000000100000-000000001fffffff: RAM
  585. [DEBUG] 4. 0000000020000000-00000000200fffff: RESERVED
  586. [DEBUG] 5. 0000000020100000-000000007af11fff: RAM
  587. [DEBUG] 6. 000000007af12000-000000007af79fff: CONFIGURATION TABLES
  588. [DEBUG] 7. 000000007af7a000-000000007afcbfff: RAMSTAGE
  589. [DEBUG] 8. 000000007afcc000-000000007affffff: CONFIGURATION TABLES
  590. [DEBUG] 9. 000000007b000000-000000007fffffff: RESERVED
  591. [DEBUG] 10. 00000000e0000000-00000000efffffff: RESERVED
  592. [DEBUG] 11. 00000000feb00000-00000000febfffff: RESERVED
  593. [DEBUG] 12. 00000000fed01000-00000000fed01fff: RESERVED
  594. [DEBUG] 13. 00000000fed03000-00000000fed03fff: RESERVED
  595. [DEBUG] 14. 00000000fed05000-00000000fed05fff: RESERVED
  596. [DEBUG] 15. 00000000fed08000-00000000fed08fff: RESERVED
  597. [DEBUG] 16. 00000000fed0c000-00000000fed0ffff: RESERVED
  598. [DEBUG] 17. 00000000fed1c000-00000000fed1cfff: RESERVED
  599. [DEBUG] 18. 00000000fed40000-00000000fed44fff: RESERVED
  600. [DEBUG] 19. 00000000fef00000-00000000feffffff: RESERVED
  601. [DEBUG] 20. 0000000100000000-000000017fffffff: RAM
  602. [DEBUG] Wrote coreboot table at: 0x7af4e000, 0x52c bytes, checksum b7bf
  603. [DEBUG] coreboot table: 1348 bytes.
  604. [DEBUG] IMD ROOT 0. 0x7afff000 0x00001000
  605. [DEBUG] IMD SMALL 1. 0x7affe000 0x00001000
  606. [DEBUG] CONSOLE 2. 0x7afde000 0x00020000
  607. [DEBUG] RO MCACHE 3. 0x7afdd000 0x00000374
  608. [DEBUG] TIME STAMP 4. 0x7afdc000 0x00000910
  609. [DEBUG] MEM INFO 5. 0x7afdb000 0x00000768
  610. [DEBUG] MRC DATA 6. 0x7afd9000 0x0000166b
  611. [DEBUG] AFTER CAR 7. 0x7afcc000 0x0000d000
  612. [DEBUG] RAMSTAGE 8. 0x7af79000 0x00053000
  613. [DEBUG] SMM BACKUP 9. 0x7af69000 0x00010000
  614. [DEBUG] IGD OPREGION10. 0x7af66000 0x00002e13
  615. [DEBUG] SMM COMBUFFER11. 0x7af56000 0x00010000
  616. [DEBUG] COREBOOT 12. 0x7af4e000 0x00008000
  617. [DEBUG] ACPI 13. 0x7af2a000 0x00024000
  618. [DEBUG] TCPA TCGLOG14. 0x7af1a000 0x00010000
  619. [DEBUG] SMBIOS 15. 0x7af12000 0x00008000
  620. [DEBUG] IMD small region:
  621. [DEBUG] IMD ROOT 0. 0x7affec00 0x00000400
  622. [DEBUG] VPD 1. 0x7affeb40 0x000000bf
  623. [DEBUG] FMAP 2. 0x7affea00 0x00000134
  624. [DEBUG] POWER STATE 3. 0x7affe9e0 0x00000020
  625. [DEBUG] ROMSTAGE 4. 0x7affe9c0 0x00000004
  626. [DEBUG] ROMSTG STCK 5. 0x7affe920 0x00000088
  627. [DEBUG] ACPI GNVS 6. 0x7affe820 0x000000e8
  628. [DEBUG] TPM PPI 7. 0x7affe6c0 0x0000015a
  629. [DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 5 / 0 ms
  630. [INFO ] CBFS: Found 'fallback/payload' @0x56c40 size 0xc7760 in mcache @0x7afdd2c4
  631. [DEBUG] Checking segment from ROM address 0xffe5ae6c
  632. [DEBUG] Checking segment from ROM address 0xffe5ae88
  633. [DEBUG] Loading segment from ROM address 0xffe5ae6c
  634. [DEBUG] code (compression=1)
  635. [DEBUG] New segment dstaddr 0x00800000 memsize 0x590000 srcaddr 0xffe5aea4 filesize 0xc7728
  636. [DEBUG] Loading Segment: addr: 0x00800000 memsz: 0x0000000000590000 filesz: 0x00000000000c7728
  637. [DEBUG] using LZMA
  638. [DEBUG] Loading segment from ROM address 0xffe5ae88
  639. [DEBUG] Entry Point 0x00801626
  640. [DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 260 / 0 ms
  641. [DEBUG] Applying perf/power settings.
  642. [DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 1 / 0 ms
  643. [DEBUG] Jumping to boot code at 0x00801626(0x7af4e000)
  644.  
  645.  
  646. [NOTE ] coreboot-4.18-156-g8a76e170c64-MrChromebox-4.18.1 Thu Oct 27 13:24:50 UTC 2022 bootblock starting (log level: 7)...
  647. [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x604000.
  648. [DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 6
  649. [DEBUG] FMAP: area COREBOOT found @ 604200 (2080256 bytes)
  650. [INFO ] CBFS: mcache @0xfe002e00 built for 17 files, used 0x374 of 0x4000 bytes
  651. [INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x65d0 in mcache @0xfe002e2c
  652. [DEBUG] BS: bootblock times (exec / console): total (unknown) / 1 ms
  653.  
  654.  
  655. [NOTE ] coreboot-4.18-156-g8a76e170c64-MrChromebox-4.18.1 Thu Oct 27 13:24:50 UTC 2022 romstage starting (log level: 7)...
  656. [DEBUG] Enabling VR PS2 mode: VNN VCC
  657. [DEBUG] FMAP: area COREBOOT found @ 604200 (2080256 bytes)
  658. [INFO ] CBFS: Found 'spd.bin' @0x39c00 size 0x400 in mcache @0xfe002f98
  659. [DEBUG] ram_id=3, total_spds: 4
  660. [DEBUG] pm1_sts: 2000 pm1_en: 0000 pm1_cnt: 00000000
  661. [DEBUG] gpe0_sts: 00002000 gpe0_en: 00000000 tco_sts: 00000000
  662. [DEBUG] prsts: 04450910 gen_pmcon1: 00201238 gen_pmcon2: 00000000
  663. [DEBUG] prev_sleep_state = S0
  664. [DEBUG] FMAP: area RW_MRC_CACHE found @ 5b0000 (65536 bytes)
  665. [INFO ] CBFS: Found 'mrc.bin' @0x19adc0 size 0x11218 in mcache @0xfe0030f0
  666. BayTrail-MD MRC wrapper v5
  667. Training for Memory Down designs.
  668. Applying weaker ODT settings. DRAM ODT is 120.
  669. [DEBUG] CBMEM:
  670. [DEBUG] IMD: root @ 0x7afff000 254 entries.
  671. [DEBUG] IMD: root @ 0x7affec00 62 entries.
  672. [DEBUG] FMAP: area RO_VPD found @ 600000 (16384 bytes)
  673. [ERROR] init_vpd_rdev: No RW_VPD FMAP section.
  674. [DEBUG] External stage cache:
  675. [DEBUG] IMD: root @ 0x7b7ff000 254 entries.
  676. [DEBUG] IMD: root @ 0x7b7fec00 62 entries.
  677. [INFO ] MRC v0.97
  678. [INFO ] 2 channels of DDR3 @ 1333MHz
  679. [DEBUG] CBMEM entry for DIMM info: 0x7afdb000
  680. [DEBUG] MRC Wrapper returned 0
  681. [DEBUG] MRC data at 0xfe00965f 5719 bytes
  682. [DEBUG] SMM Memory Map
  683. [DEBUG] SMRAM : 0x7b000000 0x800000
  684. [DEBUG] Subregion 0: 0x7b000000 0x700000
  685. [DEBUG] Subregion 1: 0x7b700000 0x100000
  686. [DEBUG] Subregion 2: 0x7b800000 0x0
  687. [DEBUG] Normal boot
  688. [INFO ] CBFS: Found 'fallback/postcar' @0x51580 size 0x566c in mcache @0xfe003080
  689. [DEBUG] Loading module at 0x7afcd000 with entry 0x7afcd031. filesize: 0x52e0 memsize: 0xb618
  690. [DEBUG] Processing 211 relocs. Offset value of 0x78fcd000
  691. [DEBUG] BS: romstage times (exec / console): total (unknown) / 1 ms
  692.  
  693.  
  694. [NOTE ] coreboot-4.18-156-g8a76e170c64-MrChromebox-4.18.1 Thu Oct 27 13:24:50 UTC 2022 postcar starting (log level: 7)...
  695. [DEBUG] Normal boot
  696. [DEBUG] FMAP: area COREBOOT found @ 604200 (2080256 bytes)
  697. [INFO ] CBFS: Found 'fallback/ramstage' @0x1ff40 size 0x1937f in mcache @0x7afdd0dc
  698. [DEBUG] Loading module at 0x7af7a000 with entry 0x7af7a000. filesize: 0x3a978 memsize: 0x51390
  699. [DEBUG] Processing 3521 relocs. Offset value of 0x76f7a000
  700. [DEBUG] BS: postcar times (exec / console): total (unknown) / 0 ms
  701.  
  702.  
  703. [NOTE ] coreboot-4.18-156-g8a76e170c64-MrChromebox-4.18.1 Thu Oct 27 13:24:50 UTC 2022 ramstage starting (log level: 7)...
  704. [DEBUG] Normal boot
  705. [DEBUG] FMAP: area COREBOOT found @ 604200 (2080256 bytes)
  706. [INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x6700 size 0x19800 in mcache @0x7afdd0ac
  707. [DEBUG] microcode: sig=0x30678 pf=0x8 revision=0x838
  708. [DEBUG] BYT: cpuid 00030678 cpus 2 rid 0e step C0
  709. [DEBUG] msr(17) = 000c000090341f4e
  710. [DEBUG] msr(ce) = 0000060000001a00
  711. [DEBUG] ModPHY init entry
  712. [DEBUG] SOC B0 and later ModPhy Table programming
  713. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  714. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  715. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  716. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  717. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  718. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  719. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  720. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  721. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  722. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  723. [DEBUG] ModPHY init done
  724. [DEBUG] Tri-state TDO and TMS
  725. [DEBUG] Initializing sideband SCC registers.
  726. [DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 2 / 0 ms
  727. [INFO ] Enumerating buses...
  728. [DEBUG] Root Device scanning...
  729. [DEBUG] CPU_CLUSTER: 0 enabled
  730. [DEBUG] DOMAIN: 0000 enabled
  731. [DEBUG] DOMAIN: 0000 scanning...
  732. [DEBUG] PCI: pci_scan_bus for bus 00
  733. [DEBUG] PCI: 00:00.0 [8086/0f00] enabled
  734. [DEBUG] PCI: 00:02.0 [8086/0f31] enabled
  735. [DEBUG] PCI: 00:10.0: Disabling device: 10.0
  736. [DEBUG] Power management CAP offset 0x80.
  737. [DEBUG] PCI: 00:11.0: Disabling device: 11.0
  738. [DEBUG] Power management CAP offset 0x80.
  739. [DEBUG] PCI: 00:12.0 [8086/0f16] enabled
  740. [INFO ] PCI: Static device PCI: 00:13.0 not found, disabling it.
  741. [DEBUG] PCI: 00:14.0 [8086/0f35] enabled
  742. [DEBUG] PCI: 00:15.0 [8086/0f28] enabled
  743. [DEBUG] PCI: 00:17.0 [8086/0f50] enabled
  744. [DEBUG] PCI: 00:18.0 [8086/0f40] enabled
  745. [DEBUG] PCI: 00:18.1 [8086/0f41] enabled
  746. [DEBUG] PCI: 00:18.2 [8086/0f42] enabled
  747. [DEBUG] PCI: 00:18.3: Disabling device: 18.3
  748. [DEBUG] Power management CAP offset 0x80.
  749. [DEBUG] PCI: 00:18.4: Disabling device: 18.4
  750. [DEBUG] Power management CAP offset 0x80.
  751. [DEBUG] PCI: 00:18.5: Disabling device: 18.5
  752. [DEBUG] Power management CAP offset 0x80.
  753. [DEBUG] PCI: 00:18.5 [8086/0f45] disabled
  754. [DEBUG] PCI: 00:18.6: Disabling device: 18.6
  755. [DEBUG] Power management CAP offset 0x80.
  756. [DEBUG] PCI: 00:18.6 [8086/0f46] disabled
  757. [DEBUG] PCI: 00:18.7: Disabling device: 18.7
  758. [DEBUG] Power management CAP offset 0x80.
  759. [DEBUG] PCI: 00:1a.0: Disabling device: 1a.0
  760. [DEBUG] PCI: 00:1b.0 [8086/0f04] enabled
  761. [DEBUG] PCI: 00:1c.0 [8086/0f48] enabled
  762. [DEBUG] No PCIe device present.
  763. [WARN ] reg_script_run_step: POLL timeout waiting for 0x328 to be 0x1000000, got 0x0
  764. [DEBUG] PCI: 00:1c.1: Disabling device: 1c.1
  765. [DEBUG] Power management CAP offset 0xa0.
  766. [DEBUG] PCI: 00:1c.1 [8086/0f4a] disabled
  767. [DEBUG] PCI: 00:1c.2: Disabling device: 1c.2
  768. [DEBUG] Power management CAP offset 0xa0.
  769. [DEBUG] PCI: 00:1c.3: Disabling device: 1c.3
  770. [DEBUG] Power management CAP offset 0xa0.
  771. [DEBUG] PCI: 00:1d.0 [8086/0f34] enabled
  772. [DEBUG] PCI: 00:1e.0 [8086/0f06] enabled
  773. [DEBUG] PCI: 00:1e.1: Disabling device: 1e.1
  774. [DEBUG] Power management CAP offset 0x80.
  775. [DEBUG] PCI: 00:1e.2: Disabling device: 1e.2
  776. [DEBUG] Power management CAP offset 0x80.
  777. [DEBUG] PCI: 00:1e.3: Disabling device: 1e.3
  778. [DEBUG] Power management CAP offset 0x80.
  779. [DEBUG] PCI: 00:1e.4: Disabling device: 1e.4
  780. [DEBUG] Power management CAP offset 0x80.
  781. [DEBUG] PCI: 00:1e.4 [8086/0f0c] disabled
  782. [DEBUG] PCI: 00:1e.5: Disabling device: 1e.5
  783. [DEBUG] Power management CAP offset 0x80.
  784. [DEBUG] PCI: 00:1e.5 [8086/0f0e] disabled
  785. [DEBUG] PCI: 00:1f.0 [8086/0f1c] enabled
  786. [DEBUG] PCI: 00:1f.3: Disabling device: 1f.3
  787. [DEBUG] Power management CAP offset 0x50.
  788. [WARN ] PCI: Leftover static devices:
  789. [WARN ] PCI: 00:10.0
  790. [WARN ] PCI: 00:11.0
  791. [WARN ] PCI: 00:13.0
  792. [WARN ] PCI: 00:18.3
  793. [WARN ] PCI: 00:18.4
  794. [WARN ] PCI: 00:18.7
  795. [WARN ] PCI: 00:1a.0
  796. [WARN ] PCI: 00:1c.2
  797. [WARN ] PCI: 00:1c.3
  798. [WARN ] PCI: 00:1e.1
  799. [WARN ] PCI: 00:1e.2
  800. [WARN ] PCI: 00:1e.3
  801. [WARN ] PCI: 00:1f.3
  802. [WARN ] PCI: Check your devicetree.cb.
  803. [DEBUG] PCI: 00:1c.0 scanning...
  804. [DEBUG] PCI: pci_scan_bus for bus 01
  805. [DEBUG] PCI: 01:00.0 [8086/08b1] enabled
  806. [INFO ] Enabling Common Clock Configuration
  807. [INFO ] ASPM: Enabled L1
  808. [INFO ] PCIe: Max_Payload_Size adjusted to 128
  809. [DEBUG] scan_bus: bus PCI: 00:1c.0 finished in 0 msecs
  810. [DEBUG] PCI: 00:1f.0 scanning...
  811. [DEBUG] PNP: 0c31.0 enabled
  812. [DEBUG] PNP: 00ff.1 enabled
  813. [DEBUG] PNP: 00ff.0 enabled
  814. [DEBUG] PNP: 00ff.0 scanning...
  815. [DEBUG] scan_bus: bus PNP: 00ff.0 finished in 0 msecs
  816. [DEBUG] scan_bus: bus PCI: 00:1f.0 finished in 0 msecs
  817. [DEBUG] scan_bus: bus DOMAIN: 0000 finished in 50 msecs
  818. [DEBUG] scan_bus: bus Root Device finished in 50 msecs
  819. [INFO ] done
  820. [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 51 / 0 ms
  821. [DEBUG] FMAP: area RW_MRC_CACHE found @ 5b0000 (65536 bytes)
  822. [DEBUG] FMAP: area RW_MRC_CACHE found @ 5b0000 (65536 bytes)
  823. [DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
  824. [INFO ] Manufacturer: ef
  825. [INFO ] SF: Detected ef 6017 with sector size 0x1000, total 0x800000
  826. [DEBUG] MRC: 'RW_MRC_CACHE' does not need update.
  827. [DEBUG] found VGA at PCI: 00:02.0
  828. [DEBUG] Setting up VGA for PCI: 00:02.0
  829. [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
  830. [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
  831. [INFO ] Allocating resources...
  832. [INFO ] Reading resources...
  833. [INFO ] Available memory above 4GB: 2048M
  834. [ERROR] PNP: 00ff.1 missing read_resources
  835. [INFO ] Done reading resources.
  836. [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
  837. [DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
  838. [DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done
  839. [DEBUG] PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  840. [DEBUG] PCI: 01:00.0 10 * [0x0 - 0x1fff] mem
  841. [DEBUG] PCI: 00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
  842. [DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
  843. [DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
  844. [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
  845. [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
  846. [DEBUG] update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
  847. [DEBUG] update_constraints: PNP: 00ff.0 00 base 00000800 limit 000009fe io (fixed)
  848. [INFO ] DOMAIN: 0000: Resource ranges:
  849. [INFO ] * Base: 1000, Size: f000, Tag: 100
  850. [DEBUG] PCI: 00:02.0 20 * [0x1000 - 0x1007] limit: 1007 io
  851. [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
  852. [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff
  853. [DEBUG] update_constraints: PCI: 00:00.0 27 base e0000000 limit efffffff mem (fixed)
  854. [DEBUG] update_constraints: PCI: 00:00.0 00 base 00000000 limit 0009ffff mem (fixed)
  855. [DEBUG] update_constraints: PCI: 00:00.0 01 base 000c0000 limit 7affffff mem (fixed)
  856. [DEBUG] update_constraints: PCI: 00:00.0 02 base 7b000000 limit 7b7fffff mem (fixed)
  857. [DEBUG] update_constraints: PCI: 00:00.0 03 base 7b800000 limit 7fffffff mem (fixed)
  858. [DEBUG] update_constraints: PCI: 00:00.0 04 base 100000000 limit 17fffffff mem (fixed)
  859. [DEBUG] update_constraints: PCI: 00:00.0 05 base 000a0000 limit 000bffff mem (fixed)
  860. [DEBUG] update_constraints: PCI: 00:00.0 06 base 000c0000 limit 000fffff mem (fixed)
  861. [DEBUG] update_constraints: PCI: 00:15.0 a8 base 20000000 limit 200fffff mem (fixed)
  862. [DEBUG] update_constraints: PCI: 00:1f.0 feb base feb00000 limit febfffff mem (fixed)
  863. [DEBUG] update_constraints: PCI: 00:1f.0 44 base fed03000 limit fed033ff mem (fixed)
  864. [DEBUG] update_constraints: PCI: 00:1f.0 4c base fed0c000 limit fed0ffff mem (fixed)
  865. [DEBUG] update_constraints: PCI: 00:1f.0 50 base fed08000 limit fed083ff mem (fixed)
  866. [DEBUG] update_constraints: PCI: 00:1f.0 54 base fed01000 limit fed013ff mem (fixed)
  867. [DEBUG] update_constraints: PCI: 00:1f.0 58 base fef00000 limit feffffff mem (fixed)
  868. [DEBUG] update_constraints: PCI: 00:1f.0 5c base fed05000 limit fed057ff mem (fixed)
  869. [DEBUG] update_constraints: PCI: 00:1f.0 f0 base fed1c000 limit fed1c3ff mem (fixed)
  870. [DEBUG] update_constraints: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed)
  871. [INFO ] DOMAIN: 0000: Resource ranges:
  872. [INFO ] * Base: 80000000, Size: 60000000, Tag: 200
  873. [INFO ] * Base: f0000000, Size: eb00000, Tag: 200
  874. [INFO ] * Base: fec00000, Size: 101000, Tag: 200
  875. [INFO ] * Base: fed02000, Size: 1000, Tag: 200
  876. [INFO ] * Base: fed04000, Size: 1000, Tag: 200
  877. [INFO ] * Base: fed06000, Size: 2000, Tag: 200
  878. [INFO ] * Base: fed09000, Size: 3000, Tag: 200
  879. [INFO ] * Base: fed10000, Size: c000, Tag: 200
  880. [INFO ] * Base: fed1d000, Size: 23000, Tag: 200
  881. [INFO ] * Base: fed45000, Size: 1bb000, Tag: 200
  882. [INFO ] * Base: ff000000, Size: 1000000, Tag: 200
  883. [INFO ] * Base: 180000000, Size: e80000000, Tag: 100200
  884. [DEBUG] PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
  885. [DEBUG] PCI: 00:02.0 10 * [0x90000000 - 0x903fffff] limit: 903fffff mem
  886. [DEBUG] PCI: 00:15.0 10 * [0x90400000 - 0x905fffff] limit: 905fffff mem
  887. [DEBUG] PCI: 00:1c.0 20 * [0x90600000 - 0x906fffff] limit: 906fffff mem
  888. [DEBUG] PCI: 00:14.0 10 * [0x90700000 - 0x9070ffff] limit: 9070ffff mem
  889. [DEBUG] PCI: 00:18.0 10 * [0x90710000 - 0x90713fff] limit: 90713fff mem
  890. [DEBUG] PCI: 00:1b.0 10 * [0x90714000 - 0x90717fff] limit: 90717fff mem
  891. [DEBUG] PCI: 00:1e.0 10 * [0x90718000 - 0x9071bfff] limit: 9071bfff mem
  892. [DEBUG] PCI: 00:12.0 10 * [0x9071c000 - 0x9071cfff] limit: 9071cfff mem
  893. [DEBUG] PCI: 00:12.0 14 * [0x9071d000 - 0x9071dfff] limit: 9071dfff mem
  894. [DEBUG] PCI: 00:15.0 14 * [0x9071e000 - 0x9071efff] limit: 9071efff mem
  895. [DEBUG] PCI: 00:17.0 10 * [0x9071f000 - 0x9071ffff] limit: 9071ffff mem
  896. [DEBUG] PCI: 00:17.0 14 * [0x90720000 - 0x90720fff] limit: 90720fff mem
  897. [DEBUG] PCI: 00:18.0 14 * [0x90721000 - 0x90721fff] limit: 90721fff mem
  898. [DEBUG] PCI: 00:18.1 10 * [0x90722000 - 0x90722fff] limit: 90722fff mem
  899. [DEBUG] PCI: 00:18.1 14 * [0x90723000 - 0x90723fff] limit: 90723fff mem
  900. [DEBUG] PCI: 00:18.2 10 * [0x90724000 - 0x90724fff] limit: 90724fff mem
  901. [DEBUG] PCI: 00:18.2 14 * [0x90725000 - 0x90725fff] limit: 90725fff mem
  902. [DEBUG] PCI: 00:1e.0 14 * [0x90726000 - 0x90726fff] limit: 90726fff mem
  903. [DEBUG] PCI: 00:1d.0 10 * [0x90727000 - 0x907273ff] limit: 907273ff mem
  904. [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done
  905. [DEBUG] PCI: 00:1c.0 mem: base: 90600000 size: 100000 align: 20 gran: 20 limit: 906fffff
  906. [INFO ] PCI: 00:1c.0: Resource ranges:
  907. [INFO ] * Base: 90600000, Size: 100000, Tag: 200
  908. [DEBUG] PCI: 01:00.0 10 * [0x90600000 - 0x90601fff] limit: 90601fff mem
  909. [DEBUG] PCI: 00:1c.0 mem: base: 90600000 size: 100000 align: 20 gran: 20 limit: 906fffff done
  910. [INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
  911. [ERROR] PCI: 00:00.0 missing set_resources
  912. [DEBUG] PCI: 00:02.0 10 <- [0x0000000090000000 - 0x00000000903fffff] size 0x00400000 gran 0x16 mem
  913. [DEBUG] PCI: 00:02.0 18 <- [0x0000000080000000 - 0x000000008fffffff] size 0x10000000 gran 0x1c prefmem
  914. [DEBUG] PCI: 00:02.0 20 <- [0x0000000000001000 - 0x0000000000001007] size 0x00000008 gran 0x03 io
  915. [DEBUG] PCI: 00:12.0 10 <- [0x000000009071c000 - 0x000000009071cfff] size 0x00001000 gran 0x0c mem
  916. [DEBUG] PCI: 00:12.0 14 <- [0x000000009071d000 - 0x000000009071dfff] size 0x00001000 gran 0x0c mem
  917. [DEBUG] PCI: 00:14.0 10 <- [0x0000000090700000 - 0x000000009070ffff] size 0x00010000 gran 0x10 mem64
  918. [DEBUG] PCI: 00:15.0 10 <- [0x0000000090400000 - 0x00000000905fffff] size 0x00200000 gran 0x15 mem
  919. [DEBUG] PCI: 00:15.0 14 <- [0x000000009071e000 - 0x000000009071efff] size 0x00001000 gran 0x0c mem
  920. [DEBUG] PCI: 00:17.0 10 <- [0x000000009071f000 - 0x000000009071ffff] size 0x00001000 gran 0x0c mem
  921. [DEBUG] PCI: 00:17.0 14 <- [0x0000000090720000 - 0x0000000090720fff] size 0x00001000 gran 0x0c mem
  922. [DEBUG] PCI: 00:18.0 10 <- [0x0000000090710000 - 0x0000000090713fff] size 0x00004000 gran 0x0e mem
  923. [DEBUG] PCI: 00:18.0 14 <- [0x0000000090721000 - 0x0000000090721fff] size 0x00001000 gran 0x0c mem
  924. [DEBUG] PCI: 00:18.1 10 <- [0x0000000090722000 - 0x0000000090722fff] size 0x00001000 gran 0x0c mem
  925. [DEBUG] PCI: 00:18.1 14 <- [0x0000000090723000 - 0x0000000090723fff] size 0x00001000 gran 0x0c mem
  926. [DEBUG] PCI: 00:18.2 10 <- [0x0000000090724000 - 0x0000000090724fff] size 0x00001000 gran 0x0c mem
  927. [DEBUG] PCI: 00:18.2 14 <- [0x0000000090725000 - 0x0000000090725fff] size 0x00001000 gran 0x0c mem
  928. [DEBUG] PCI: 00:1b.0 10 <- [0x0000000090714000 - 0x0000000090717fff] size 0x00004000 gran 0x0e mem64
  929. [DEBUG] PCI: 00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 01 io
  930. [DEBUG] PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
  931. [DEBUG] PCI: 00:1c.0 20 <- [0x0000000090600000 - 0x00000000906fffff] size 0x00100000 gran 0x14 bus 01 mem
  932. [DEBUG] PCI: 01:00.0 10 <- [0x0000000090600000 - 0x0000000090601fff] size 0x00002000 gran 0x0d mem64
  933. [DEBUG] PCI: 00:1d.0 10 <- [0x0000000090727000 - 0x00000000907273ff] size 0x00000400 gran 0x0a mem
  934. [DEBUG] PCI: 00:1e.0 10 <- [0x0000000090718000 - 0x000000009071bfff] size 0x00004000 gran 0x0e mem
  935. [DEBUG] PCI: 00:1e.0 14 <- [0x0000000090726000 - 0x0000000090726fff] size 0x00001000 gran 0x0c mem
  936. [INFO ] Done setting resources.
  937. [INFO ] Done allocating resources.
  938. [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 1 / 0 ms
  939. [INFO ] Enabling resources...
  940. [DEBUG] PCI: 00:02.0 subsystem <- 8086/0f31
  941. [DEBUG] PCI: 00:02.0 cmd <- 03
  942. [DEBUG] PCI: 00:12.0 subsystem <- 8086/0f16
  943. [DEBUG] PCI: 00:12.0 cmd <- 106
  944. [DEBUG] PCI: 00:14.0 subsystem <- 8086/0f35
  945. [DEBUG] PCI: 00:14.0 cmd <- 102
  946. [DEBUG] PCI: 00:15.0 subsystem <- 8086/0f28
  947. [DEBUG] PCI: 00:15.0 cmd <- 102
  948. [DEBUG] PCI: 00:17.0 subsystem <- 8086/0f50
  949. [DEBUG] PCI: 00:17.0 cmd <- 106
  950. [DEBUG] PCI: 00:18.0 subsystem <- 8086/0f40
  951. [DEBUG] PCI: 00:18.0 cmd <- 106
  952. [DEBUG] PCI: 00:18.1 subsystem <- 8086/0f41
  953. [DEBUG] PCI: 00:18.1 cmd <- 102
  954. [DEBUG] PCI: 00:18.2 subsystem <- 8086/0f42
  955. [DEBUG] PCI: 00:18.2 cmd <- 102
  956. [DEBUG] PCI: 00:1b.0 subsystem <- 8086/0f04
  957. [DEBUG] PCI: 00:1b.0 cmd <- 102
  958. [DEBUG] PCI: 00:1c.0 bridge ctrl <- 0013
  959. [DEBUG] PCI: 00:1c.0 subsystem <- 8086/0f48
  960. [DEBUG] PCI: 00:1c.0 cmd <- 106
  961. [DEBUG] PCI: 00:1d.0 subsystem <- 8086/0f34
  962. [DEBUG] PCI: 00:1d.0 cmd <- 102
  963. [DEBUG] PCI: 00:1e.0 subsystem <- 8086/0f06
  964. [DEBUG] PCI: 00:1e.0 cmd <- 106
  965. [DEBUG] PCI: 01:00.0 cmd <- 02
  966. [INFO ] done.
  967. [DEBUG] Applying SOC Thermal settings for DPTF.
  968. [INFO ] Initializing devices...
  969. [DEBUG] Root Device init
  970. [DEBUG] mainboard_ec_init
  971. [DEBUG] Chrome EC: Set SMI mask to 0x0000000000000001
  972. [DEBUG] Chrome EC: UHEPI not supported
  973. [DEBUG] Chrome EC: Set WAKE mask to 0x0000000000000000
  974. [DEBUG] Root Device init finished in 1 msecs
  975. [DEBUG] CPU_CLUSTER: 0 init
  976. [DEBUG] MTRR: Physical address space:
  977. [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
  978. [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
  979. [DEBUG] 0x00000000000c0000 - 0x000000007b7fffff size 0x7b740000 type 6
  980. [DEBUG] 0x000000007b800000 - 0x000000007fffffff size 0x04800000 type 0
  981. [DEBUG] 0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 1
  982. [DEBUG] 0x0000000090000000 - 0x00000000ffffffff size 0x70000000 type 0
  983. [DEBUG] 0x0000000100000000 - 0x000000017fffffff size 0x80000000 type 6
  984. [DEBUG] MTRR: Fixed MSR 0x250 0x0606060606060606
  985. [DEBUG] MTRR: Fixed MSR 0x258 0x0606060606060606
  986. [DEBUG] MTRR: Fixed MSR 0x259 0x0000000000000000
  987. [DEBUG] MTRR: Fixed MSR 0x268 0x0606060606060606
  988. [DEBUG] MTRR: Fixed MSR 0x269 0x0606060606060606
  989. [DEBUG] MTRR: Fixed MSR 0x26a 0x0606060606060606
  990. [DEBUG] MTRR: Fixed MSR 0x26b 0x0606060606060606
  991. [DEBUG] MTRR: Fixed MSR 0x26c 0x0606060606060606
  992. [DEBUG] MTRR: Fixed MSR 0x26d 0x0606060606060606
  993. [DEBUG] MTRR: Fixed MSR 0x26e 0x0606060606060606
  994. [DEBUG] MTRR: Fixed MSR 0x26f 0x0606060606060606
  995. [DEBUG] CPU physical address size: 36 bits
  996. [DEBUG] MTRR: default type WB/UC MTRR counts: 6/5.
  997. [DEBUG] MTRR: UC selected as default type.
  998. [DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
  999. [DEBUG] MTRR: 1 base 0x000000007b800000 mask 0x0000000fff800000 type 0
  1000. [DEBUG] MTRR: 2 base 0x000000007c000000 mask 0x0000000ffc000000 type 0
  1001. [DEBUG] MTRR: 3 base 0x0000000080000000 mask 0x0000000ff0000000 type 1
  1002. [DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000000f80000000 type 6
  1003.  
  1004. [DEBUG] MTRR check
  1005. [DEBUG] Fixed MTRRs : Enabled
  1006. [DEBUG] Variable MTRRs: Enabled
  1007.  
  1008. [INFO ] Turbo is available but hidden
  1009. [INFO ] Turbo is available and visible
  1010. [DEBUG] Setting up SMI for CPU
  1011. [INFO ] Will perform SMM setup.
  1012. [INFO ] CPU: Intel(R) Celeron(R) CPU N2840 @ 2.16GHz.
  1013. [INFO ] LAPIC 0x0 in XAPIC mode.
  1014. [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
  1015. [DEBUG] Processing 18 relocs. Offset value of 0x00030000
  1016. [DEBUG] Attempting to start 1 APs
  1017. [DEBUG] Waiting for 10ms after sending INIT.
  1018. [DEBUG] Waiting for SIPI to complete...
  1019. [DEBUG] done.
  1020. [DEBUG] Waiting for SIPI to complete...
  1021. [DEBUG] done.
  1022. [INFO ] LAPIC 0x2 in XAPIC mode.
  1023. [INFO ] AP: slot 1 apic_id 2, MCU rev: 0x00000838
  1024. [DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e0 memsize: 0x1e0
  1025. [DEBUG] Processing 11 relocs. Offset value of 0x00038000
  1026. [DEBUG] smm_module_setup_stub: stack_top = 0x7b001000
  1027. [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
  1028. [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c
  1029. [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
  1030. [DEBUG] SMM Module: stub loaded at 38000. Will call 0x7af91cd6
  1031. [DEBUG] Installing permanent SMM handler to 0x7b000000
  1032. [DEBUG] FX_SAVE [0x7b6ffc00-0x7b700000]
  1033. [DEBUG] HANDLER [0x7b6fb000-0x7b6ff048]
  1034.  
  1035. [DEBUG] CPU 0
  1036. [DEBUG] ss0 [0x7b6fac00-0x7b6fb000]
  1037. [DEBUG] stub0 [0x7b6f3000-0x7b6f31e0]
  1038.  
  1039. [DEBUG] CPU 1
  1040. [DEBUG] ss1 [0x7b6fa800-0x7b6fac00]
  1041. [DEBUG] stub1 [0x7b6f2c00-0x7b6f2de0]
  1042.  
  1043. [DEBUG] stacks [0x7b000000-0x7b001000]
  1044. [DEBUG] Loading module at 0x7b6fb000 with entry 0x7b6fbaff. filesize: 0x3f38 memsize: 0x4048
  1045. [DEBUG] Processing 236 relocs. Offset value of 0x7b6fb000
  1046. [DEBUG] Loading module at 0x7b6f3000 with entry 0x7b6f3000. filesize: 0x1e0 memsize: 0x1e0
  1047. [DEBUG] Processing 11 relocs. Offset value of 0x7b6f3000
  1048. [DEBUG] smm_module_setup_stub: stack_top = 0x7b001000
  1049. [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
  1050. [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c
  1051. [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x700000
  1052. [DEBUG] SMM Module: placing smm entry code at 7b6f2c00, cpu # 0x1
  1053. [DEBUG] SMM Module: stub loaded at 7b6f3000. Will call 0x7b6fbaff
  1054. [DEBUG] Initializing Southbridge SMI...SMI_STS: PM1
  1055. [DEBUG] USB GPE0a_STS: PME_B0
  1056. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b6eb000, cpu = 0
  1057. [DEBUG] Relocation complete.
  1058. [INFO ] microcode: Update skipped, already up-to-date
  1059. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b6eac00, cpu = 1
  1060. [DEBUG] Relocation complete.
  1061. [INFO ] microcode: Update skipped, already up-to-date
  1062. [INFO ] Initializing CPU #0
  1063. [DEBUG] CPU: vendor Intel device 30678
  1064. [DEBUG] CPU: family 06, model 37, stepping 08
  1065. [DEBUG] Init BayTrail core.
  1066. [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled
  1067. [DEBUG] IA32_FEATURE_CONTROL already locked
  1068. [INFO ] CPU #0 initialized
  1069. [INFO ] Initializing CPU #1
  1070. [DEBUG] CPU: vendor Intel device 30678
  1071. [DEBUG] CPU: family 06, model 37, stepping 08
  1072. [DEBUG] Init BayTrail core.
  1073. [INFO ] Turbo is available and visible
  1074. [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled
  1075. [DEBUG] IA32_FEATURE_CONTROL already locked
  1076. [INFO ] CPU #1 initialized
  1077. [INFO ] bsp_do_flight_plan done after 0 msecs.
  1078. [DEBUG] Enabling SMIs.
  1079. [DEBUG] GPIO_ROUT = 00024000
  1080. [DEBUG] ALT_GPIO_SMI = 00000080
  1081. [DEBUG] CPU_CLUSTER: 0 init finished in 10 msecs
  1082. [DEBUG] PCI: 00:02.0 init
  1083. [INFO ] CBFS: Found 'vbt.bin' @0x50d40 size 0x48e in mcache @0x7afdd228
  1084. [INFO ] Found a VBT of 4608 bytes after decompression
  1085. [INFO ] GMA: Found VBT in CBFS
  1086. [INFO ] GMA: Found valid VBT in CBFS
  1087. [INFO ] GFX: Pre VBIOS Init
  1088. [INFO ] GFX: Power Management Init
  1089. [INFO ] GFX: Initialize PIPEA
  1090. [INFO ] GFX: Post VBIOS Init
  1091. [DEBUG] PCI: 00:02.0 init finished in 1 msecs
  1092. [DEBUG] PCI: 00:12.0 init
  1093. [DEBUG] Overriding SD Card controller caps.
  1094. [DEBUG] PCI: 00:12.0 init finished in 0 msecs
  1095. [DEBUG] PCI: 00:14.0 init
  1096. [INFO ] USB: Route ports to XHCI controller
  1097. [DEBUG] PCI: 00:14.0 init finished in 0 msecs
  1098. [DEBUG] PCI: 00:15.0 init
  1099. [DEBUG] LPE Audio codec clock set to 25MHz.
  1100. [DEBUG] PCI: 00:15.0 init finished in 0 msecs
  1101. [DEBUG] PCI: 00:17.0 init
  1102. [DEBUG] eMMC init
  1103. [DEBUG] PCI: 00:17.0 init finished in 0 msecs
  1104. [DEBUG] PCI: 00:18.0 init
  1105. [DEBUG] PCI: 00:18.0 init finished in 0 msecs
  1106. [DEBUG] PCI: 00:18.1 init
  1107. [DEBUG] Releasing I2C device from reset.
  1108. [DEBUG] PCI: 00:18.1 init finished in 0 msecs
  1109. [DEBUG] PCI: 00:18.2 init
  1110. [DEBUG] Releasing I2C device from reset.
  1111. [DEBUG] PCI: 00:18.2 init finished in 0 msecs
  1112. [DEBUG] PCI: 00:1b.0 init
  1113. [DEBUG] codec mask = 4
  1114. [DEBUG] HDA: Initializing codec #2
  1115. [DEBUG] HDA: codec viddid: 80862882
  1116. [DEBUG] HDA: verb loaded.
  1117. [DEBUG] PCI: 00:1b.0 init finished in 3 msecs
  1118. [DEBUG] PCI: 00:1c.0 init
  1119. [DEBUG] PCI: 00:1c.0 init finished in 0 msecs
  1120. [DEBUG] PCI: 00:1d.0 init
  1121. [DEBUG] PCI: 00:1d.0: Disabling device: 1d.0
  1122. [DEBUG] Power management CAP offset 0x70.
  1123. [DEBUG] PCI: 00:1d.0 init finished in 0 msecs
  1124. [DEBUG] PCI: 00:1e.0 init
  1125. [DEBUG] PCI: 00:1e.0 init finished in 0 msecs
  1126. [DEBUG] PCI: 00:1f.0 init
  1127. [DEBUG] RTC Init
  1128. [DEBUG] Disabling slp_x stretching.
  1129. [DEBUG] PCI: 00:1f.0 init finished in 0 msecs
  1130. [DEBUG] PCI: 01:00.0 init
  1131. [DEBUG] PCI: 01:00.0 init finished in 0 msecs
  1132. [DEBUG] PNP: 00ff.0 init
  1133. [DEBUG] Google Chrome EC: Initializing
  1134. [DEBUG] Google Chrome EC: version:
  1135. [DEBUG] ro: swanky_v1.6.197-c5a86fe
  1136. [DEBUG] rw: swanky_v1.6.205-92b7845
  1137. [DEBUG] running image: 2
  1138. [INFO ] CBFS: Found 'ecrw.hash' @0x50cc0 size 0x20 in mcache @0x7afdd204
  1139. [DEBUG] ChromeEC SW Sync: Expected hash: 4439807613e3c0d01e43ed9468f5d96bd644cab9ac0b9e3eb38549b1d2373f3d
  1140. [DEBUG] ChromeEC: Getting hash:
  1141. [DEBUG] ChromeEC SW Sync: current EC_RW hash: 4439807613e3c0d01e43ed9468f5d96bd644cab9ac0b9e3eb38549b1d2373f3d
  1142. [DEBUG] ChromeEC SW Sync: EC_RW is up to date
  1143. [DEBUG] PNP: 00ff.0 init finished in 3 msecs
  1144. [INFO ] Devices initialized
  1145. [DEBUG] BS: BS_DEV_INIT run times (exec / console): 22 / 0 ms
  1146. [DEBUG] FMAP: area SMMSTORE found @ 5c0000 (262144 bytes)
  1147. [DEBUG] smm store: 4 # blocks with size 0x10000
  1148. [INFO ] SMMSTORE: Setting up SMI handler
  1149. [INFO ] Found TPM SLB9635 TT 1.2 by Infineon
  1150. [DEBUG] TPM: Startup
  1151. [DEBUG] TPM: command 0x99 returned 0x0
  1152. [DEBUG] TPM: Asserting physical presence
  1153. [DEBUG] TPM: command 0x4000000a returned 0x0
  1154. [DEBUG] TPM: command 0x65 returned 0x0
  1155. [DEBUG] TPM: flags disable=0, deactivated=0, nvlocked=1
  1156. [INFO ] TPM: setup succeeded
  1157. [DEBUG] BS: BS_DEV_INIT exit times (exec / console): 12 / 0 ms
  1158. [INFO ] Finalize devices...
  1159. [INFO ] Devices finalized
  1160. [INFO ] CBFS: Found 'fallback/dsdt.aml' @0x3a040 size 0x3eca in mcache @0x7afdd1b8
  1161. [WARN ] CBFS: 'fallback/slic' not found.
  1162. [INFO ] ACPI: Writing ACPI tables at 7af2a000.
  1163. [DEBUG] ACPI: * FACS
  1164. [DEBUG] ACPI: * DSDT
  1165. [DEBUG] ACPI: * FADT
  1166. [DEBUG] SCI is IRQ9
  1167. [DEBUG] ACPI: added table 1/32, length now 40
  1168. [DEBUG] ACPI: * SSDT
  1169. [INFO ] Turbo is available and visible
  1170. [DEBUG] PSS: 2167MHz power 7000 control 0x1f4e status 0x1f4e
  1171. [DEBUG] PSS: 2166MHz power 7000 control 0x1a45 status 0x1a45
  1172. [DEBUG] PSS: 1999MHz power 6312 control 0x1843 status 0x1843
  1173. [DEBUG] PSS: 1833MHz power 5649 control 0x163f status 0x163f
  1174. [DEBUG] PSS: 1666MHz power 5016 control 0x143c status 0x143c
  1175. [DEBUG] PSS: 1499MHz power 4412 control 0x1239 status 0x1239
  1176. [DEBUG] PSS: 1333MHz power 3827 control 0x1035 status 0x1035
  1177. [DEBUG] PSS: 1166MHz power 3268 control 0xe32 status 0xe32
  1178. [DEBUG] PSS: 999MHz power 2733 control 0xc2f status 0xc2f
  1179. [DEBUG] PSS: 833MHz power 2220 control 0xa2b status 0xa2b
  1180. [DEBUG] PSS: 666MHz power 1729 control 0x828 status 0x828
  1181. [DEBUG] PSS: 499MHz power 1263 control 0x624 status 0x624
  1182. [INFO ] Turbo is available and visible
  1183. [DEBUG] PSS: 2167MHz power 7000 control 0x1f4e status 0x1f4e
  1184. [DEBUG] PSS: 2166MHz power 7000 control 0x1a45 status 0x1a45
  1185. [DEBUG] PSS: 1999MHz power 6312 control 0x1843 status 0x1843
  1186. [DEBUG] PSS: 1833MHz power 5649 control 0x163f status 0x163f
  1187. [DEBUG] PSS: 1666MHz power 5016 control 0x143c status 0x143c
  1188. [DEBUG] PSS: 1499MHz power 4412 control 0x1239 status 0x1239
  1189. [DEBUG] PSS: 1333MHz power 3827 control 0x1035 status 0x1035
  1190. [DEBUG] PSS: 1166MHz power 3268 control 0xe32 status 0xe32
  1191. [DEBUG] PSS: 999MHz power 2733 control 0xc2f status 0xc2f
  1192. [DEBUG] PSS: 833MHz power 2220 control 0xa2b status 0xa2b
  1193. [DEBUG] PSS: 666MHz power 1729 control 0x828 status 0x828
  1194. [DEBUG] PSS: 499MHz power 1263 control 0x624 status 0x624
  1195. [DEBUG] PPI: Pending OS request: 0x0 (0x0)
  1196. [DEBUG] PPI: OS response: CMD 0xa41ce184 = 0x0
  1197. [INFO ] \_SB_.PCI0.TPM: LPC TPM PNP: 0c31.0
  1198. [ERROR] PS2K: Bad resp from EC. Vivaldi disabled!
  1199. [DEBUG] ACPI: added table 2/32, length now 44
  1200. [DEBUG] ACPI: * MCFG
  1201. [DEBUG] ACPI: added table 3/32, length now 48
  1202. [DEBUG] ACPI: * TCPA
  1203. [DEBUG] TCPA log created at 0x7af1a000
  1204. [DEBUG] ACPI: added table 4/32, length now 52
  1205. [DEBUG] ACPI: * MADT
  1206. [DEBUG] ACPI: added table 5/32, length now 56
  1207. [DEBUG] current = 7af2f2f0
  1208. [DEBUG] ACPI: * HPET
  1209. [DEBUG] ACPI: added table 6/32, length now 60
  1210. [INFO ] ACPI: done.
  1211. [DEBUG] ACPI tables: 21296 bytes.
  1212. [DEBUG] smbios_write_tables: 7af12000
  1213. [DEBUG] BIOS version set to CONFIG_LOCALVERSION: 'MrChromebox-4.18.1'
  1214. [INFO ] Create SMBIOS type 16
  1215. [INFO ] Create SMBIOS type 17
  1216. [INFO ] Create SMBIOS type 20
  1217. [INFO ] Root Device (Google Swanky)
  1218. [INFO ] PCI: 01:00.0 (unknown)
  1219. [DEBUG] SMBIOS tables: 978 bytes.
  1220. [DEBUG] Writing table forward entry at 0x00000500
  1221. [DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum a4e9
  1222. [DEBUG] Writing coreboot table at 0x7af4e000
  1223. [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
  1224. [DEBUG] 1. 0000000000001000-000000000009ffff: RAM
  1225. [DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED
  1226. [DEBUG] 3. 0000000000100000-000000001fffffff: RAM
  1227. [DEBUG] 4. 0000000020000000-00000000200fffff: RESERVED
  1228. [DEBUG] 5. 0000000020100000-000000007af11fff: RAM
  1229. [DEBUG] 6. 000000007af12000-000000007af79fff: CONFIGURATION TABLES
  1230. [DEBUG] 7. 000000007af7a000-000000007afcbfff: RAMSTAGE
  1231. [DEBUG] 8. 000000007afcc000-000000007affffff: CONFIGURATION TABLES
  1232. [DEBUG] 9. 000000007b000000-000000007fffffff: RESERVED
  1233. [DEBUG] 10. 00000000e0000000-00000000efffffff: RESERVED
  1234. [DEBUG] 11. 00000000feb00000-00000000febfffff: RESERVED
  1235. [DEBUG] 12. 00000000fed01000-00000000fed01fff: RESERVED
  1236. [DEBUG] 13. 00000000fed03000-00000000fed03fff: RESERVED
  1237. [DEBUG] 14. 00000000fed05000-00000000fed05fff: RESERVED
  1238. [DEBUG] 15. 00000000fed08000-00000000fed08fff: RESERVED
  1239. [DEBUG] 16. 00000000fed0c000-00000000fed0ffff: RESERVED
  1240. [DEBUG] 17. 00000000fed1c000-00000000fed1cfff: RESERVED
  1241. [DEBUG] 18. 00000000fed40000-00000000fed44fff: RESERVED
  1242. [DEBUG] 19. 00000000fef00000-00000000feffffff: RESERVED
  1243. [DEBUG] 20. 0000000100000000-000000017fffffff: RAM
  1244. [DEBUG] Wrote coreboot table at: 0x7af4e000, 0x52c bytes, checksum b7bf
  1245. [DEBUG] coreboot table: 1348 bytes.
  1246. [DEBUG] IMD ROOT 0. 0x7afff000 0x00001000
  1247. [DEBUG] IMD SMALL 1. 0x7affe000 0x00001000
  1248. [DEBUG] CONSOLE 2. 0x7afde000 0x00020000
  1249. [DEBUG] RO MCACHE 3. 0x7afdd000 0x00000374
  1250. [DEBUG] TIME STAMP 4. 0x7afdc000 0x00000910
  1251. [DEBUG] MEM INFO 5. 0x7afdb000 0x00000768
  1252. [DEBUG] MRC DATA 6. 0x7afd9000 0x0000166b
  1253. [DEBUG] AFTER CAR 7. 0x7afcc000 0x0000d000
  1254. [DEBUG] RAMSTAGE 8. 0x7af79000 0x00053000
  1255. [DEBUG] SMM BACKUP 9. 0x7af69000 0x00010000
  1256. [DEBUG] IGD OPREGION10. 0x7af66000 0x00002e13
  1257. [DEBUG] SMM COMBUFFER11. 0x7af56000 0x00010000
  1258. [DEBUG] COREBOOT 12. 0x7af4e000 0x00008000
  1259. [DEBUG] ACPI 13. 0x7af2a000 0x00024000
  1260. [DEBUG] TCPA TCGLOG14. 0x7af1a000 0x00010000
  1261. [DEBUG] SMBIOS 15. 0x7af12000 0x00008000
  1262. [DEBUG] IMD small region:
  1263. [DEBUG] IMD ROOT 0. 0x7affec00 0x00000400
  1264. [DEBUG] VPD 1. 0x7affeb40 0x000000bf
  1265. [DEBUG] FMAP 2. 0x7affea00 0x00000134
  1266. [DEBUG] POWER STATE 3. 0x7affe9e0 0x00000020
  1267. [DEBUG] ROMSTAGE 4. 0x7affe9c0 0x00000004
  1268. [DEBUG] ROMSTG STCK 5. 0x7affe920 0x00000088
  1269. [DEBUG] ACPI GNVS 6. 0x7affe820 0x000000e8
  1270. [DEBUG] TPM PPI 7. 0x7affe6c0 0x0000015a
  1271. [DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 5 / 0 ms
  1272. [INFO ] CBFS: Found 'fallback/payload' @0x56c40 size 0xc7760 in mcache @0x7afdd2c4
  1273. [DEBUG] Checking segment from ROM address 0xffe5ae6c
  1274. [DEBUG] Checking segment from ROM address 0xffe5ae88
  1275. [DEBUG] Loading segment from ROM address 0xffe5ae6c
  1276. [DEBUG] code (compression=1)
  1277. [DEBUG] New segment dstaddr 0x00800000 memsize 0x590000 srcaddr 0xffe5aea4 filesize 0xc7728
  1278. [DEBUG] Loading Segment: addr: 0x00800000 memsz: 0x0000000000590000 filesz: 0x00000000000c7728
  1279. [DEBUG] using LZMA
  1280. [DEBUG] Loading segment from ROM address 0xffe5ae88
  1281. [DEBUG] Entry Point 0x00801626
  1282. [DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 280 / 0 ms
  1283. [DEBUG] Applying perf/power settings.
  1284. [DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 1 / 0 ms
  1285. [DEBUG] Jumping to boot code at 0x00801626(0x7af4e000)
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