ex1_thirdlab

/*
module FA (a,b,cin,cout,sum);
    input a,b, cin;
    output reg cout, sum;

    always @ (*)
        begin
            {cout, sum} = a + b + cin;
        end

endmodule
*/

module MUX2to1NB (s, i, f);
    parameter n = 4;
    input               s;
    input [n-1:0]       i;
    output reg [n-1:0]  f;

    always @ (*)
        begin
            f   = i[s +: n];
        end
endmodule

module CLA4bit  (a, b, cin, cout, s);
    parameter n = 4;

    input   [n-1:0] a, b;
    input           cin;
    output  [n-1:0] s;
    output          cout;

    wire    [n:0]   c;
    wire    [n-1:0] g, p, sum;

    assign c[0]     = cin;

    genvar  j;
    generate
        for (j=0; j<n; j=j+1)
            begin
                assign g[j]     = a[j] & b[j];
                assign p[j]     = a[j] ^ b[j];
                assign sum[j]   = p[j] ^ c[j];
                assign c[j+1]   = g[j] | p[j] & c[j];
            end
    endgenerate

    assign cout = c[n];
    assign s = sum;

endmodule

module Adder8bit    (a, b, cin, cout, s);
    input   [7:0]   a, b;
    input           cin;

    output          cout;
    output  [7:0]   s;

    wire            w_c0, w_c1, w_c2, w_cin1, w_cin2;
    wire    [3:0]   w_s1, w_s2;

    assign w_cin1 =     0;
    assign w_cin2 =     1;

    CLA4bit#(.n(4)) CLA0 (.a(a[3:0]), .b(b[3:0]), .cin(cin), .cout(w_c0), .s(s[3:0]));
    CLA4bit#(.n(4)) CLA1 (.a(a[7:4]), .b(b[7:4]), .cin(w_cin1), .cout(w_c1), .s(w_s1));
    CLA4bit#(.n(4)) CLA2 (.a(a[7:4]), .b(b[7:4]), .cin(w_cin2), .cout(w_c2), .s(w_s2));

    MUX2to1NB#(.n(4)) MUX1 (.s(w_c0), .i({w_s2, w_s1}), .f(s[7:4]));
    MUX2to1NB#(.n(1)) MUX2 (.s(w_c0), .i({w_c2, w_c1}), .f(cout));

endmodule