always @(posedge clk or posedge reset) begin
   if (rst) state <= clear;
   begin
      case(state)
         clear: state <= zero;

         zero: state <= startstop ? start : zero;

         start: state <= startstop ? start : counting;

         counting: state <= startstop ? stop : counting;

         stop: state <= startstop ? stop : stopped;

         stopped: state <= startstop ? start : stopped;

         default : state <= clear;

      endcase
   end
end

end

assign rst = (state == clear) ? 1'b1 : 1'b0;
assign clken = (state == counting) ? 1'b1 : 1'b0;