Litex on Upduino_V3 --cpu-variant=minimal --build --cpu-type=picorv32 --no-compile-gateware --flash

PS C:\JTAG\github\litex-boards> python -m litex_boards.targets.upduino_v3 --cpu-variant=minimal --build --cpu-type=picorv32 --no-compile-gateware --flash
INFO:SoC:        __   _ __      _  __
INFO:SoC:       / /  (_) /____ | |/_/
INFO:SoC:      / /__/ / __/ -_)>  <
INFO:SoC:     /____/_/\__/\__/_/|_|
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2022-06-27 03:24:35)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : ice40-up5k-sg48.
INFO:SoC:System clock: 12.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU picorv32 added.
INFO:SoC:CPU picorv32 adding IO Region 0 at 0x80000000 (Size: 0x80000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoC:CPU picorv32 setting reset address to 0x00000000.
INFO:SoC:CPU picorv32 adding Bus Master(s).
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoC:CPU picorv32 adding Interrupt(s).
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:SoCBusHandler:Allocating Cached Region of size 0x00020000...
INFO:SoCRegion:Region size rounded internally from 0xffffffff to 0x100000000.
INFO:SoCBusHandler:sram Region allocated at Origin: 0x00000000, Size: 0x00020000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoCBusHandler:Allocating Cached Region of size 0x00400000...
INFO:SoCRegion:Region size rounded internally from 0xffffffff to 0x100000000.
INFO:SoCBusHandler:spiflash Region allocated at Origin: 0x00400000, Size: 0x00400000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:spiflash added as Bus Slave.
INFO:SoCBusHandler:rom Region added at Origin: 0x00440000, Size: 0x00008000, Mode: RW, Cached: True Linker: True.
INFO:SoC:CSR Bridge csr added.
INFO:SoCBusHandler:csr Region added at Origin: 0x82000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:csr added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (1 <-> 3).
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 1.
INFO:SoCCSRHandler:leds CSR allocated at Location 2.
INFO:SoCCSRHandler:spiflash_core CSR allocated at Location 3.
INFO:SoCCSRHandler:spiflash_phy CSR allocated at Location 4.
INFO:SoCCSRHandler:timer0 CSR allocated at Location 5.
INFO:SoCCSRHandler:uart CSR allocated at Location 6.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0                 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False
Bus Regions: (4)
sram                : Origin: 0x00000000, Size: 0x00020000, Mode: RW, Cached: True Linker: False
spiflash            : Origin: 0x00400000, Size: 0x00400000, Mode: RW, Cached: True Linker: False
rom                 : Origin: 0x00440000, Size: 0x00008000, Mode: RW, Cached: True Linker: True
csr                 : Origin: 0x82000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
Bus Masters: (1)
- cpu_bus0
Bus Slaves: (3)
- sram
- spiflash
- csr
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (7)
- ctrl           : 0
- identifier_mem : 1
- leds           : 2
- spiflash_core  : 3
- spiflash_phy   : 4
- timer0         : 5
- uart           : 6
INFO:SoC:IRQ Handler (up to 32 Locations).
IRQ Locations: (2)
- uart   : 0
- timer0 : 1
INFO:SoC:--------------------------------------------------------------------------------
make: Entering directory 'C:/JTAG/github/litex-boards/build/upduino_v3/software/libc'
if [ -d "c:\\jtag\\github\\litex\\litex\\soc\\software\\libc/riscv" ]; then \
        cp c:\\jtag\\github\\litex\\litex\\soc\\software\\libc/riscv/* C:\\Users\\river\\AppData\\Roaming\\Python\\Python310\\site-packages\\pythondata_software_picolibc\\data/newlib/libc/machine/riscv/ ;\
fi
-d was unexpected at this time.
make: *** [c:\jtag\github\litex\litex\soc\software\libc\Makefile:42: __libc.a] Error 255
make: Leaving directory 'C:/JTAG/github/litex-boards/build/upduino_v3/software/libc'
Traceback (most recent call last):
  File "C:\Python310\lib\runpy.py", line 196, in _run_module_as_main
    return _run_code(code, main_globals, None,
  File "C:\Python310\lib\runpy.py", line 86, in _run_code
    exec(code, run_globals)
  File "C:\JTAG\github\litex-boards\litex_boards\targets\upduino_v3.py", line 127, in <module>
    main()
  File "C:\JTAG\github\litex-boards\litex_boards\targets\upduino_v3.py", line 121, in main
    builder.build()
  File "c:\jtag\github\litex\litex\soc\integration\builder.py", line 339, in build
    self._generate_rom_software(compile_bios=use_bios)
  File "c:\jtag\github\litex\litex\soc\integration\builder.py", line 276, in _generate_rom_software
    subprocess.check_call(["make", "-C", dst_dir, "-f", makefile])
  File "C:\Python310\lib\subprocess.py", line 369, in check_call
    raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['make', '-C', 'C:\\JTAG\\github\\litex-boards\\build\\upduino_v3\\software\\libc', '-f', 'c:\\jtag\\github\\litex\\litex\\soc\\software\\libc\\Makefile']' returned non-zero exit status 2.
PS C:\JTAG\github\litex-boards>