example code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity equation is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           C : in STD_LOGIC;
           F : out STD_LOGIC;
           G : out STD_LOGIC;
           H : out STD_LOGIC);
end equation;

architecture Behavioral of equation is

begin

 F <= ((A AND B) XNOR (NOT(A) AND C))
  OR
  (((A AND B) OR (NOT(A) AND C)) AND (A OR (B AND NOT(C))));

  G <= A OR NOT(C);

  H <= (NOT(A) AND NOT(B) AND NOT(C))
   OR (NOT(A) AND B AND NOT(C))
    OR(A AND NOT(B) AND NOT(C))
     OR(A AND B AND NOT(C))
      OR (A AND B AND C)
       OR (A AND NOT(B) AND C);

end Behavioral;


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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity equation_tb is
--  Port ( );
end equation_tb;

architecture Behavioral of equation_tb is
--import model, change entity to componenet
component equation is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           C : in STD_LOGIC;
           F : out STD_LOGIC;
           G : out STD_LOGIC;
           H : out STD_LOGIC);
end component;
-- define connections to ports
signal a, b, c, f, g, h : std_logic;


begin
    -- have an instance of the model being tested
    uut: equation port map( a => a, b => b, c=> c, f=> f, g => g, h=> h);

    process
    -- variables to help with automation
        variable counter : integer := 0;
        variable counterslv: std_logic_vector(2 downto 0);
    begin
    -- convert integer to std_logic_vector
        counterslv := std_logic_vector(to_unsigned(counter, 3));
        --increment counter
        counter := counter + 1;
       --extract each individual input
        a <= counterslv(2);
        b <= counterslv(1);
        c <= counterslv(0);

        wait for 20ns;
    end process;

end Behavioral;