# clktst.py - checkout clock domains
# 2020-08-06 E. Brombaugh

from nmigen import *
from nmigen.sim.pysim import *

# simple counter for submodules
class counter(Elaboratable):
    def __init__(self):
        # ports
        self.output = Signal(4)

    def elaborate(self, platform):
        m = Module()

        m.d.sync += self.output.eq(self.output + 1)

        return m

# hook up some counters in different domains
class clktst(Elaboratable):
    def __init__(self):
        # ports
        self.out1 = Signal(4)
        self.out2 = Signal(4)

    def elaborate(self, platform):
        m = Module()

        # generate lower rate clk and retimed reset
        clk_div2 = Signal()
        m.d.sync += clk_div2.eq(~clk_div2)
        nreset_div2 = Signal(2)
        m.d.sync += nreset_div2.eq(Cat(1,nreset_div2[0]))

        # instantiate first counter at default rate
        m.submodules.cnt1 = counter()

        # instantiate second counter with rename
        m.submodules.cnt2 = DomainRenamer("sync_two")(counter())

        # create a clock domain in the renamed domain and connect
        # to divided clock and retimed reset
        sync2 = ClockDomain("sync_two")
        m.domains += sync2
        m.d.comb += [
            sync2.clk.eq(clk_div2),
            sync2.rst.eq(~nreset_div2[1])
        ]

        # route both counters out
        m.d.comb += [
            self.out1.eq(m.submodules.cnt1.output),
            self.out2.eq(m.submodules.cnt2.output)
        ]

        return m

# simulate
if __name__ == "__main__":
    dut = clktst()
    sim = Simulator(dut)
    with sim.write_vcd("clktst.vcd"):
        def proc():
            for i in range( 256 ):
                yield Tick()
        sim.add_clock( 1/40e6 )
        sim.add_sync_process( proc )
        sim.run()