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  1. # clktst.py - checkout clock domains
  2. # 2020-08-06 E. Brombaugh
  3.  
  4. from nmigen import *
  5. from nmigen.sim.pysim import *
  6.  
  7. # simple counter for submodules
  8. class counter(Elaboratable):
  9.     def __init__(self):        
  10.         # ports
  11.         self.output = Signal(4)
  12.        
  13.     def elaborate(self, platform):
  14.         m = Module()
  15.        
  16.         m.d.sync += self.output.eq(self.output + 1)
  17.        
  18.         return m        
  19.  
  20. # hook up some counters in different domains
  21. class clktst(Elaboratable):
  22.     def __init__(self):        
  23.         # ports
  24.         self.out1 = Signal(4)
  25.         self.out2 = Signal(4)
  26.        
  27.     def elaborate(self, platform):
  28.         m = Module()
  29.        
  30.         # generate lower rate clk and retimed reset
  31.         clk_div2 = Signal()
  32.         m.d.sync += clk_div2.eq(~clk_div2)
  33.         nreset_div2 = Signal(2)
  34.         m.d.sync += nreset_div2.eq(Cat(1,nreset_div2[0]))
  35.        
  36.         # instantiate first counter at default rate
  37.         m.submodules.cnt1 = counter()
  38.        
  39.         # instantiate second counter with rename
  40.         m.submodules.cnt2 = DomainRenamer("sync_two")(counter())
  41.        
  42.         # create a clock domain in the renamed domain and connect
  43.         # to divided clock and retimed reset
  44.         sync2 = ClockDomain("sync_two")
  45.         m.domains += sync2
  46.         m.d.comb += [
  47.             sync2.clk.eq(clk_div2),
  48.             sync2.rst.eq(~nreset_div2[1])
  49.         ]
  50.        
  51.         # route both counters out
  52.         m.d.comb += [
  53.             self.out1.eq(m.submodules.cnt1.output),
  54.             self.out2.eq(m.submodules.cnt2.output)
  55.         ]
  56.        
  57.         return m
  58.  
  59. # simulate
  60. if __name__ == "__main__":
  61.     dut = clktst()
  62.     sim = Simulator(dut)
  63.     with sim.write_vcd("clktst.vcd"):
  64.         def proc():
  65.             for i in range( 256 ):                    
  66.                 yield Tick()
  67.         sim.add_clock( 1/40e6 )
  68.         sim.add_sync_process( proc )
  69.         sim.run()
  70.  
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