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Jun 22nd, 2014
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  1. Подсветка:
  2. #define BACKLIGHT_BASE_STEP 80
  3. #define BACKLIGHT_MIN_VALUE 10
  4. void T3_PWMBL_CTR(int vla, int state)
  5. {
  6. //背光强度控制
  7. unsigned int TC103_PWMBL_TBL[16]={0x08,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xa0,0xb0,0xc0,0xd0,0xe8,0xff};
  8. unsigned char tData[2];
  9. int blvalue=vla;
  10. bl_level=vla;
  11. if(enable3d==0) {
  12. blvalue = vla-BACKLIGHT_BASE_STEP; # C040B934
  13. if(blvalue < BACKLIGHT_MIN_VALUE) # C040B93C
  14. blvalue=BACKLIGHT_MIN_VALUE; # C040B940
  15. } else {
  16. if(blvalue<BACKLIGHT_BASE_STEP) # C040B958
  17. blvalue=BACKLIGHT_BASE_STEP; # C040B960
  18. }
  19.  
  20. if (state) {
  21. if(twx_tc103_bl_i2c_client) {
  22. tData[0]=0x42;
  23. tData[1] = 0x00;
  24. twx_i2c_write(twx_tc103_bl_i2c_client,tData,2);
  25. tData[0]=0x43;
  26. tData[1] = blvalue;//TC103_DBL_TBL[vla];
  27. twx_i2c_write(twx_tc103_bl_i2c_client,tData,2);
  28. printk( "tc103 set backlight leve %d\n",blvalue);
  29. }
  30. }
  31. }
  32.  
  33.  
  34. RAM:C040B92C ; =============== S U B R O U T I N E =======================================
  35. RAM:C040B92C
  36. RAM:C040B92C
  37. RAM:C040B92C T3_PWMBL_CTR ; CODE XREF: RAM:C040B9FCp
  38. RAM:C040B92C ; T2_Panel3DLense+94p ...
  39. RAM:C040B92C
  40. RAM:C040B92C var_A = -0xA
  41. RAM:C040B92C var_9 = -9
  42. RAM:C040B92C
  43. RAM:C040B92C LDR R3, =dword_C0978A58
  44. RAM:C040B930 STMFD SP!, {R4,LR}
  45. RAM:C040B934 SUB R4, R0, #0x50
  46. RAM:C040B938 LDR R2, [R3]
  47. RAM:C040B93C CMP R4, #0xA
  48. RAM:C040B940 MOVLT R4, #0xA
  49. RAM:C040B944 LDR R12, =unk_C08061A8
  50. RAM:C040B948 SUB SP, SP, #8
  51. RAM:C040B94C CMP R2, #0
  52. RAM:C040B950 STR R0, [R12,#(dword_C0806364 - 0xC08061A8)]
  53. RAM:C040B954 BEQ loc_C040B964
  54. RAM:C040B958 CMP R0, #0x50
  55. RAM:C040B95C MOVGE R4, R0
  56. RAM:C040B960 MOVLT R4, #0x50
  57. RAM:C040B964
  58. RAM:C040B964 loc_C040B964 ; CODE XREF: T3_PWMBL_CTR+28j
  59. RAM:C040B964 CMP R1, #0
  60. RAM:C040B968 BEQ loc_C040B978
  61. RAM:C040B96C LDR R0, [R3,#0x10]
  62. RAM:C040B970 CMP R0, #0
  63. RAM:C040B974 BNE loc_C040B980
  64. RAM:C040B978
  65. RAM:C040B978 loc_C040B978 ; CODE XREF: T3_PWMBL_CTR+3Cj
  66. RAM:C040B978 ; T3_PWMBL_CTR+94j
  67. RAM:C040B978 ADD SP, SP, #8
  68. RAM:C040B97C LDMFD SP!, {R4,PC}
  69. RAM:C040B980 ; ---------------------------------------------------------------------------
  70. RAM:C040B980
  71. RAM:C040B980 loc_C040B980 ; CODE XREF: T3_PWMBL_CTR+48j
  72. RAM:C040B980 ADD R1, SP, #0x10+var_A
  73. RAM:C040B984 MOV R3, #0x42
  74. RAM:C040B988 STRB R3, [SP,#0x10+var_A]
  75. RAM:C040B98C MOV R3, #0
  76. RAM:C040B990 STRB R3, [SP,#0x10+var_9]
  77. RAM:C040B994 BL twx_i2c_write.constprop.4
  78. RAM:C040B998 LDR R3, =dword_C0978A58
  79. RAM:C040B99C ADD R1, SP, #0x10+var_A
  80. RAM:C040B9A0 STRB R4, [SP,#0x10+var_9]
  81. RAM:C040B9A4 LDR R0, [R3,#(dword_C0978A68 - 0xC0978A58)]
  82. RAM:C040B9A8 MOV R3, #0x43
  83. RAM:C040B9AC STRB R3, [SP,#0x10+var_A]
  84. RAM:C040B9B0 BL twx_i2c_write.constprop.4
  85. RAM:C040B9B4 MOV R1, R4
  86. RAM:C040B9B8 LDR R0, =aTc103SetBackli ; "tc103 set backlight leve %d\n"
  87. RAM:C040B9BC BL printk
  88. RAM:C040B9C0 B loc_C040B978
  89. RAM:C040B9C0 ; End of function T3_PWMBL_CTR
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