# A partial DEMUX18 implementation.
# Logic involving S<2:0> is done outside
# in order to minimize redundant gates.
DEF DEMUX18_ABST
  # The regular DEMUX18 ports
  PORT IN A
  PORT IN S2
  PORT IN S1
  PORT IN S0
  PORT OUT Z0
  PORT OUT Z1
  PORT OUT Z2
  PORT OUT Z3
  PORT OUT Z4
  PORT OUT Z5
  PORT OUT Z6
  PORT OUT Z7
  # ZP7 through ZP0 select the output.
  # In case you're wondering, P just means "prime" in my head.
  PORT IN ZP7
  PORT IN ZP6
  PORT IN ZP5
  PORT IN ZP4
  PORT IN ZP3
  PORT IN ZP2
  PORT IN ZP1
  PORT IN ZP0
  NET NOT_Z7
  NET NOT_Z6
  NET NOT_Z5
  NET NOT_Z4
  NET NOT_Z3
  NET NOT_Z2
  NET NOT_Z1
  NET NOT_Z0

  # And each selector with the input, and that's it for this.
  INST NAND7 NAND ZP7 A NOT_Z7
  INST NOT7 NOT NOT_Z7 Z7

  INST NAND8 NAND ZP6 A NOT_Z6
  INST NOT8 NOT NOT_Z6 Z6

  INST NAND9 NAND ZP5 A NOT_Z5
  INST NOT9 NOT NOT_Z5 Z5

  INST NAND10 NAND ZP4 A NOT_Z4
  INST NOT10 NOT NOT_Z4 Z4

  INST NAND11 NAND ZP3 A NOT_Z3
  INST NOT11 NOT NOT_Z3 Z3

  INST NAND12 NAND ZP2 A NOT_Z2
  INST NOT12 NOT NOT_Z2 Z2

  INST NAND13 NAND ZP1 A NOT_Z1
  INST NOT13 NOT NOT_Z1 Z1

  INST NAND14 NAND ZP0 A NOT_Z0
  INST NOT14 NOT NOT_Z0 Z0
ENDDEF

# The gravy.
DEF DEMUX18x8
  PORT IN A<7:0>
  PORT IN S<2:0>
  PORT OUT Z0<7:0>
  PORT OUT Z1<7:0>
  PORT OUT Z2<7:0>
  PORT OUT Z3<7:0>
  PORT OUT Z4<7:0>
  PORT OUT Z5<7:0>
  PORT OUT Z6<7:0>
  PORT OUT Z7<7:0>
  # A0-A3 have nothing to do with the input, A.
  # Those are just the labels I wrote on my whiteboard for the equations.
  # A0-A3 pertains to S<2:1>.
  # The following logic selects which output Z to use.
  # Equations are reused heavily in order to avoid redundant gates.
  NET A0
  NET A1
  NET A2
  NET A3
  NET NOT_A0
  NET NOT_A1
  NET NOT_A2
  NET NOT_A3
  NET NOT_S1
  NET ZP0_STAGE1
  NET ZP0
  NET ZP1_STAGE1
  NET ZP1
  NET ZP2_STAGE1
  NET ZP2
  NET ZP3_STAGE1
  NET ZP3
  NET ZP4_STAGE1
  NET ZP4
  NET ZP5_STAGE1
  NET ZP5
  NET ZP6_STAGE1
  NET ZP6
  NET ZP7_STAGE1
  NET ZP7

  # A0' = S2 nand S1
  INST NAND1 NAND S<2> S<1> NOT_A0
  # A0 = not A0'
  INST NOT1 NOT NOT_A0 A0
  # A1' = S2 nand (not S1) = A0' nand S2
  INST NAND2 NAND NOT_A0 S<2> NOT_A1
  # A1 = not A1'
  INST NOT2 NOT NOT_A1 A1
  # A2' = (not S2) nand S1 = A0' nand S1
  INST NAND3 NAND NOT_A0 S<1> NOT_A2
  # A2 = not A2'
  INST NOT3 NOT NOT_A2 A2
  # A3' = (not S2) nand (not S1) = (not S1) nand A1'
  INST NOT4 NOT S<1> NOT_S1
  INST NAND4 NAND NOT_S1 NOT_A1 NOT_A3
  # A3 = not A3'
  INST NOT4_5 NOT NOT_A3 A3

  # Now we handle S0.
  # ZP7' = (S2 and S1) nand S0 = A0 nand S0
  INST NAND5 NAND A0 S<0> ZP7_STAGE1
  # ZP7 = not ZP7'
  INST NOT5 NOT ZP7_STAGE1 ZP7
  # ZP6' = (S2 and S1) nand (not S0) = ZP7' nand A0
  INST NAND6 NAND ZP7_STAGE1 A0 ZP6_STAGE1
  # ZP6 = not ZP6'
  INST NOT6 NOT ZP6_STAGE1 ZP6
  # ZP5' = (S2 and not S1) nand S0 = A1 nand S0
  INST NAND7 NAND A1 S<0> ZP5_STAGE1
  # ZP5 = not ZP5'
  INST NOT7 NOT ZP5_STAGE1 ZP5
  # ZP4' = (S2 and not S1) nand (not S0) = A1 nand ZP5'
  INST NAND8 NAND ZP5_STAGE1 A1 ZP4_STAGE1
  # ZP4 = not ZP4'
  INST NOT8 NOT ZP4_STAGE1 ZP4
  # ZP3' = (not S2 and S1) nand S0 = A2 nand S0
  INST NAND9 NAND A2 S<0> ZP3_STAGE1
  # ZP3 = not ZP3'
  INST NOT9 NOT ZP3_STAGE1 ZP3
  # ZP2' = (not S2 and S1) nand (not S0) = A2 nand ZP3'
  INST NAND10 NAND ZP3_STAGE1 A2 ZP2_STAGE1
  # ZP2 = not ZP2'
  INST NOT10 NOT ZP2_STAGE1 ZP2
  # ZP1' = (not S2 and not S1) nand S1 = A3 nand S0
  INST NAND11 NAND A3 S<0> ZP1_STAGE1
  # ZP1 = not ZP1'
  INST NOT11 NOT ZP1_STAGE1 ZP1
  # ZP0' = (not S2 and not S1) nand (not S0) = A3 nand ZP1'
  INST NAND12 NAND ZP1_STAGE1 A3 ZP0_STAGE1
  # ZP0 = not ZP0'
  INST NOT12 NOT ZP0_STAGE1 ZP0

  # I'm hungry.
  INST DM1 DEMUX18_ABST A<7> S<2:0> Z0<7> Z1<7> Z2<7> Z3<7> Z4<7> Z5<7> Z6<7> Z7<7> ZP7 ZP6 ZP5 ZP4 ZP3 ZP2 ZP1 ZP0
  INST DM2 DEMUX18_ABST A<6> S<2:0> Z0<6> Z1<6> Z2<6> Z3<6> Z4<6> Z5<6> Z6<6> Z7<6> ZP7 ZP6 ZP5 ZP4 ZP3 ZP2 ZP1 ZP0
  INST DM3 DEMUX18_ABST A<5> S<2:0> Z0<5> Z1<5> Z2<5> Z3<5> Z4<5> Z5<5> Z6<5> Z7<5> ZP7 ZP6 ZP5 ZP4 ZP3 ZP2 ZP1 ZP0
  INST DM4 DEMUX18_ABST A<4> S<2:0> Z0<4> Z1<4> Z2<4> Z3<4> Z4<4> Z5<4> Z6<4> Z7<4> ZP7 ZP6 ZP5 ZP4 ZP3 ZP2 ZP1 ZP0
  INST DM5 DEMUX18_ABST A<3> S<2:0> Z0<3> Z1<3> Z2<3> Z3<3> Z4<3> Z5<3> Z6<3> Z7<3> ZP7 ZP6 ZP5 ZP4 ZP3 ZP2 ZP1 ZP0
  INST DM6 DEMUX18_ABST A<2> S<2:0> Z0<2> Z1<2> Z2<2> Z3<2> Z4<2> Z5<2> Z6<2> Z7<2> ZP7 ZP6 ZP5 ZP4 ZP3 ZP2 ZP1 ZP0
  INST DM7 DEMUX18_ABST A<1> S<2:0> Z0<1> Z1<1> Z2<1> Z3<1> Z4<1> Z5<1> Z6<1> Z7<1> ZP7 ZP6 ZP5 ZP4 ZP3 ZP2 ZP1 ZP0
  INST DM8 DEMUX18_ABST A<0> S<2:0> Z0<0> Z1<0> Z2<0> Z3<0> Z4<0> Z5<0> Z6<0> Z7<0> ZP7 ZP6 ZP5 ZP4 ZP3 ZP2 ZP1 ZP0
ENDDEF