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MrRockchip

am1ia fail culprit --- STATIC_OPTION_TABLE if used

Jan 8th, 2024 (edited)
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  1. #git revert --no-edit d81d80c554a2549720ce2114a1a84720d0605192 # 4858 # GRF # soc/intel/cse: remove cbfs_unverified_area_map() API in cse_lite
  2. ++++++++++ INSERT THIS GIT REVERT HERE
  3. git revert --no-edit 6dff1fd7d5e419b2f947f516551dcab3f4ebe30a # 4782 # GRF # cpu/intel/common: Define build time physical address reserved bits
  4.  
  5. https://pastebin.com/GWKw8PSm
  6.  
  7. commit 29030d0f3dad2ec6b86000dfe2c8e951ae80bf94
  8. Author: Bill Xie <persmule@hardenedlinux.org>
  9. Date: Sat Oct 7 01:32:51 2023 +0800
  10.  
  11. drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume
  12.  
  13. After commit e12b313844da ("drivers/pc80/rtc/option.c: Allow CMOS
  14. defaults to extend to bank 1"), Thinkpad X200 with
  15. CONFIG(STATIC_OPTION_TABLE) can no longer resume from s3 (detected via
  16. bisect).
  17.  
  18. Further inspection shows that DRAM training result of GM45 is stored
  19. in CMOS above 128 bytes in raminit_read_write_training.c, for s3 resume
  20. to restore, but it will be erased by sanitize_cmos(), which now clears
  21. both bank 0 and bank 1, leaving only "untrained" result restored, so s3
  22. resume will fail.
  23.  
  24. However, resetting CMOS seems unnecessary during s3 resume. Now,
  25. cmos_need_reset will be negated when acpi_is_wakeup_s3() returns true.
  26.  
  27. Tested: Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from
  28. s3 again with these changes.
  29.  
  30. Change-Id: I533e83f3b95f327b0e24f4d750f8812325b7770b
  31. Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
  32. Reviewed-on: https://review.coreboot.org/c/coreboot/+/78288
  33. Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
  34. Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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