-- Engineer: Declan Moriarty
--
-- Create Date:    09:07:51 03/25/2012
-- Design Name:
-- Module Name:    FM Generator
-- Project Name:
-- Target Devices: ispMach40xx
-- Revision: 0.01

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_signed.ALL;

entity fmgen is
	Port (data : in std_logic;
		clock : in STD_LOGIC ;
		cnt : in std_logic_vector (3 downto 0);
		hb :  out std_logic_vector (3 downto 0):= "1100");
end fmgen;
--21
Architecture Behavioral of fmgen is

signal 	dlyd: std_logic_vector (3 downto 0) := "0000";
	-- dlyd times the FM pulse (@ 1/2 xtal speed)
signal 	hbd: std_logic_vector (3 downto 0) := "0000";
	--hbd times the output pulse @ xtal speed for 50% of dlyd
signal halfclock : std_logic := '0';
	-- halfclock is used in generating FM (1/2 xtal speed).
signal dlyq: std_logic :='0';
	-- output to H BRIDGE.
signal start: std_logic :='0';
	-- first time pulse for FM.
signal lst: std_logic :='0';
	-- Last state of o/p to hbridge
signal half: std_logic := '0';
begin

--39  Generate half speed clock for fm generation to save hardware.
halfclk: process (clock)
begin
	if (clock'event and clock='1') then
		half <= halfclock;
		halfclock <= (not halfclock);
	end if;
-- 45
end process halfclk;
	-- Next, Generate timing for FM pulses
	-- Using halfclock as speed
	-- samples data for a high data @ dlyd=1 & pulses accordingly.
	-- Startup routine provides initial pulse & loads timers
	-- process handles FM timing. Long or short pulses
delay: process (halfclock, clock,dlyd, start, data, cnt,half, hbd,dlyq)
begin


-- 56 No rising edge check possible on halfclock, so needs half to avoid double pulsing.
	if (half = '0' and (halfclock = '1')) then
		if (start = '0') then
		hbd  <= cnt;
		dlyd <= cnt;
		start <= '1';
		end if;
-- 63 That lot provides a startup pulse.
	elsif ((dlyd = "0001" and data = '1') or ( dlyd = "0000")) then
			hbd <= (cnt - 1);
			dlyd <= cnt;
			dlyq <= '1';
	else	dlyd <= (dlyd -1);
	end if;
-- 70 The Above provides FM timing
	--  Counting hbd(=pulse length)twice as fast as fm for 50% duty cycle.
	if (rising_edge (clock)) then
		if (hbd > 0) then
			hbd <= (hbd -1);
			dlyq <= '1';
		else	dlyq <= '0'; 	--This is the 5th occurrence of dlyq
		end if;
		if dlyq = lst then
			if (dlyq = '1') then hb <= "0101";
			else   hb <= "1010";
			end if;
-- 81 If dlyq is different to lst, it has changed state
		else hb <= "1100";
		--Turns off all hbridge transistors for one cycle
		end if;
		lst <= dlyq;
	end if;
-- 87
end process;
	--hb(3) => pnp left top.
	--hb(2) => pnp right top.
	--hb(1) => npn left bottom.
	--hb(0) => npn right bottom.
end Behavioral;