/*
module porraninhuma(led0,led1,led2,led3,led4,led5,led6,led7,memlinha,memcoluna);
    //input [4:1]memlinha;
    //output reg[4:1]memcoluna;
    input [4:1]memcoluna;
    output reg[4:1]memlinha;
    output reg led0;
    output reg led1;
    output reg led2;
    output reg led3;
    output reg led4;
    output reg led5;
    output reg led6;
    output reg led7;



    initial begin
        led0<=0;
        led1<=0;
        led2<=0;
        led3<=0;
        led4<=0;
        led5<=0;
        led6<=0;
        led7<=0;
        memlinha[1]<=0;
        memlinha[2]<=0;
        memlinha[3]<=0;
        memlinha[4]<=0;
    end



    always@(*)begin
        led0<=memlinha[1];
        led1<=memlinha[2];
        led2<=memlinha[3];
        led3<=memlinha[4];
        led4<=memcoluna[1];
        led5<=memcoluna[2];
        led6<=memcoluna[3];
        led7<=memcoluna[4];
    end



endmodule
*/

module porraninhuma(clk,led1,led2,led3,led4,led5,led6,led7,led8,led0,led9,ledzeppelin,memlinha,memcoluna,ledefo,ledefo1,ledefo2,ledefo3,ledefo4,ledefo5);
    input [1:4]memcoluna;
    output reg[1:4]memlinha;
    wire [1:4]colunadeb;
    output reg led8;
    output reg led1;
    output reg led2;
    output reg led3;
    output reg led4;
    output reg led5;
    output reg led6;
    output reg led9;
    output reg led0;
    output reg ledzeppelin;
    output reg led7;
    output reg ledefo,ledefo1,ledefo2,ledefo3,ledefo4,ledefo5;
    reg c;
    input clk;
    integer counter;
    reg clk2;

    debounce D0(clk, memcoluna[1], colunadeb[1]);
    debounce D1(clk, memcoluna[2], colunadeb[2]);
    debounce D2(clk, memcoluna[3], colunadeb[3]);
    debounce D3(clk, memcoluna[4], colunadeb[4]);

    //module pra clock auxiliar

    initial begin
        led1<=0;
        led2<=0;
        led3<=0;
        led4<=0;
        led5<=0;
        led6<=0;
        led7<=0;
        led8<=0;
        led9<=0;
        led0<=0;
        ledefo<=0;
        ledefo1<=0;
        ledefo2<=0;
        ledefo3<=0;
        ledefo4<=0;
        ledefo5<=0;
        ledzeppelin<=0;
        c<=0;
        memlinha<=4'b1110;
    end

    always@(posedge clk)begin
        if(c==1000000)begin
            clk2 <= ~clk2;
            c<=0;
        end
        else
            c<=c+1;
    end

    always@(posedge clk2)begin

        case(memlinha)
            4'b0111:begin
                memlinha<=4'b1011;
            end
            4'b1011:begin
                memlinha<=4'b1101;
            end
            4'b1101:begin
                memlinha<=4'b1110;
            end
            4'b1110:begin
                memlinha<=4'b0111;
            end
            default:begin
                ledefo<=1;
            end
        endcase
    end

    always@(posedge clk2)begin

        case(memlinha)
            4'b0111:begin
                case(colunadeb)
                    4'b0111:begin
                        led1<=1;
                    end
                    4'b1011:begin
                        led2<=1;
                    end
                    4'b1101:begin
                        led3<=1;
                    end
                    default:begin
                        memlinha <= 4'b1011;
                    end
                endcase
            end
            4'b1011:begin
                case(colunadeb)
                    4'b0111:begin
                        led4<=1;
                    end
                    4'b1011:begin
                        led5<=1;
                    end
                    4'b1101:begin
                        led6<=1;
                    end
                    default:begin
                        ledefo2<=1;
                    end
                endcase
            end
            4'b1101:begin
                case(colunadeb)
                    4'b0111:begin
                        led7<=1;
                    end
                    4'b1011:begin
                        led8<=1;
                    end
                    4'b1101:begin
                        led9<=1;
                    end
                    default:begin
                    ledefo3<=1;
                    end
                endcase
                memlinha<=4'b1110;
            end
            4'b1110:begin
                case(colunadeb)
                    4'b1011:begin
                        led0<=1;
                    end
                    4'b1101:begin
                        ledzeppelin<=1;
                    end
                    default:begin
                        ledefo4<=1;
                    end
                    memlinha<=4'b0111;
                endcase
            end
            default:begin
                ledefo5<=1;
            end
        endcase

    end




endmodule
/*
module porraninhuma(led0,led1,led2,led3,led4,led5,led6,led7,memlinha,memcoluna);
    //input [4:1]memlinha;
    //output reg[4:1]memcoluna;
    input [4:1]memcoluna;
    output reg[4:1]memlinha;
    output reg led0;
    output reg led1;
    output reg led2;
    output reg led3;
    output reg led4;
    output reg led5;
    output reg led6;
    output reg led7;



    initial begin
        led0<=0;
        led1<=0;
        led2<=0;
        led3<=0;
        led4<=0;
        led5<=0;
        led6<=0;
        led7<=0;
        memlinha[1]<=0;
        memlinha[2]<=0;
        memlinha[3]<=0;
        memlinha[4]<=0;
    end



    always@(*)begin
        led0<=memlinha[1];
        led1<=memlinha[2];
        led2<=memlinha[3];
        led3<=memlinha[4];
        led4<=memcoluna[1];
        led5<=memcoluna[2];
        led6<=memcoluna[3];
        led7<=memcoluna[4];
    end



endmodule
*/

module porraninhuma(clk,led1,led2,led3,led4,led5,led6,led7,led8,led0,led9,ledzeppelin,memlinha,memcoluna,ledefo,ledefo1,ledefo2,ledefo3,ledefo4,ledefo5);
    input [1:4]memcoluna;
    output reg[1:4]memlinha;
    wire [1:4]colunadeb;
    output reg led8;
    output reg led1;
    output reg led2;
    output reg led3;
    output reg led4;
    output reg led5;
    output reg led6;
    output reg led9;
    output reg led0;
    output reg ledzeppelin;
    output reg led7;
    output reg ledefo,ledefo1,ledefo2,ledefo3,ledefo4,ledefo5;
    reg c;
    input clk;
    integer counter;
    reg clk2;

    debounce D0(clk, memcoluna[1], colunadeb[1]);
    debounce D1(clk, memcoluna[2], colunadeb[2]);
    debounce D2(clk, memcoluna[3], colunadeb[3]);
    debounce D3(clk, memcoluna[4], colunadeb[4]);

    //module pra clock auxiliar

    initial begin
        led1<=0;
        led2<=0;
        led3<=0;
        led4<=0;
        led5<=0;
        led6<=0;
        led7<=0;
        led8<=0;
        led9<=0;
        led0<=0;
        ledefo<=0;
        ledefo1<=0;
        ledefo2<=0;
        ledefo3<=0;
        ledefo4<=0;
        ledefo5<=0;
        ledzeppelin<=0;
        c<=0;
        memlinha<=4'b1110;
    end

    always@(posedge clk)begin
        if(c==1000000)begin
            clk2 <= ~clk2;
            c<=0;
        end
        else
            c<=c+1;
    end

    always@(posedge clk2)begin

        case(memlinha)
            4'b0111:begin
                memlinha<=4'b1011;
            end
            4'b1011:begin
                memlinha<=4'b1101;
            end
            4'b1101:begin
                memlinha<=4'b1110;
            end
            4'b1110:begin
                memlinha<=4'b0111;
            end
            default:begin
                ledefo<=1;
            end
        endcase
    end

    always@(posedge clk2)begin

        case(memlinha)
            4'b0111:begin
                case(colunadeb)
                    4'b0111:begin
                        led1<=1;
                    end
                    4'b1011:begin
                        led2<=1;
                    end
                    4'b1101:begin
                        led3<=1;
                    end
                    default:begin
                        memlinha <= 4'b1011;
                    end
                endcase
            end
            4'b1011:begin
                case(colunadeb)
                    4'b0111:begin
                        led4<=1;
                    end
                    4'b1011:begin
                        led5<=1;
                    end
                    4'b1101:begin
                        led6<=1;
                    end
                    default:begin
                        ledefo2<=1;
                    end
                endcase
            end
            4'b1101:begin
                case(colunadeb)
                    4'b0111:begin
                        led7<=1;
                    end
                    4'b1011:begin
                        led8<=1;
                    end
                    4'b1101:begin
                        led9<=1;
                    end
                    default:begin
                    ledefo3<=1;
                    end
                endcase
                memlinha<=4'b1110;
            end
            4'b1110:begin
                case(colunadeb)
                    4'b1011:begin
                        led0<=1;
                    end
                    4'b1101:begin
                        ledzeppelin<=1;
                    end
                    default:begin
                        ledefo4<=1;
                    end
                    memlinha<=4'b0111;
                endcase
            end
            default:begin
                ledefo5<=1;
            end
        endcase

    end




endmodule