library ieee ;
use ieee.std_logic_1164.all;
use work.all;


entity dff is
port(	dado:	in std_logic;
	    clock:	in std_logic;
	    saida:	out std_logic
);
end dff;


architecture behv of dff is
begin

    process(dado, clock)
    begin

	--if (clock='1' and clock'event) then
	if (clock='1' ) then
	    saida <= dado;
	end if;

    end process;

end behv;