lab4

module counter (
input clk,
input rst,
input drc,
input [2:0] num,
output [2:0] count
//output wire [7:0] out
);
//reg [6:0] count;

always @ (posedge clk) begin
  if (rst)
    if (drc)
       assign count = 3'b000; //rst high, count down
    else
       assign count = count;       //rst high, count up
  else
    if (drc)
       assign count = count + 1;   //
    else
       assign count = count - 1;
end

endmodule

module seven_seg_decoder (
input [2:0] num,
output [6:0] count
);

always @(*)
    begin
        case(num)
        3'b000: assign count = 7'b1111110; // "0"
        3'b001: assign count = 7'b0110000; // "1"
        3'b010: assign count = 7'b1101101; // "2"
        3'b011: assign count = 7'b1111001; // "3"
        3'b100: assign count = 7'b0110011; // "4"
        3'b101: assign count = 7'b1011011; // "5"
        3'b110: assign count = 7'b1011111; // "6"
        3'b111: assign count = 7'b1110000; // "7"
        default: assign count = 7'b0000000;

        endcase
end
endmodule