Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- module div (
- input signed [31:0] A,
- input signed [31:0] B,
- input clk,
- input reset,
- input DivCon,
- output reg signed [31:0] hi,
- output reg signed [31:0] lo,
- output reg exc
- );
- reg signed [63:0] remainder;
- reg signed [63:0] Divisor;
- reg signed [31:0] quo;
- reg signed [63:0] aux;
- integer i;
- initial begin
- i = 32;
- end
- always @ (posedge clk) begin
- if (reset == 1) begin
- remainder = 64'b0;
- Divisor = 64'b0;
- quo = 32'b0;
- aux = 64'b0;
- end
- if (DivCon == 1) begin
- if (i > 31) begin
- if (B == 32'b0) begin
- exc = 1;
- i = 0;
- end
- else begin
- remainder = {32'b0, A};
- Divisor = {B, 32'b0};
- quo = 32'b0;
- i = 0;
- exc = 1'b0;
- end
- end
- end
- if (i < 32) begin
- aux = ~Divisor + 1;
- aux = remainder + aux;
- case (aux[63])
- 1'b1: begin
- quo = quo <<< 1;
- Divisor = Divisor >>> 1;
- end
- 1'b0: begin
- quo = quo <<< 1;
- quo = quo + 1;
- Divisor = Divisor >>> 1;
- //quo = {quo[31:1], 1'b1};
- remainder = aux;
- end
- endcase
- i = i + 1;
- //hi = i;
- if (i == 32) begin
- hi = quo;
- lo = remainder[31:0];
- end
- end
- end
- endmodule //
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement