module DE1_SoC_Computer (
    ////////////////////////////////////
    // FPGA Pins
    ////////////////////////////////////

    // Clock pins
    CLOCK_50,
    CLOCK2_50,
    CLOCK3_50,
    CLOCK4_50,

    // ADC
    ADC_CS_N,
    ADC_DIN,
    ADC_DOUT,
    ADC_SCLK,

    // Audio
    AUD_ADCDAT,
    AUD_ADCLRCK,
    AUD_BCLK,
    AUD_DACDAT,
    AUD_DACLRCK,
    AUD_XCK,

    // SDRAM
    DRAM_ADDR,
    DRAM_BA,
    DRAM_CAS_N,
    DRAM_CKE,
    DRAM_CLK,
    DRAM_CS_N,
    DRAM_DQ,
    DRAM_LDQM,
    DRAM_RAS_N,
    DRAM_UDQM,
    DRAM_WE_N,

    // I2C Bus for Configuration of the Audio and Video-In Chips
    FPGA_I2C_SCLK,
    FPGA_I2C_SDAT,

    // 40-Pin Headers
    GPIO_0,
    GPIO_1,

    // Seven Segment Displays
    HEX0,
    HEX1,
    HEX2,
    HEX3,
    HEX4,
    HEX5,

    // IR
    IRDA_RXD,
    IRDA_TXD,

    // Pushbuttons
    KEY,

    // LEDs
    LEDR,

    // PS2 Ports
    PS2_CLK,
    PS2_DAT,

    PS2_CLK2,
    PS2_DAT2,

    // Slider Switches
    SW,

    // Video-In
    TD_CLK27,
    TD_DATA,
    TD_HS,
    TD_RESET_N,
    TD_VS,

    // VGA
    VGA_B,
    VGA_BLANK_N,
    VGA_CLK,
    VGA_G,
    VGA_HS,
    VGA_R,
    VGA_SYNC_N,
    VGA_VS,

    ////////////////////////////////////
    // HPS Pins
    ////////////////////////////////////

    // DDR3 SDRAM
    HPS_DDR3_ADDR,
    HPS_DDR3_BA,
    HPS_DDR3_CAS_N,
    HPS_DDR3_CKE,
    HPS_DDR3_CK_N,
    HPS_DDR3_CK_P,
    HPS_DDR3_CS_N,
    HPS_DDR3_DM,
    HPS_DDR3_DQ,
    HPS_DDR3_DQS_N,
    HPS_DDR3_DQS_P,
    HPS_DDR3_ODT,
    HPS_DDR3_RAS_N,
    HPS_DDR3_RESET_N,
    HPS_DDR3_RZQ,
    HPS_DDR3_WE_N,

    // Ethernet
    HPS_ENET_GTX_CLK,
    HPS_ENET_INT_N,
    HPS_ENET_MDC,
    HPS_ENET_MDIO,
    HPS_ENET_RX_CLK,
    HPS_ENET_RX_DATA,
    HPS_ENET_RX_DV,
    HPS_ENET_TX_DATA,
    HPS_ENET_TX_EN,

    // Flash
    HPS_FLASH_DATA,
    HPS_FLASH_DCLK,
    HPS_FLASH_NCSO,

    // Accelerometer
    HPS_GSENSOR_INT,

    // General Purpose I/O
    HPS_GPIO,

    // I2C
    HPS_I2C_CONTROL,
    HPS_I2C1_SCLK,
    HPS_I2C1_SDAT,
    HPS_I2C2_SCLK,
    HPS_I2C2_SDAT,

    // Pushbutton
    HPS_KEY,

    // LED
    HPS_LED,

    // SD Card
    HPS_SD_CLK,
    HPS_SD_CMD,
    HPS_SD_DATA,

    // SPI
    HPS_SPIM_CLK,
    HPS_SPIM_MISO,
    HPS_SPIM_MOSI,
    HPS_SPIM_SS,

    // UART
    HPS_UART_RX,
    HPS_UART_TX,

    // USB
    HPS_CONV_USB_N,
    HPS_USB_CLKOUT,
    HPS_USB_DATA,
    HPS_USB_DIR,
    HPS_USB_NXT,
    HPS_USB_STP
);

//=======================================================
//  PARAMETER declarations
//=======================================================


//=======================================================
//  PORT declarations
//=======================================================

////////////////////////////////////
// FPGA Pins
////////////////////////////////////

// Clock pins
input                       CLOCK_50;
input                       CLOCK2_50;
input                       CLOCK3_50;
input                       CLOCK4_50;

// ADC
inout                       ADC_CS_N;
output                  ADC_DIN;
input                       ADC_DOUT;
output                  ADC_SCLK;

// Audio
input                       AUD_ADCDAT;
inout                       AUD_ADCLRCK;
inout                       AUD_BCLK;
output                  AUD_DACDAT;
inout                       AUD_DACLRCK;
output                  AUD_XCK;

// SDRAM
output      [12: 0] DRAM_ADDR;
output      [ 1: 0] DRAM_BA;
output                  DRAM_CAS_N;
output                  DRAM_CKE;
output                  DRAM_CLK;
output                  DRAM_CS_N;
inout           [15: 0] DRAM_DQ;
output                  DRAM_LDQM;
output                  DRAM_RAS_N;
output                  DRAM_UDQM;
output                  DRAM_WE_N;

// I2C Bus for Configuration of the Audio and Video-In Chips
output                  FPGA_I2C_SCLK;
inout                       FPGA_I2C_SDAT;

// 40-pin headers
inout           [35: 0] GPIO_0;
inout           [35: 0] GPIO_1;

// Seven Segment Displays
output      [ 6: 0] HEX0;
output      [ 6: 0] HEX1;
output      [ 6: 0] HEX2;
output      [ 6: 0] HEX3;
output      [ 6: 0] HEX4;
output      [ 6: 0] HEX5;

// IR
input                       IRDA_RXD;
output                  IRDA_TXD;

// Pushbuttons
input           [ 3: 0] KEY;

// LEDs
output      [ 9: 0] LEDR;

// PS2 Ports
inout                       PS2_CLK;
inout                       PS2_DAT;

inout                       PS2_CLK2;
inout                       PS2_DAT2;

// Slider Switches
input           [ 9: 0] SW;

// Video-In
input                       TD_CLK27;
input           [ 7: 0] TD_DATA;
input                       TD_HS;
output                  TD_RESET_N;
input                       TD_VS;

// VGA
output      [ 7: 0] VGA_B;
output                  VGA_BLANK_N;
output                  VGA_CLK;
output      [ 7: 0] VGA_G;
output                  VGA_HS;
output      [ 7: 0] VGA_R;
output                  VGA_SYNC_N;
output                  VGA_VS;



////////////////////////////////////
// HPS Pins
////////////////////////////////////

// DDR3 SDRAM
output      [14: 0] HPS_DDR3_ADDR;
output      [ 2: 0]  HPS_DDR3_BA;
output                  HPS_DDR3_CAS_N;
output                  HPS_DDR3_CKE;
output                  HPS_DDR3_CK_N;
output                  HPS_DDR3_CK_P;
output                  HPS_DDR3_CS_N;
output      [ 3: 0] HPS_DDR3_DM;
inout           [31: 0] HPS_DDR3_DQ;
inout           [ 3: 0] HPS_DDR3_DQS_N;
inout           [ 3: 0] HPS_DDR3_DQS_P;
output                  HPS_DDR3_ODT;
output                  HPS_DDR3_RAS_N;
output                  HPS_DDR3_RESET_N;
input                       HPS_DDR3_RZQ;
output                  HPS_DDR3_WE_N;

// Ethernet
output                  HPS_ENET_GTX_CLK;
inout                       HPS_ENET_INT_N;
output                  HPS_ENET_MDC;
inout                       HPS_ENET_MDIO;
input                       HPS_ENET_RX_CLK;
input           [ 3: 0] HPS_ENET_RX_DATA;
input                       HPS_ENET_RX_DV;
output      [ 3: 0] HPS_ENET_TX_DATA;
output                  HPS_ENET_TX_EN;

// Flash
inout           [ 3: 0] HPS_FLASH_DATA;
output                  HPS_FLASH_DCLK;
output                  HPS_FLASH_NCSO;

// Accelerometer
inout                       HPS_GSENSOR_INT;

// General Purpose I/O
inout           [ 1: 0] HPS_GPIO;

// I2C
inout                       HPS_I2C_CONTROL;
inout                       HPS_I2C1_SCLK;
inout                       HPS_I2C1_SDAT;
inout                       HPS_I2C2_SCLK;
inout                       HPS_I2C2_SDAT;

// Pushbutton
inout                       HPS_KEY;

// LED
inout                       HPS_LED;

// SD Card
output                  HPS_SD_CLK;
inout                       HPS_SD_CMD;
inout           [ 3: 0] HPS_SD_DATA;

// SPI
output                  HPS_SPIM_CLK;
input                       HPS_SPIM_MISO;
output                  HPS_SPIM_MOSI;
inout                       HPS_SPIM_SS;

// UART
input                       HPS_UART_RX;
output                  HPS_UART_TX;

// USB
inout                       HPS_CONV_USB_N;
input                       HPS_USB_CLKOUT;
inout           [ 7: 0] HPS_USB_DATA;
input                       HPS_USB_DIR;
input                       HPS_USB_NXT;
output                  HPS_USB_STP;

//=======================================================
//  REG/WIRE declarations
//=======================================================

HexDigit Digit0(HEX0, mid_out[3:0]);
HexDigit Digit1(HEX1, mid_out[7:4]);
HexDigit Digit2(HEX2, mid_out[11:8]);
HexDigit Digit3(HEX3, mid_out[15:12]);
HexDigit Digit4(HEX4, {2'b0,mid_out[17:16]});

//=======================================================
// Bus controller for AVALON bus-master
//=======================================================
// computes DDS for sine wave and fills audio FIFO

reg [31:0] bus_addr ; // Avalon address
// see
// ftp://ftp.altera.com/up/pub/Altera_Material/15.1/University_Program_IP_Cores/Audio_Video/Audio.pdf
// for addresses
wire [31:0] audio_base_address = 32'h00003040 ;  // Avalon address
wire [31:0] audio_fifo_address = 32'h00003044 ;  // Avalon address +4 offset
wire [31:0] audio_left_address = 32'h00003048 ;  // Avalon address +8
wire [31:0] audio_right_address = 32'h0000304c ;  // Avalon address +12
reg [3:0] bus_byte_enable ; // four bit byte read/write mask
reg bus_read  ;       // high when requesting data
reg bus_write ;      //  high when writing data
reg [31:0] bus_write_data ; //  data to send to Avalog bus
wire bus_ack  ;       //  Avalon bus raises this when done
wire [31:0] bus_read_data ; // data from Avalon bus
reg [30:0] timer ;
reg [3:0] state ;
wire state_clock ;

// current free words in audio interface
reg [7:0] fifo_space ;

//Stuff we added
reg start; //control signal for columns to calculate 1 time step
wire signed[17:0]  mid_out; //output of the middle node of the drum, the sound

always @(posedge CLOCK_50) begin //CLOCK_50

    // reset state machine and read/write controls
    if (~KEY[0]) begin
        state <= 0 ;
        bus_read <= 0 ; // set to one if a read opeation from bus
        bus_write <= 0 ; // set to one if a write operation to bus
        timer <= 0;
        start <= 0;
    end
    else begin
        // timer just for deubgging
        timer <= timer + 1;
    end

    // set up read FIFO available space
    if (state==4'd0) begin
        bus_addr <= audio_fifo_address ;
        bus_read <= 1'b1 ;
        bus_byte_enable <= 4'b1111;
        state <= 4'd1 ; // wait for read ACK
    end

    // wait for read ACK and read the fifo available
    // bus ACK is high when data is available
    if (state==4'd1 && bus_ack==1) begin
        state <= 4'd2 ; //4'd2
        // FIFO space is in high byte
        fifo_space <= (bus_read_data>>24) ;
        // end the read
        bus_read <= 1'b0 ;
    end

    // When there is room in the FIFO
    // -- set start high to begin computation of next time step
    // -- start write to fifo for each channel
    // -- first the left channel
    if (state==4'd2 && fifo_space>8'd2) begin //
        state <= 4'd3;
        start <= 1'b1;
        bus_write_data <= (mid_out << 14) ;
        bus_addr <= audio_left_address ;
        bus_byte_enable <= 4'b1111;
        bus_write <= 1'b1 ;
    end
    // if no space, try again later
    else if (state==4'd2 && fifo_space<=8'd2) begin
        state <= 4'b0 ;
    end

    // detect bus-transaction-complete ACK
    // for left channel write
    // You MUST do this check
    if (state==4'd3 && bus_ack==1) begin
        state <= 4'd4 ;
        bus_write <= 0;
        start <= 1'b0;
    end

    // -- now the right channel
    if (state==4'd4) begin //
        state <= 4'd5;
        bus_addr <= audio_right_address ;
        bus_write <= 1'b1 ;
    end

    // detect bus-transaction-complete ACK
    // for right channel write
    // You MUST do this check
    if (state==4'd5 && bus_ack==1) begin
        state <= 4'd0 ;
        bus_write <= 0;
    end

end // always @(posedge state_clock)

maker m(.CLOCK_50(CLOCK_50),
          .reset(KEY[0]),
          .start(start),
          .sound(mid_out),
          .sw(SW[9:0]));
//=======================================================
//  Structural coding
//=======================================================


Computer_System The_System (
    ////////////////////////////////////
    // FPGA Side
    ////////////////////////////////////

    // Global signals
    .system_pll_ref_clk_clk                 (CLOCK_50),
    .system_pll_ref_reset_reset         (1'b0),
    .sdram_clk_clk                              (state_clock),

    // AV Config
    .av_config_SCLK                         (FPGA_I2C_SCLK),
    .av_config_SDAT                         (FPGA_I2C_SDAT),

    // Audio Subsystem
    .audio_pll_ref_clk_clk                  (CLOCK3_50),
    .audio_pll_ref_reset_reset              (1'b0),
    .audio_clk_clk                              (AUD_XCK),
    .audio_ADCDAT                               (AUD_ADCDAT),
    .audio_ADCLRCK                              (AUD_ADCLRCK),
    .audio_BCLK                                 (AUD_BCLK),
    .audio_DACDAT                               (AUD_DACDAT),
    .audio_DACLRCK                              (AUD_DACLRCK),

    // bus-master state machine interface
    .bus_master_audio_external_interface_address     (bus_addr),
    .bus_master_audio_external_interface_byte_enable (bus_byte_enable),
    .bus_master_audio_external_interface_read        (bus_read),
    .bus_master_audio_external_interface_write       (bus_write),
    .bus_master_audio_external_interface_write_data  (bus_write_data),
    .bus_master_audio_external_interface_acknowledge (bus_ack),
    .bus_master_audio_external_interface_read_data   (bus_read_data),


    ////////////////////////////////////
    // HPS Side
    ////////////////////////////////////
    // DDR3 SDRAM
    .memory_mem_a           (HPS_DDR3_ADDR),
    .memory_mem_ba          (HPS_DDR3_BA),
    .memory_mem_ck          (HPS_DDR3_CK_P),
    .memory_mem_ck_n        (HPS_DDR3_CK_N),
    .memory_mem_cke     (HPS_DDR3_CKE),
    .memory_mem_cs_n        (HPS_DDR3_CS_N),
    .memory_mem_ras_n       (HPS_DDR3_RAS_N),
    .memory_mem_cas_n       (HPS_DDR3_CAS_N),
    .memory_mem_we_n        (HPS_DDR3_WE_N),
    .memory_mem_reset_n (HPS_DDR3_RESET_N),
    .memory_mem_dq          (HPS_DDR3_DQ),
    .memory_mem_dqs     (HPS_DDR3_DQS_P),
    .memory_mem_dqs_n       (HPS_DDR3_DQS_N),
    .memory_mem_odt     (HPS_DDR3_ODT),
    .memory_mem_dm          (HPS_DDR3_DM),
    .memory_oct_rzqin       (HPS_DDR3_RZQ),

    // Ethernet
    .hps_io_hps_io_gpio_inst_GPIO35 (HPS_ENET_INT_N),
    .hps_io_hps_io_emac1_inst_TX_CLK    (HPS_ENET_GTX_CLK),
    .hps_io_hps_io_emac1_inst_TXD0  (HPS_ENET_TX_DATA[0]),
    .hps_io_hps_io_emac1_inst_TXD1  (HPS_ENET_TX_DATA[1]),
    .hps_io_hps_io_emac1_inst_TXD2  (HPS_ENET_TX_DATA[2]),
    .hps_io_hps_io_emac1_inst_TXD3  (HPS_ENET_TX_DATA[3]),
    .hps_io_hps_io_emac1_inst_RXD0  (HPS_ENET_RX_DATA[0]),
    .hps_io_hps_io_emac1_inst_MDIO  (HPS_ENET_MDIO),
    .hps_io_hps_io_emac1_inst_MDC       (HPS_ENET_MDC),
    .hps_io_hps_io_emac1_inst_RX_CTL    (HPS_ENET_RX_DV),
    .hps_io_hps_io_emac1_inst_TX_CTL    (HPS_ENET_TX_EN),
    .hps_io_hps_io_emac1_inst_RX_CLK    (HPS_ENET_RX_CLK),
    .hps_io_hps_io_emac1_inst_RXD1  (HPS_ENET_RX_DATA[1]),
    .hps_io_hps_io_emac1_inst_RXD2  (HPS_ENET_RX_DATA[2]),
    .hps_io_hps_io_emac1_inst_RXD3  (HPS_ENET_RX_DATA[3]),

    // Flash
    .hps_io_hps_io_qspi_inst_IO0    (HPS_FLASH_DATA[0]),
    .hps_io_hps_io_qspi_inst_IO1    (HPS_FLASH_DATA[1]),
    .hps_io_hps_io_qspi_inst_IO2    (HPS_FLASH_DATA[2]),
    .hps_io_hps_io_qspi_inst_IO3    (HPS_FLASH_DATA[3]),
    .hps_io_hps_io_qspi_inst_SS0    (HPS_FLASH_NCSO),
    .hps_io_hps_io_qspi_inst_CLK    (HPS_FLASH_DCLK),

    // Accelerometer
    .hps_io_hps_io_gpio_inst_GPIO61 (HPS_GSENSOR_INT),

    //.adc_sclk                        (ADC_SCLK),
    //.adc_cs_n                        (ADC_CS_N),
    //.adc_dout                        (ADC_DOUT),
    //.adc_din                         (ADC_DIN),

    // General Purpose I/O
    .hps_io_hps_io_gpio_inst_GPIO40 (HPS_GPIO[0]),
    .hps_io_hps_io_gpio_inst_GPIO41 (HPS_GPIO[1]),

    // I2C
    .hps_io_hps_io_gpio_inst_GPIO48 (HPS_I2C_CONTROL),
    .hps_io_hps_io_i2c0_inst_SDA        (HPS_I2C1_SDAT),
    .hps_io_hps_io_i2c0_inst_SCL        (HPS_I2C1_SCLK),
    .hps_io_hps_io_i2c1_inst_SDA        (HPS_I2C2_SDAT),
    .hps_io_hps_io_i2c1_inst_SCL        (HPS_I2C2_SCLK),

    // Pushbutton
    .hps_io_hps_io_gpio_inst_GPIO54 (HPS_KEY),

    // LED
    .hps_io_hps_io_gpio_inst_GPIO53 (HPS_LED),

    // SD Card
    .hps_io_hps_io_sdio_inst_CMD    (HPS_SD_CMD),
    .hps_io_hps_io_sdio_inst_D0 (HPS_SD_DATA[0]),
    .hps_io_hps_io_sdio_inst_D1 (HPS_SD_DATA[1]),
    .hps_io_hps_io_sdio_inst_CLK    (HPS_SD_CLK),
    .hps_io_hps_io_sdio_inst_D2 (HPS_SD_DATA[2]),
    .hps_io_hps_io_sdio_inst_D3 (HPS_SD_DATA[3]),

    // SPI
    .hps_io_hps_io_spim1_inst_CLK       (HPS_SPIM_CLK),
    .hps_io_hps_io_spim1_inst_MOSI  (HPS_SPIM_MOSI),
    .hps_io_hps_io_spim1_inst_MISO  (HPS_SPIM_MISO),
    .hps_io_hps_io_spim1_inst_SS0       (HPS_SPIM_SS),

    // UART
    .hps_io_hps_io_uart0_inst_RX    (HPS_UART_RX),
    .hps_io_hps_io_uart0_inst_TX    (HPS_UART_TX),

    // USB
    .hps_io_hps_io_gpio_inst_GPIO09 (HPS_CONV_USB_N),
    .hps_io_hps_io_usb1_inst_D0     (HPS_USB_DATA[0]),
    .hps_io_hps_io_usb1_inst_D1     (HPS_USB_DATA[1]),
    .hps_io_hps_io_usb1_inst_D2     (HPS_USB_DATA[2]),
    .hps_io_hps_io_usb1_inst_D3     (HPS_USB_DATA[3]),
    .hps_io_hps_io_usb1_inst_D4     (HPS_USB_DATA[4]),
    .hps_io_hps_io_usb1_inst_D5     (HPS_USB_DATA[5]),
    .hps_io_hps_io_usb1_inst_D6     (HPS_USB_DATA[6]),
    .hps_io_hps_io_usb1_inst_D7     (HPS_USB_DATA[7]),
    .hps_io_hps_io_usb1_inst_CLK        (HPS_USB_CLKOUT),
    .hps_io_hps_io_usb1_inst_STP        (HPS_USB_STP),
    .hps_io_hps_io_usb1_inst_DIR        (HPS_USB_DIR),
    .hps_io_hps_io_usb1_inst_NXT        (HPS_USB_NXT)
);


endmodule

//module that generates the columns and connections between them
//provides clock, reset, and start to the column modules and reads output of middle node from middle column
module maker(
    input CLOCK_50, reset, start,
    input [9:0] sw,
    output [17:0] sound
);
    parameter n = 170; // number of columns
    parameter column_size = 500; // number of rows

//set various parameters of the wave equation using the switches on the FPGA
    wire[1:0] gain; // left shift by gain in rho equation
    assign gain = sw[8:7];
    wire [17:0] rho0; //right shift rho0 by switch 4
    assign rho0 = (18'h0_8000 >> sw[4]);
    parameter rho_max = 18'h0_fae1; //about 0.49
    wire [4:0] etadt; //damping factor, default of a right shift by 12
    assign etadt = sw[0] ? (5'd8 + sw[3:1]) : 12;
    wire signed [17:0] u_shift, u_sq, rho_plus, rho;

    //global rho calculation
    //wires[(n-1)>>].sound gives the middle row of the middle column -- the center of the drum
    assign u_shift = (wires[(n-1)>>1].sound >>> gain);
    signed_mult u_squared(u_sq, u_shift, u_shift);
    assign rho_plus = u_sq + rho0;
    assign rho = (rho_plus > rho_max) ? rho_max : rho_plus;

    assign sound = wires[(n-1)>>1].sound; // get sound from middle node
    genvar i;
    reg [8:0] row = 0; //will be constantly incremented while the reset button is held, used for writing initial values
    generate
        for(i = 0; i < n; i = i+1) begin : wires
            wire [4:0] etadts; //damping factor input
            wire signed [17:0] wout, sound, rhos; //wout is position of node in current row, passed to neighboring columns
            wire signed [17:0] iminus, iplus; //input from neighboring columns
            reg [8:0] curr_wradd_init, prev_wradd_init; //initial values
            reg [17:0] curr_in_init, prev_in_init; //initial values
            wire [8:0] column_size; //input of column size into columns
        end //for
        for(i = 0; i < n; i = i+1) begin : columns
            //attach to neighboring column or 0 if on an edge
            if (i == 0)
                assign wires[i].iminus = 18'h0;
            else
                assign wires[i].iminus = wires[i-1].wout;
            if (i == n-1)
                assign wires[i].iplus = 18'h0;
            else
                assign wires[i].iplus = wires[i+1].wout;

            //inputs for calculations
            assign wires[i].rhos = rho;
            assign wires[i].etadts = etadt;
            assign wires[i].column_size = column_size;

            column ccc(.CLOCK_50(CLOCK_50),
                        .reset(reset),
                        .start(start),
                        .iminus(wires[i].iminus),
                        .iplus(wires[i].iplus),
                        .curr_wradd_init(wires[i].curr_wradd_init),
                        .prev_wradd_init(wires[i].prev_wradd_init),
                        .curr_in_init(wires[i].curr_in_init),
                        .prev_in_init(wires[i].prev_in_init),
                        .rho(wires[i].rhos),
                        .etadt(wires[i].etadts),
                        .jplus_out(wires[i].wout),
                        .sound(wires[i].sound),
                        .column_size(wires[i].column_size));
        end //for

        always @ (posedge CLOCK_50) begin
            //cycle row through all row values to write initial values while reset is held
            if (reset==0) begin
                if (9'd0 > row || row >= column_size-1) begin
                    row <= 9'd0;
                end
                else begin
                    row <= row + 1;
                end
            end //if
        end //always
        //our initial waveform is a 17x17 gaussian with max magnitude 0.25, in the center of the drum
        //the relevant values were generated by matlab
        //all other nodes are initialized to 0
        for(i=0; i < n; i=i+1) begin : inits
            always @ (posedge CLOCK_50) begin
                wires[i].curr_wradd_init <= row;
                wires[i].prev_wradd_init <= row;
                //initializing nodes not in the center 17x17 to 0
                if (i < ((n-1)>>1)-8 || i > ((n-1)>>1)+8 || row < ((column_size-1)>>1)-8 || row > ((column_size-1)>>1)+8) begin
                    wires[i].curr_in_init <= 18'h0;
                    wires[i].prev_in_init <= 18'h0;
                end
                else begin
                    //case statement assigns values to the center 17x17
                    case(17*(row - (((column_size-1)>>1)-8)) + i - (((n-1)>>1)-8))
                        0: begin
                            wires[i].curr_in_init <= 18'h00000;
                            wires[i].prev_in_init <= 18'h00000;
                        end
                        1: begin
                            wires[i].curr_in_init <= 18'h00000;
                            wires[i].prev_in_init <= 18'h00000;
                        end
                        2: begin
                            wires[i].curr_in_init <= 18'h00001;
                            wires[i].prev_in_init <= 18'h00001;
                        end
                        3: begin
                            wires[i].curr_in_init <= 18'h00004;
                            wires[i].prev_in_init <= 18'h00004;
                        end
                        4: begin
                            wires[i].curr_in_init <= 18'h0000a;
                            wires[i].prev_in_init <= 18'h0000a;
                        end
                        5: begin
                            wires[i].curr_in_init <= 18'h00016;
                            wires[i].prev_in_init <= 18'h00016;
                        end
                        6: begin
                            wires[i].curr_in_init <= 18'h00024;
                            wires[i].prev_in_init <= 18'h00024;
                        end
                        7: begin
                            wires[i].curr_in_init <= 18'h00031;
                            wires[i].prev_in_init <= 18'h00031;
                        end
                        8: begin
                            wires[i].curr_in_init <= 18'h00036;
                            wires[i].prev_in_init <= 18'h00036;
                        end
                        9: begin
                            wires[i].curr_in_init <= 18'h00031;
                            wires[i].prev_in_init <= 18'h00031;
                        end
                        10: begin
                            wires[i].curr_in_init <= 18'h00024;
                            wires[i].prev_in_init <= 18'h00024;
                        end
                        11: begin
                            wires[i].curr_in_init <= 18'h00016;
                            wires[i].prev_in_init <= 18'h00016;
                        end
                        12: begin
                            wires[i].curr_in_init <= 18'h0000a;
                            wires[i].prev_in_init <= 18'h0000a;
                        end
                        13: begin
                            wires[i].curr_in_init <= 18'h00004;
                            wires[i].prev_in_init <= 18'h00004;
                        end
                        14: begin
                            wires[i].curr_in_init <= 18'h00001;
                            wires[i].prev_in_init <= 18'h00001;
                        end
                        15: begin
                            wires[i].curr_in_init <= 18'h00000;
                            wires[i].prev_in_init <= 18'h00000;
                        end
                        16: begin
                            wires[i].curr_in_init <= 18'h00000;
                            wires[i].prev_in_init <= 18'h00000;
                        end
                        17: begin
                            wires[i].curr_in_init <= 18'h00000;
                            wires[i].prev_in_init <= 18'h00000;
                        end
                        18: begin
                            wires[i].curr_in_init <= 18'h00001;
                            wires[i].prev_in_init <= 18'h00001;
                        end
                        19: begin
                            wires[i].curr_in_init <= 18'h00006;
                            wires[i].prev_in_init <= 18'h00006;
                        end
                        20: begin
                            wires[i].curr_in_init <= 18'h00014;
                            wires[i].prev_in_init <= 18'h00014;
                        end
                        21: begin
                            wires[i].curr_in_init <= 18'h00031;
                            wires[i].prev_in_init <= 18'h00031;
                        end
                        22: begin
                            wires[i].curr_in_init <= 18'h00063;
                            wires[i].prev_in_init <= 18'h00063;
                        end
                        23: begin
                            wires[i].curr_in_init <= 18'h000a3;
                            wires[i].prev_in_init <= 18'h000a3;
                        end
                        24: begin
                            wires[i].curr_in_init <= 18'h000dc;
                            wires[i].prev_in_init <= 18'h000dc;
                        end
                        25: begin
                            wires[i].curr_in_init <= 18'h000f4;
                            wires[i].prev_in_init <= 18'h000f4;
                        end
                        26: begin
                            wires[i].curr_in_init <= 18'h000dc;
                            wires[i].prev_in_init <= 18'h000dc;
                        end
                        27: begin
                            wires[i].curr_in_init <= 18'h000a3;
                            wires[i].prev_in_init <= 18'h000a3;
                        end
                        28: begin
                            wires[i].curr_in_init <= 18'h00063;
                            wires[i].prev_in_init <= 18'h00063;
                        end
                        29: begin
                            wires[i].curr_in_init <= 18'h00031;
                            wires[i].prev_in_init <= 18'h00031;
                        end
                        30: begin
                            wires[i].curr_in_init <= 18'h00014;
                            wires[i].prev_in_init <= 18'h00014;
                        end
                        31: begin
                            wires[i].curr_in_init <= 18'h00006;
                            wires[i].prev_in_init <= 18'h00006;
                        end
                        32: begin
                            wires[i].curr_in_init <= 18'h00001;
                            wires[i].prev_in_init <= 18'h00001;
                        end
                        33: begin
                            wires[i].curr_in_init <= 18'h00000;
                            wires[i].prev_in_init <= 18'h00000;
                        end
                        34: begin
                            wires[i].curr_in_init <= 18'h00001;
                            wires[i].prev_in_init <= 18'h00001;
                        end
                        35: begin
                            wires[i].curr_in_init <= 18'h00006;
                            wires[i].prev_in_init <= 18'h00006;
                        end
                        36: begin
                            wires[i].curr_in_init <= 18'h00018;
                            wires[i].prev_in_init <= 18'h00018;
                        end
                        37: begin
                            wires[i].curr_in_init <= 18'h00049;
                            wires[i].prev_in_init <= 18'h00049;
                        end
                        38: begin
                            wires[i].curr_in_init <= 18'h000b4;
                            wires[i].prev_in_init <= 18'h000b4;
                        end
                        39: begin
                            wires[i].curr_in_init <= 18'h0016c;
                            wires[i].prev_in_init <= 18'h0016c;
                        end
                        40: begin
                            wires[i].curr_in_init <= 18'h00258;
                            wires[i].prev_in_init <= 18'h00258;
                        end
                        41: begin
                            wires[i].curr_in_init <= 18'h0032a;
                            wires[i].prev_in_init <= 18'h0032a;
                        end
                        42: begin
                            wires[i].curr_in_init <= 18'h0037f;
                            wires[i].prev_in_init <= 18'h0037f;
                        end
                        43: begin
                            wires[i].curr_in_init <= 18'h0032a;
                            wires[i].prev_in_init <= 18'h0032a;
                        end
                        44: begin
                            wires[i].curr_in_init <= 18'h00258;
                            wires[i].prev_in_init <= 18'h00258;
                        end
                        45: begin
                            wires[i].curr_in_init <= 18'h0016c;
                            wires[i].prev_in_init <= 18'h0016c;
                        end
                        46: begin
                            wires[i].curr_in_init <= 18'h000b4;
                            wires[i].prev_in_init <= 18'h000b4;
                        end
                        47: begin
                            wires[i].curr_in_init <= 18'h00049;
                            wires[i].prev_in_init <= 18'h00049;
                        end
                        48: begin
                            wires[i].curr_in_init <= 18'h00018;
                            wires[i].prev_in_init <= 18'h00018;
                        end
                        49: begin
                            wires[i].curr_in_init <= 18'h00006;
                            wires[i].prev_in_init <= 18'h00006;
                        end
                        50: begin
                            wires[i].curr_in_init <= 18'h00001;
                            wires[i].prev_in_init <= 18'h00001;
                        end
                        51: begin
                            wires[i].curr_in_init <= 18'h00004;
                            wires[i].prev_in_init <= 18'h00004;
                        end
                        52: begin
                            wires[i].curr_in_init <= 18'h00014;
                            wires[i].prev_in_init <= 18'h00014;
                        end
                        53: begin
                            wires[i].curr_in_init <= 18'h00049;
                            wires[i].prev_in_init <= 18'h00049;
                        end
                        54: begin
                            wires[i].curr_in_init <= 18'h000dc;
                            wires[i].prev_in_init <= 18'h000dc;
                        end
                        55: begin
                            wires[i].curr_in_init <= 18'h0021f;
                            wires[i].prev_in_init <= 18'h0021f;
                        end
                        56: begin
                            wires[i].curr_in_init <= 18'h00445;
                            wires[i].prev_in_init <= 18'h00445;
                        end
                        57: begin
                            wires[i].curr_in_init <= 18'h0070a;
                            wires[i].prev_in_init <= 18'h0070a;
                        end
                        58: begin
                            wires[i].curr_in_init <= 18'h00981;
                            wires[i].prev_in_init <= 18'h00981;
                        end
                        59: begin
                            wires[i].curr_in_init <= 18'h00a81;
                            wires[i].prev_in_init <= 18'h00a81;
                        end
                        60: begin
                            wires[i].curr_in_init <= 18'h00981;
                            wires[i].prev_in_init <= 18'h00981;
                        end
                        61: begin
                            wires[i].curr_in_init <= 18'h0070a;
                            wires[i].prev_in_init <= 18'h0070a;
                        end
                        62: begin
                            wires[i].curr_in_init <= 18'h00445;
                            wires[i].prev_in_init <= 18'h00445;
                        end
                        63: begin
                            wires[i].curr_in_init <= 18'h0021f;
                            wires[i].prev_in_init <= 18'h0021f;
                        end
                        64: begin
                            wires[i].curr_in_init <= 18'h000dc;
                            wires[i].prev_in_init <= 18'h000dc;
                        end
                        65: begin
                            wires[i].curr_in_init <= 18'h00049;
                            wires[i].prev_in_init <= 18'h00049;
                        end
                        66: begin
                            wires[i].curr_in_init <= 18'h00014;
                            wires[i].prev_in_init <= 18'h00014;
                        end
                        67: begin
                            wires[i].curr_in_init <= 18'h00004;
                            wires[i].prev_in_init <= 18'h00004;
                        end
                        68: begin
                            wires[i].curr_in_init <= 18'h0000a;
                            wires[i].prev_in_init <= 18'h0000a;
                        end
                        69: begin
                            wires[i].curr_in_init <= 18'h00031;
                            wires[i].prev_in_init <= 18'h00031;
                        end
                        70: begin
                            wires[i].curr_in_init <= 18'h000b4;
                            wires[i].prev_in_init <= 18'h000b4;
                        end
                        71: begin
                            wires[i].curr_in_init <= 18'h0021f;
                            wires[i].prev_in_init <= 18'h0021f;
                        end
                        72: begin
                            wires[i].curr_in_init <= 18'h00537;
                            wires[i].prev_in_init <= 18'h00537;
                        end
                        73: begin
                            wires[i].curr_in_init <= 18'h00a81;
                            wires[i].prev_in_init <= 18'h00a81;
                        end
                        74: begin
                            wires[i].curr_in_init <= 18'h01152;
                            wires[i].prev_in_init <= 18'h01152;
                        end
                        75: begin
                            wires[i].curr_in_init <= 18'h01762;
                            wires[i].prev_in_init <= 18'h01762;
                        end
                        76: begin
                            wires[i].curr_in_init <= 18'h019d7;
                            wires[i].prev_in_init <= 18'h019d7;
                        end
                        77: begin
                            wires[i].curr_in_init <= 18'h01762;
                            wires[i].prev_in_init <= 18'h01762;
                        end
                        78: begin
                            wires[i].curr_in_init <= 18'h01152;
                            wires[i].prev_in_init <= 18'h01152;
                        end
                        79: begin
                            wires[i].curr_in_init <= 18'h00a81;
                            wires[i].prev_in_init <= 18'h00a81;
                        end
                        80: begin
                            wires[i].curr_in_init <= 18'h00537;
                            wires[i].prev_in_init <= 18'h00537;
                        end
                        81: begin
                            wires[i].curr_in_init <= 18'h0021f;
                            wires[i].prev_in_init <= 18'h0021f;
                        end
                        82: begin
                            wires[i].curr_in_init <= 18'h000b4;
                            wires[i].prev_in_init <= 18'h000b4;
                        end
                        83: begin
                            wires[i].curr_in_init <= 18'h00031;
                            wires[i].prev_in_init <= 18'h00031;
                        end
                        84: begin
                            wires[i].curr_in_init <= 18'h0000a;
                            wires[i].prev_in_init <= 18'h0000a;
                        end
                        85: begin
                            wires[i].curr_in_init <= 18'h00016;
                            wires[i].prev_in_init <= 18'h00016;
                        end
                        86: begin
                            wires[i].curr_in_init <= 18'h00063;
                            wires[i].prev_in_init <= 18'h00063;
                        end
                        87: begin
                            wires[i].curr_in_init <= 18'h0016c;
                            wires[i].prev_in_init <= 18'h0016c;
                        end
                        88: begin
                            wires[i].curr_in_init <= 18'h00445;
                            wires[i].prev_in_init <= 18'h00445;
                        end
                        89: begin
                            wires[i].curr_in_init <= 18'h00a81;
                            wires[i].prev_in_init <= 18'h00a81;
                        end
                        90: begin
                            wires[i].curr_in_init <= 18'h01528;
                            wires[i].prev_in_init <= 18'h01528;
                        end
                        91: begin
                            wires[i].curr_in_init <= 18'h022e2;
                            wires[i].prev_in_init <= 18'h022e2;
                        end
                        92: begin
                            wires[i].curr_in_init <= 18'h02f16;
                            wires[i].prev_in_init <= 18'h02f16;
                        end
                        93: begin
                            wires[i].curr_in_init <= 18'h0340a;
                            wires[i].prev_in_init <= 18'h0340a;
                        end
                        94: begin
                            wires[i].curr_in_init <= 18'h02f16;
                            wires[i].prev_in_init <= 18'h02f16;
                        end
                        95: begin
                            wires[i].curr_in_init <= 18'h022e2;
                            wires[i].prev_in_init <= 18'h022e2;
                        end
                        96: begin
                            wires[i].curr_in_init <= 18'h01528;
                            wires[i].prev_in_init <= 18'h01528;
                        end
                        97: begin
                            wires[i].curr_in_init <= 18'h00a81;
                            wires[i].prev_in_init <= 18'h00a81;
                        end
                        98: begin
                            wires[i].curr_in_init <= 18'h00445;
                            wires[i].prev_in_init <= 18'h00445;
                        end
                        99: begin
                            wires[i].curr_in_init <= 18'h0016c;
                            wires[i].prev_in_init <= 18'h0016c;
                        end
                        100: begin
                            wires[i].curr_in_init <= 18'h00063;
                            wires[i].prev_in_init <= 18'h00063;
                        end
                        101: begin
                            wires[i].curr_in_init <= 18'h00016;
                            wires[i].prev_in_init <= 18'h00016;
                        end
                        102: begin
                            wires[i].curr_in_init <= 18'h00024;
                            wires[i].prev_in_init <= 18'h00024;
                        end
                        103: begin
                            wires[i].curr_in_init <= 18'h000a3;
                            wires[i].prev_in_init <= 18'h000a3;
                        end
                        104: begin
                            wires[i].curr_in_init <= 18'h00258;
                            wires[i].prev_in_init <= 18'h00258;
                        end
                        105: begin
                            wires[i].curr_in_init <= 18'h0070a;
                            wires[i].prev_in_init <= 18'h0070a;
                        end
                        106: begin
                            wires[i].curr_in_init <= 18'h01152;
                            wires[i].prev_in_init <= 18'h01152;
                        end
                        107: begin
                            wires[i].curr_in_init <= 18'h022e2;
                            wires[i].prev_in_init <= 18'h022e2;
                        end
                        108: begin
                            wires[i].curr_in_init <= 18'h03983;
                            wires[i].prev_in_init <= 18'h03983;
                        end
                        109: begin
                            wires[i].curr_in_init <= 18'h04da2;
                            wires[i].prev_in_init <= 18'h04da2;
                        end
                        110: begin
                            wires[i].curr_in_init <= 18'h055cc;
                            wires[i].prev_in_init <= 18'h055cc;
                        end
                        111: begin
                            wires[i].curr_in_init <= 18'h04da2;
                            wires[i].prev_in_init <= 18'h04da2;
                        end
                        112: begin
                            wires[i].curr_in_init <= 18'h03983;
                            wires[i].prev_in_init <= 18'h03983;
                        end
                        113: begin
                            wires[i].curr_in_init <= 18'h022e2;
                            wires[i].prev_in_init <= 18'h022e2;
                        end
                        114: begin
                            wires[i].curr_in_init <= 18'h01152;
                            wires[i].prev_in_init <= 18'h01152;
                        end
                        115: begin
                            wires[i].curr_in_init <= 18'h0070a;
                            wires[i].prev_in_init <= 18'h0070a;
                        end
                        116: begin
                            wires[i].curr_in_init <= 18'h00258;
                            wires[i].prev_in_init <= 18'h00258;
                        end
                        117: begin
                            wires[i].curr_in_init <= 18'h000a3;
                            wires[i].prev_in_init <= 18'h000a3;
                        end
                        118: begin
                            wires[i].curr_in_init <= 18'h00024;
                            wires[i].prev_in_init <= 18'h00024;
                        end
                        119: begin
                            wires[i].curr_in_init <= 18'h00031;
                            wires[i].prev_in_init <= 18'h00031;
                        end
                        120: begin
                            wires[i].curr_in_init <= 18'h000dc;
                            wires[i].prev_in_init <= 18'h000dc;
                        end
                        121: begin
                            wires[i].curr_in_init <= 18'h0032a;
                            wires[i].prev_in_init <= 18'h0032a;
                        end
                        122: begin
                            wires[i].curr_in_init <= 18'h00981;
                            wires[i].prev_in_init <= 18'h00981;
                        end
                        123: begin
                            wires[i].curr_in_init <= 18'h01762;
                            wires[i].prev_in_init <= 18'h01762;
                        end
                        124: begin
                            wires[i].curr_in_init <= 18'h02f16;
                            wires[i].prev_in_init <= 18'h02f16;
                        end
                        125: begin
                            wires[i].curr_in_init <= 18'h04da2;
                            wires[i].prev_in_init <= 18'h04da2;
                        end
                        126: begin
                            wires[i].curr_in_init <= 18'h068cb;
                            wires[i].prev_in_init <= 18'h068cb;
                        end
                        127: begin
                            wires[i].curr_in_init <= 18'h073d1;
                            wires[i].prev_in_init <= 18'h073d1;
                        end
                        128: begin
                            wires[i].curr_in_init <= 18'h068cb;
                            wires[i].prev_in_init <= 18'h068cb;
                        end
                        129: begin
                            wires[i].curr_in_init <= 18'h04da2;
                            wires[i].prev_in_init <= 18'h04da2;
                        end
                        130: begin
                            wires[i].curr_in_init <= 18'h02f16;
                            wires[i].prev_in_init <= 18'h02f16;
                        end
                        131: begin
                            wires[i].curr_in_init <= 18'h01762;
                            wires[i].prev_in_init <= 18'h01762;
                        end
                        132: begin
                            wires[i].curr_in_init <= 18'h00981;
                            wires[i].prev_in_init <= 18'h00981;
                        end
                        133: begin
                            wires[i].curr_in_init <= 18'h0032a;
                            wires[i].prev_in_init <= 18'h0032a;
                        end
                        134: begin
                            wires[i].curr_in_init <= 18'h000dc;
                            wires[i].prev_in_init <= 18'h000dc;
                        end
                        135: begin
                            wires[i].curr_in_init <= 18'h00031;
                            wires[i].prev_in_init <= 18'h00031;
                        end
                        136: begin
                            wires[i].curr_in_init <= 18'h00036;
                            wires[i].prev_in_init <= 18'h00036;
                        end
                        137: begin
                            wires[i].curr_in_init <= 18'h000f4;
                            wires[i].prev_in_init <= 18'h000f4;
                        end
                        138: begin
                            wires[i].curr_in_init <= 18'h0037f;
                            wires[i].prev_in_init <= 18'h0037f;
                        end
                        139: begin
                            wires[i].curr_in_init <= 18'h00a81;
                            wires[i].prev_in_init <= 18'h00a81;
                        end
                        140: begin
                            wires[i].curr_in_init <= 18'h019d7;
                            wires[i].prev_in_init <= 18'h019d7;
                        end
                        141: begin
                            wires[i].curr_in_init <= 18'h0340a;
                            wires[i].prev_in_init <= 18'h0340a;
                        end
                        142: begin
                            wires[i].curr_in_init <= 18'h055cc;
                            wires[i].prev_in_init <= 18'h055cc;
                        end
                        143: begin
                            wires[i].curr_in_init <= 18'h073d1;
                            wires[i].prev_in_init <= 18'h073d1;
                        end
                        144: begin
                            wires[i].curr_in_init <= 18'h07fff;
                            wires[i].prev_in_init <= 18'h07fff;
                        end
                        145: begin
                            wires[i].curr_in_init <= 18'h073d1;
                            wires[i].prev_in_init <= 18'h073d1;
                        end
                        146: begin
                            wires[i].curr_in_init <= 18'h055cc;
                            wires[i].prev_in_init <= 18'h055cc;
                        end
                        147: begin
                            wires[i].curr_in_init <= 18'h0340a;
                            wires[i].prev_in_init <= 18'h0340a;
                        end
                        148: begin
                            wires[i].curr_in_init <= 18'h019d7;
                            wires[i].prev_in_init <= 18'h019d7;
                        end
                        149: begin
                            wires[i].curr_in_init <= 18'h00a81;
                            wires[i].prev_in_init <= 18'h00a81;
                        end
                        150: begin
                            wires[i].curr_in_init <= 18'h0037f;
                            wires[i].prev_in_init <= 18'h0037f;
                        end
                        151: begin
                            wires[i].curr_in_init <= 18'h000f4;
                            wires[i].prev_in_init <= 18'h000f4;
                        end
                        152: begin
                            wires[i].curr_in_init <= 18'h00036;
                            wires[i].prev_in_init <= 18'h00036;
                        end
                        153: begin
                            wires[i].curr_in_init <= 18'h00031;
                            wires[i].prev_in_init <= 18'h00031;
                        end
                        154: begin
                            wires[i].curr_in_init <= 18'h000dc;
                            wires[i].prev_in_init <= 18'h000dc;
                        end
                        155: begin
                            wires[i].curr_in_init <= 18'h0032a;
                            wires[i].prev_in_init <= 18'h0032a;
                        end
                        156: begin
                            wires[i].curr_in_init <= 18'h00981;
                            wires[i].prev_in_init <= 18'h00981;
                        end
                        157: begin
                            wires[i].curr_in_init <= 18'h01762;
                            wires[i].prev_in_init <= 18'h01762;
                        end
                        158: begin
                            wires[i].curr_in_init <= 18'h02f16;
                            wires[i].prev_in_init <= 18'h02f16;
                        end
                        159: begin
                            wires[i].curr_in_init <= 18'h04da2;
                            wires[i].prev_in_init <= 18'h04da2;
                        end
                        160: begin
                            wires[i].curr_in_init <= 18'h068cb;
                            wires[i].prev_in_init <= 18'h068cb;
                        end
                        161: begin
                            wires[i].curr_in_init <= 18'h073d1;
                            wires[i].prev_in_init <= 18'h073d1;
                        end
                        162: begin
                            wires[i].curr_in_init <= 18'h068cb;
                            wires[i].prev_in_init <= 18'h068cb;
                        end
                        163: begin
                            wires[i].curr_in_init <= 18'h04da2;
                            wires[i].prev_in_init <= 18'h04da2;
                        end
                        164: begin
                            wires[i].curr_in_init <= 18'h02f16;
                            wires[i].prev_in_init <= 18'h02f16;
                        end
                        165: begin
                            wires[i].curr_in_init <= 18'h01762;
                            wires[i].prev_in_init <= 18'h01762;
                        end
                        166: begin
                            wires[i].curr_in_init <= 18'h00981;
                            wires[i].prev_in_init <= 18'h00981;
                        end
                        167: begin
                            wires[i].curr_in_init <= 18'h0032a;
                            wires[i].prev_in_init <= 18'h0032a;
                        end
                        168: begin
                            wires[i].curr_in_init <= 18'h000dc;
                            wires[i].prev_in_init <= 18'h000dc;
                        end
                        169: begin
                            wires[i].curr_in_init <= 18'h00031;
                            wires[i].prev_in_init <= 18'h00031;
                        end
                        170: begin
                            wires[i].curr_in_init <= 18'h00024;
                            wires[i].prev_in_init <= 18'h00024;
                        end
                        171: begin
                            wires[i].curr_in_init <= 18'h000a3;
                            wires[i].prev_in_init <= 18'h000a3;
                        end
                        172: begin
                            wires[i].curr_in_init <= 18'h00258;
                            wires[i].prev_in_init <= 18'h00258;
                        end
                        173: begin
                            wires[i].curr_in_init <= 18'h0070a;
                            wires[i].prev_in_init <= 18'h0070a;
                        end
                        174: begin
                            wires[i].curr_in_init <= 18'h01152;
                            wires[i].prev_in_init <= 18'h01152;
                        end
                        175: begin
                            wires[i].curr_in_init <= 18'h022e2;
                            wires[i].prev_in_init <= 18'h022e2;
                        end
                        176: begin
                            wires[i].curr_in_init <= 18'h03983;
                            wires[i].prev_in_init <= 18'h03983;
                        end
                        177: begin
                            wires[i].curr_in_init <= 18'h04da2;
                            wires[i].prev_in_init <= 18'h04da2;
                        end
                        178: begin
                            wires[i].curr_in_init <= 18'h055cc;
                            wires[i].prev_in_init <= 18'h055cc;
                        end
                        179: begin
                            wires[i].curr_in_init <= 18'h04da2;
                            wires[i].prev_in_init <= 18'h04da2;
                        end
                        180: begin
                            wires[i].curr_in_init <= 18'h03983;
                            wires[i].prev_in_init <= 18'h03983;
                        end
                        181: begin
                            wires[i].curr_in_init <= 18'h022e2;
                            wires[i].prev_in_init <= 18'h022e2;
                        end
                        182: begin
                            wires[i].curr_in_init <= 18'h01152;
                            wires[i].prev_in_init <= 18'h01152;
                        end
                        183: begin
                            wires[i].curr_in_init <= 18'h0070a;
                            wires[i].prev_in_init <= 18'h0070a;
                        end
                        184: begin
                            wires[i].curr_in_init <= 18'h00258;
                            wires[i].prev_in_init <= 18'h00258;
                        end
                        185: begin
                            wires[i].curr_in_init <= 18'h000a3;
                            wires[i].prev_in_init <= 18'h000a3;
                        end
                        186: begin
                            wires[i].curr_in_init <= 18'h00024;
                            wires[i].prev_in_init <= 18'h00024;
                        end
                        187: begin
                            wires[i].curr_in_init <= 18'h00016;
                            wires[i].prev_in_init <= 18'h00016;
                        end
                        188: begin
                            wires[i].curr_in_init <= 18'h00063;
                            wires[i].prev_in_init <= 18'h00063;
                        end
                        189: begin
                            wires[i].curr_in_init <= 18'h0016c;
                            wires[i].prev_in_init <= 18'h0016c;
                        end
                        190: begin
                            wires[i].curr_in_init <= 18'h00445;
                            wires[i].prev_in_init <= 18'h00445;
                        end
                        191: begin
                            wires[i].curr_in_init <= 18'h00a81;
                            wires[i].prev_in_init <= 18'h00a81;
                        end
                        192: begin
                            wires[i].curr_in_init <= 18'h01528;
                            wires[i].prev_in_init <= 18'h01528;
                        end
                        193: begin
                            wires[i].curr_in_init <= 18'h022e2;
                            wires[i].prev_in_init <= 18'h022e2;
                        end
                        194: begin
                            wires[i].curr_in_init <= 18'h02f16;
                            wires[i].prev_in_init <= 18'h02f16;
                        end
                        195: begin
                            wires[i].curr_in_init <= 18'h0340a;
                            wires[i].prev_in_init <= 18'h0340a;
                        end
                        196: begin
                            wires[i].curr_in_init <= 18'h02f16;
                            wires[i].prev_in_init <= 18'h02f16;
                        end
                        197: begin
                            wires[i].curr_in_init <= 18'h022e2;
                            wires[i].prev_in_init <= 18'h022e2;
                        end
                        198: begin
                            wires[i].curr_in_init <= 18'h01528;
                            wires[i].prev_in_init <= 18'h01528;
                        end
                        199: begin
                            wires[i].curr_in_init <= 18'h00a81;
                            wires[i].prev_in_init <= 18'h00a81;
                        end
                        200: begin
                            wires[i].curr_in_init <= 18'h00445;
                            wires[i].prev_in_init <= 18'h00445;
                        end
                        201: begin
                            wires[i].curr_in_init <= 18'h0016c;
                            wires[i].prev_in_init <= 18'h0016c;
                        end
                        202: begin
                            wires[i].curr_in_init <= 18'h00063;
                            wires[i].prev_in_init <= 18'h00063;
                        end
                        203: begin
                            wires[i].curr_in_init <= 18'h00016;
                            wires[i].prev_in_init <= 18'h00016;
                        end
                        204: begin
                            wires[i].curr_in_init <= 18'h0000a;
                            wires[i].prev_in_init <= 18'h0000a;
                        end
                        205: begin
                            wires[i].curr_in_init <= 18'h00031;
                            wires[i].prev_in_init <= 18'h00031;
                        end
                        206: begin
                            wires[i].curr_in_init <= 18'h000b4;
                            wires[i].prev_in_init <= 18'h000b4;
                        end
                        207: begin
                            wires[i].curr_in_init <= 18'h0021f;
                            wires[i].prev_in_init <= 18'h0021f;
                        end
                        208: begin
                            wires[i].curr_in_init <= 18'h00537;
                            wires[i].prev_in_init <= 18'h00537;
                        end
                        209: begin
                            wires[i].curr_in_init <= 18'h00a81;
                            wires[i].prev_in_init <= 18'h00a81;
                        end
                        210: begin
                            wires[i].curr_in_init <= 18'h01152;
                            wires[i].prev_in_init <= 18'h01152;
                        end
                        211: begin
                            wires[i].curr_in_init <= 18'h01762;
                            wires[i].prev_in_init <= 18'h01762;
                        end
                        212: begin
                            wires[i].curr_in_init <= 18'h019d7;
                            wires[i].prev_in_init <= 18'h019d7;
                        end
                        213: begin
                            wires[i].curr_in_init <= 18'h01762;
                            wires[i].prev_in_init <= 18'h01762;
                        end
                        214: begin
                            wires[i].curr_in_init <= 18'h01152;
                            wires[i].prev_in_init <= 18'h01152;
                        end
                        215: begin
                            wires[i].curr_in_init <= 18'h00a81;
                            wires[i].prev_in_init <= 18'h00a81;
                        end
                        216: begin
                            wires[i].curr_in_init <= 18'h00537;
                            wires[i].prev_in_init <= 18'h00537;
                        end
                        217: begin
                            wires[i].curr_in_init <= 18'h0021f;
                            wires[i].prev_in_init <= 18'h0021f;
                        end
                        218: begin
                            wires[i].curr_in_init <= 18'h000b4;
                            wires[i].prev_in_init <= 18'h000b4;
                        end
                        219: begin
                            wires[i].curr_in_init <= 18'h00031;
                            wires[i].prev_in_init <= 18'h00031;
                        end
                        220: begin
                            wires[i].curr_in_init <= 18'h0000a;
                            wires[i].prev_in_init <= 18'h0000a;
                        end
                        221: begin
                            wires[i].curr_in_init <= 18'h00004;
                            wires[i].prev_in_init <= 18'h00004;
                        end
                        222: begin
                            wires[i].curr_in_init <= 18'h00014;
                            wires[i].prev_in_init <= 18'h00014;
                        end
                        223: begin
                            wires[i].curr_in_init <= 18'h00049;
                            wires[i].prev_in_init <= 18'h00049;
                        end
                        224: begin
                            wires[i].curr_in_init <= 18'h000dc;
                            wires[i].prev_in_init <= 18'h000dc;
                        end
                        225: begin
                            wires[i].curr_in_init <= 18'h0021f;
                            wires[i].prev_in_init <= 18'h0021f;
                        end
                        226: begin
                            wires[i].curr_in_init <= 18'h00445;
                            wires[i].prev_in_init <= 18'h00445;
                        end
                        227: begin
                            wires[i].curr_in_init <= 18'h0070a;
                            wires[i].prev_in_init <= 18'h0070a;
                        end
                        228: begin
                            wires[i].curr_in_init <= 18'h00981;
                            wires[i].prev_in_init <= 18'h00981;
                        end
                        229: begin
                            wires[i].curr_in_init <= 18'h00a81;
                            wires[i].prev_in_init <= 18'h00a81;
                        end
                        230: begin
                            wires[i].curr_in_init <= 18'h00981;
                            wires[i].prev_in_init <= 18'h00981;
                        end
                        231: begin
                            wires[i].curr_in_init <= 18'h0070a;
                            wires[i].prev_in_init <= 18'h0070a;
                        end
                        232: begin
                            wires[i].curr_in_init <= 18'h00445;
                            wires[i].prev_in_init <= 18'h00445;
                        end
                        233: begin
                            wires[i].curr_in_init <= 18'h0021f;
                            wires[i].prev_in_init <= 18'h0021f;
                        end
                        234: begin
                            wires[i].curr_in_init <= 18'h000dc;
                            wires[i].prev_in_init <= 18'h000dc;
                        end
                        235: begin
                            wires[i].curr_in_init <= 18'h00049;
                            wires[i].prev_in_init <= 18'h00049;
                        end
                        236: begin
                            wires[i].curr_in_init <= 18'h00014;
                            wires[i].prev_in_init <= 18'h00014;
                        end
                        237: begin
                            wires[i].curr_in_init <= 18'h00004;
                            wires[i].prev_in_init <= 18'h00004;
                        end
                        238: begin
                            wires[i].curr_in_init <= 18'h00001;
                            wires[i].prev_in_init <= 18'h00001;
                        end
                        239: begin
                            wires[i].curr_in_init <= 18'h00006;
                            wires[i].prev_in_init <= 18'h00006;
                        end
                        240: begin
                            wires[i].curr_in_init <= 18'h00018;
                            wires[i].prev_in_init <= 18'h00018;
                        end
                        241: begin
                            wires[i].curr_in_init <= 18'h00049;
                            wires[i].prev_in_init <= 18'h00049;
                        end
                        242: begin
                            wires[i].curr_in_init <= 18'h000b4;
                            wires[i].prev_in_init <= 18'h000b4;
                        end
                        243: begin
                            wires[i].curr_in_init <= 18'h0016c;
                            wires[i].prev_in_init <= 18'h0016c;
                        end
                        244: begin
                            wires[i].curr_in_init <= 18'h00258;
                            wires[i].prev_in_init <= 18'h00258;
                        end
                        245: begin
                            wires[i].curr_in_init <= 18'h0032a;
                            wires[i].prev_in_init <= 18'h0032a;
                        end
                        246: begin
                            wires[i].curr_in_init <= 18'h0037f;
                            wires[i].prev_in_init <= 18'h0037f;
                        end
                        247: begin
                            wires[i].curr_in_init <= 18'h0032a;
                            wires[i].prev_in_init <= 18'h0032a;
                        end
                        248: begin
                            wires[i].curr_in_init <= 18'h00258;
                            wires[i].prev_in_init <= 18'h00258;
                        end
                        249: begin
                            wires[i].curr_in_init <= 18'h0016c;
                            wires[i].prev_in_init <= 18'h0016c;
                        end
                        250: begin
                            wires[i].curr_in_init <= 18'h000b4;
                            wires[i].prev_in_init <= 18'h000b4;
                        end
                        251: begin
                            wires[i].curr_in_init <= 18'h00049;
                            wires[i].prev_in_init <= 18'h00049;
                        end
                        252: begin
                            wires[i].curr_in_init <= 18'h00018;
                            wires[i].prev_in_init <= 18'h00018;
                        end
                        253: begin
                            wires[i].curr_in_init <= 18'h00006;
                            wires[i].prev_in_init <= 18'h00006;
                        end
                        254: begin
                            wires[i].curr_in_init <= 18'h00001;
                            wires[i].prev_in_init <= 18'h00001;
                        end
                        255: begin
                            wires[i].curr_in_init <= 18'h00000;
                            wires[i].prev_in_init <= 18'h00000;
                        end
                        256: begin
                            wires[i].curr_in_init <= 18'h00001;
                            wires[i].prev_in_init <= 18'h00001;
                        end
                        257: begin
                            wires[i].curr_in_init <= 18'h00006;
                            wires[i].prev_in_init <= 18'h00006;
                        end
                        258: begin
                            wires[i].curr_in_init <= 18'h00014;
                            wires[i].prev_in_init <= 18'h00014;
                        end
                        259: begin
                            wires[i].curr_in_init <= 18'h00031;
                            wires[i].prev_in_init <= 18'h00031;
                        end
                        260: begin
                            wires[i].curr_in_init <= 18'h00063;
                            wires[i].prev_in_init <= 18'h00063;
                        end
                        261: begin
                            wires[i].curr_in_init <= 18'h000a3;
                            wires[i].prev_in_init <= 18'h000a3;
                        end
                        262: begin
                            wires[i].curr_in_init <= 18'h000dc;
                            wires[i].prev_in_init <= 18'h000dc;
                        end
                        263: begin
                            wires[i].curr_in_init <= 18'h000f4;
                            wires[i].prev_in_init <= 18'h000f4;
                        end
                        264: begin
                            wires[i].curr_in_init <= 18'h000dc;
                            wires[i].prev_in_init <= 18'h000dc;
                        end
                        265: begin
                            wires[i].curr_in_init <= 18'h000a3;
                            wires[i].prev_in_init <= 18'h000a3;
                        end
                        266: begin
                            wires[i].curr_in_init <= 18'h00063;
                            wires[i].prev_in_init <= 18'h00063;
                        end
                        267: begin
                            wires[i].curr_in_init <= 18'h00031;
                            wires[i].prev_in_init <= 18'h00031;
                        end
                        268: begin
                            wires[i].curr_in_init <= 18'h00014;
                            wires[i].prev_in_init <= 18'h00014;
                        end
                        269: begin
                            wires[i].curr_in_init <= 18'h00006;
                            wires[i].prev_in_init <= 18'h00006;
                        end
                        270: begin
                            wires[i].curr_in_init <= 18'h00001;
                            wires[i].prev_in_init <= 18'h00001;
                        end
                        271: begin
                            wires[i].curr_in_init <= 18'h00000;
                            wires[i].prev_in_init <= 18'h00000;
                        end
                        272: begin
                            wires[i].curr_in_init <= 18'h00000;
                            wires[i].prev_in_init <= 18'h00000;
                        end
                        273: begin
                            wires[i].curr_in_init <= 18'h00000;
                            wires[i].prev_in_init <= 18'h00000;
                        end
                        274: begin
                            wires[i].curr_in_init <= 18'h00001;
                            wires[i].prev_in_init <= 18'h00001;
                        end
                        275: begin
                            wires[i].curr_in_init <= 18'h00004;
                            wires[i].prev_in_init <= 18'h00004;
                        end
                        276: begin
                            wires[i].curr_in_init <= 18'h0000a;
                            wires[i].prev_in_init <= 18'h0000a;
                        end
                        277: begin
                            wires[i].curr_in_init <= 18'h00016;
                            wires[i].prev_in_init <= 18'h00016;
                        end
                        278: begin
                            wires[i].curr_in_init <= 18'h00024;
                            wires[i].prev_in_init <= 18'h00024;
                        end
                        279: begin
                            wires[i].curr_in_init <= 18'h00031;
                            wires[i].prev_in_init <= 18'h00031;
                        end
                        280: begin
                            wires[i].curr_in_init <= 18'h00036;
                            wires[i].prev_in_init <= 18'h00036;
                        end
                        281: begin
                            wires[i].curr_in_init <= 18'h00031;
                            wires[i].prev_in_init <= 18'h00031;
                        end
                        282: begin
                            wires[i].curr_in_init <= 18'h00024;
                            wires[i].prev_in_init <= 18'h00024;
                        end
                        283: begin
                            wires[i].curr_in_init <= 18'h00016;
                            wires[i].prev_in_init <= 18'h00016;
                        end
                        284: begin
                            wires[i].curr_in_init <= 18'h0000a;
                            wires[i].prev_in_init <= 18'h0000a;
                        end
                        285: begin
                            wires[i].curr_in_init <= 18'h00004;
                            wires[i].prev_in_init <= 18'h00004;
                        end
                        286: begin
                            wires[i].curr_in_init <= 18'h00001;
                            wires[i].prev_in_init <= 18'h00001;
                        end
                        287: begin
                            wires[i].curr_in_init <= 18'h00000;
                            wires[i].prev_in_init <= 18'h00000;
                        end
                        288: begin
                            wires[i].curr_in_init <= 18'h00000;
                            wires[i].prev_in_init <= 18'h00000;
                        end
                        default: begin
                            wires[i].curr_in_init <= 18'h00000;
                            wires[i].prev_in_init <= 18'h00000;
                        end
                    endcase
                end //else
            end //always
        end //for
    endgenerate
endmodule

//each column module uses a single multiplier to sequentially calculate updates for the entire column
//the module contains 2 M10K blocks, one storing current values and one storing the values at the previous time step
//the state machine coordinates the movement of data between the memory blocks, several registers, and neighboring columns
module column(
    input CLOCK_50, reset, start,
    input [8:0] curr_wradd_init, prev_wradd_init,
    input [17:0] curr_in_init, prev_in_init,
    input signed [17:0] iminus, iplus, rho,
    input [4:0] etadt,
    output signed [17:0] jplus_out, sound,
    input [8:0] column_size,
);

    reg [3:0] state;
    reg [8:0] row;

    //inputs and outputs of M10K blocks
    wire [17:0] curr_out, prev_out;
    reg [17:0] curr_in, prev_in;
    reg [8:0] curr_wradd, curr_rdadd, prev_wradd, prev_rdadd;
    reg curr_wren, curr_rden, prev_wren, prev_rden;

    //inputs and output of solver module
    reg [17:0] jminus, pos;
    wire[17:0] solv_out, jplus;
    //jplus gets the value of the node in the positive j direction, except it is assigned to 0 at the top edge of the drum
    assign jplus = (state == 4'd9) ? 18'd0 : curr_out;
    //the output of the current position, used by neighboring nodes as iminus or iplus
    assign jplus_out = pos;

    //sound = value at the middle node when we reach the middle row, otherwise its value does not change during other rows
    reg[17:0] mid_node;
    assign sound = mid_node;
    always @ (posedge CLOCK_50) begin
        if (reset) begin
            if (row == (column_size+1)/2)
                mid_node <= curr_in;
            else
                mid_node <= mid_node;
        end
        else begin
            mid_node <= 0;
        end
    end

    always @ (posedge CLOCK_50) begin
        if (reset==0) begin
            state <= 0;
            row <= 0;
            curr_rdadd <= 0;
            prev_rdadd <= 0;
            curr_rden <= 0;
            prev_rden <= 0;
            // continuously load initial values into m10k while reset low
            curr_wren <= 1;
            prev_wren <= 1;
            curr_wradd <= curr_wradd_init;
            prev_wradd <= prev_wradd_init;
            curr_in <= curr_in_init;
            prev_in <= prev_in_init;

        end
        // stop writing initial values when reset is released
        if (state==4'd0 && reset==1) begin
            state <= 4'd1;
            row <= 9'd0;
            curr_wren <= 0;
            prev_wren <= 0;
            curr_wradd <= 9'd0;
            prev_wradd <= 9'd0;
        end

        //wait in state 1 for start signal from the top level module
        if (state==4'd1 && start==0 && reset==1) begin
            state <= 4'd1;
            curr_wren <= 0;
            prev_wren <= 0;
        end
        //states 1-4 are building up the pipeline, beginning with longer latency read requests and then moving and writing values
        if (state==4'd1 && start==1 && reset==1) begin
            state <= 4'd2;
            curr_wren <= 0;
            prev_wren <= 0;
            curr_rdadd <= 9'd0;
            curr_rden <= 1;
        end
        if (state==4'd2 && reset==1) begin
            state <= 4'd3;
            curr_wren <= 0;
            prev_wren <= 0;
            curr_rdadd <= 9'd1;
            prev_rdadd <= 9'd0;
            prev_rden <= 1;
        end
        if (state==4'd3 && reset==1) begin
            state <= 4'd4;
            curr_rdadd <= 9'd2;
            prev_rdadd <= 9'd1;
        end
        if (state==4'd4 && reset==1) begin
            state <= 4'd5;
            curr_rdadd <= 9'd3;
            prev_rdadd <= 9'd2;
            pos <= jplus;
            jminus <= 18'd0;
        end
        //state 5 is when the pipeline is completely full, and we remain here until we near the top edge
        if (state==4'd5 && reset==1) begin
            if (row < column_size-4)
                state <= 4'd5;
            else
                state <= 4'd6;
            curr_rdadd <= row+9'd4;
            prev_rdadd <= row+9'd3;
            jminus <= pos;
            pos <= jplus;
            curr_wradd <= row;
            prev_wradd <= row;
            curr_wren <= 1;
            prev_wren <= 1;
            curr_in <= solv_out;
            prev_in <= pos;
            row <= row+9'd1;
        end
        //state 6-9 empty the pipeline and then we return to state 1 to wait for the next start signal
        if (state==4'd6 && reset==1) begin
            state <= 4'd7;
            curr_rdadd <= 9'd0;
            curr_rden <= 0;
            prev_rdadd <= row+9'd3;
            jminus <= pos;
            pos <= jplus;
            curr_wradd <= row;
            prev_wradd <= row;
            curr_in <= solv_out;
            prev_in <= pos;
            row <= row+9'd1;
        end
        if (state==4'd7 && reset==1) begin //row = column_size-3 at start of state
            state <= 4'd8;
            prev_rdadd <= 9'd0;
            prev_rden <= 0;
            jminus <= pos;
            pos <= jplus;
            curr_wradd <= row;
            prev_wradd <= row;
            curr_in <= solv_out;
            prev_in <= pos;
            row <= row+9'd1;
        end
        if (state==4'd8 && reset==1) begin //row = column_size-2 at start of state
            state <= 4'd9;
            jminus <= pos;
            pos <= 18'd0;
            curr_wradd <= row;
            prev_wradd <= row;
            curr_in <= solv_out;
            prev_in <= pos;
            row <= row+9'd1;
        end
        if (state==4'd9 && reset==1) begin //row = last row at start of state
            state <= 4'd1;
            curr_wradd <= row;
            prev_wradd <= row;
            curr_in <= solv_out;
            prev_in <= pos;
            row <= 9'd0;
        end


    end

    IPM10K curr(.q(curr_out),
                 .data(curr_in),
                 .wraddress(curr_wradd),
                 .rdaddress(curr_rdadd),
                 .wren(curr_wren),
                 .rden(curr_rden),
                 .clock(CLOCK_50));

    IPM10K prev(.q(prev_out),
                 .data(prev_in),
                 .wraddress(prev_wradd),
                 .rdaddress(prev_rdadd),
                 .wren(prev_wren),
                 .rden(prev_rden),
                 .clock(CLOCK_50));

    solver s(.iminus(iminus),
                .iplus(iplus),
                .jminus(jminus),
                .jplus(jplus),
                .pos(pos),
                .posOld(prev_out),
                .rho(rho),
                .etadt(etadt),
                .out(solv_out));
endmodule

//there is one solver module contained inside each column module
//the column feeds the solver inputs according to its state machine, and the solver combinationally finds the output
module solver(
    input signed[17:0] iminus, iplus, jminus, jplus, pos, posOld, rho,
    input [4:0] etadt,
    output signed[17:0] out);

//=======================================================
//  REG/WIRE declarations
//=======================================================

    wire signed [17:0] tempim, tempip, tempjm, tempjp, tempsum,
               temprho, tempold, tempbig;

//=======================================================
//  Structural coding
//=======================================================

    //we split up the overall calculation into chunks to minimize the chances of overflow occurring
    assign tempim = iminus - pos;
    assign tempip = iplus - pos;
    assign tempjm = jminus - pos;
    assign tempjp = jplus - pos;
    assign tempsum = tempim + tempip + tempjm + tempjp;
    signed_mult rhoMult(temprho, tempsum, rho);
    assign tempold = pos - posOld + (posOld >>> etadt);
    assign tempbig = temprho + pos + tempold;
    assign out = tempbig - (tempbig >>> etadt);

endmodule

// the 1.17 signed fixed point multiplier
module signed_mult (out, a, b);
    output      [17:0]  out;
    input   signed  [17:0]  a;
    input   signed  [17:0]  b;

    wire    signed  [17:0]  out;
    wire    signed  [35:0]  mult_out;

    assign mult_out = a * b;
    assign out = {mult_out[35], mult_out[33:17]};

endmodule

//////////////////////////////////////////////////