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DDR Memory Calibration - Micron Memory - Board 2

Kulunu
Aug 9th, 2018
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  1.  
  2. ============================================
  3. DDR Stress Test (2.6.0)
  4. Build: Aug 1 2017, 17:33:25
  5. NXP Semiconductors.
  6. ============================================
  7.  
  8. ============================================
  9. Chip ID
  10. CHIP ID = i.MX6 Dual/Quad (0x63)
  11. Internal Revision = TO1.2
  12. ============================================
  13.  
  14. ============================================
  15. Boot Configuration
  16. SRC_SBMR1(0x020d8004) = 0x18000030
  17. SRC_SBMR2(0x020d801c) = 0x21000011
  18. ============================================
  19.  
  20. ARM Clock set to 1GHz
  21.  
  22. ============================================
  23. DDR configuration
  24. BOOT_CFG3[5-4]: 0x00, Single DDR channel.
  25. DDR type is DDR3
  26. Data width: 64, bank num: 8
  27. Row size: 15, col size: 10
  28. Chip select CSD0 is used
  29. Density per chip select: 2048MB
  30. ============================================
  31.  
  32. Current Temperature: 29
  33. ============================================
  34.  
  35. DDR Freq: 396 MHz
  36.  
  37. ddr_mr1=0x00000004
  38. Start write leveling calibration...
  39. running Write level HW calibration
  40. Write leveling calibration completed, update the following registers in your initialization script
  41. MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x0013001B
  42. MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x001F0011
  43. MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x000D0017
  44. MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x0013001D
  45. Write DQS delay result:
  46. Write DQS0 delay: 27/256 CK
  47. Write DQS1 delay: 19/256 CK
  48. Write DQS2 delay: 17/256 CK
  49. Write DQS3 delay: 31/256 CK
  50. Write DQS4 delay: 23/256 CK
  51. Write DQS5 delay: 13/256 CK
  52. Write DQS6 delay: 29/256 CK
  53. Write DQS7 delay: 19/256 CK
  54.  
  55. Starting DQS gating calibration
  56. . HC_DEL=0x00000000 result[00]=0x11111111
  57. . HC_DEL=0x00000001 result[01]=0x11111011
  58. . HC_DEL=0x00000002 result[02]=0x00000000
  59. . HC_DEL=0x00000003 result[03]=0x00000000
  60. . HC_DEL=0x00000004 result[04]=0x11111111
  61. . HC_DEL=0x00000005 result[05]=0x11111111
  62. . HC_DEL=0x00000006 result[06]=0x11111111
  63. . HC_DEL=0x00000007 result[07]=0x11111111
  64. . HC_DEL=0x00000008 result[08]=0x11111111
  65. . HC_DEL=0x00000009 result[09]=0x11111111
  66. . HC_DEL=0x0000000A result[0A]=0x11111111
  67. . HC_DEL=0x0000000B result[0B]=0x11111111
  68. . HC_DEL=0x0000000C result[0C]=0x11111111
  69. . HC_DEL=0x0000000D result[0D]=0x11111111
  70. DQS HC delay value low1 = 0x02010202, high1=0x03030303
  71. DQS HC delay value low2 = 0x02020202, high2=0x03030303
  72.  
  73. loop ABS offset to get HW_DG_LOW
  74. . ABS_OFFSET=0x00000000 result[00]=0x11111011
  75. . ABS_OFFSET=0x00000004 result[01]=0x10111111
  76. . ABS_OFFSET=0x00000008 result[02]=0x10111111
  77. . ABS_OFFSET=0x0000000C result[03]=0x10111111
  78. . ABS_OFFSET=0x00000010 result[04]=0x10111011
  79. . ABS_OFFSET=0x00000014 result[05]=0x10111011
  80. . ABS_OFFSET=0x00000018 result[06]=0x10110011
  81. . ABS_OFFSET=0x0000001C result[07]=0x00110011
  82. . ABS_OFFSET=0x00000020 result[08]=0x00110011
  83. . ABS_OFFSET=0x00000024 result[09]=0x00110011
  84. . ABS_OFFSET=0x00000028 result[0A]=0x00110011
  85. . ABS_OFFSET=0x0000002C result[0B]=0x00110001
  86. . ABS_OFFSET=0x00000030 result[0C]=0x00010000
  87. . ABS_OFFSET=0x00000034 result[0D]=0x00000000
  88. . ABS_OFFSET=0x00000038 result[0E]=0x00000000
  89. . ABS_OFFSET=0x0000003C result[0F]=0x00000000
  90. . ABS_OFFSET=0x00000040 result[10]=0x00000000
  91. . ABS_OFFSET=0x00000044 result[11]=0x00000000
  92. . ABS_OFFSET=0x00000048 result[12]=0x00000000
  93. . ABS_OFFSET=0x0000004C result[13]=0x00000000
  94. . ABS_OFFSET=0x00000050 result[14]=0x00000000
  95. . ABS_OFFSET=0x00000054 result[15]=0x00000000
  96. . ABS_OFFSET=0x00000058 result[16]=0x00000000
  97. . ABS_OFFSET=0x0000005C result[17]=0x00000000
  98. . ABS_OFFSET=0x00000060 result[18]=0x00000000
  99. . ABS_OFFSET=0x00000064 result[19]=0x00000000
  100. . ABS_OFFSET=0x00000068 result[1A]=0x00000000
  101. . ABS_OFFSET=0x0000006C result[1B]=0x00000000
  102. . ABS_OFFSET=0x00000070 result[1C]=0x00000000
  103. . ABS_OFFSET=0x00000074 result[1D]=0x00000000
  104. . ABS_OFFSET=0x00000078 result[1E]=0x00000000
  105. . ABS_OFFSET=0x0000007C result[1F]=0x00000000
  106.  
  107. loop ABS offset to get HW_DG_HIGH
  108. . ABS_OFFSET=0x00000000 result[00]=0x00000000
  109. . ABS_OFFSET=0x00000004 result[01]=0x00000000
  110. . ABS_OFFSET=0x00000008 result[02]=0x00000000
  111. . ABS_OFFSET=0x0000000C result[03]=0x00000000
  112. . ABS_OFFSET=0x00000010 result[04]=0x00000000
  113. . ABS_OFFSET=0x00000014 result[05]=0x00000000
  114. . ABS_OFFSET=0x00000018 result[06]=0x00000000
  115. . ABS_OFFSET=0x0000001C result[07]=0x00000000
  116. . ABS_OFFSET=0x00000020 result[08]=0x00000000
  117. . ABS_OFFSET=0x00000024 result[09]=0x00000000
  118. . ABS_OFFSET=0x00000028 result[0A]=0x00000000
  119. . ABS_OFFSET=0x0000002C result[0B]=0x01000000
  120. . ABS_OFFSET=0x00000030 result[0C]=0x01000000
  121. . ABS_OFFSET=0x00000034 result[0D]=0x01000000
  122. . ABS_OFFSET=0x00000038 result[0E]=0x01000000
  123. . ABS_OFFSET=0x0000003C result[0F]=0x01000000
  124. . ABS_OFFSET=0x00000040 result[10]=0x01000000
  125. . ABS_OFFSET=0x00000044 result[11]=0x01000000
  126. . ABS_OFFSET=0x00000048 result[12]=0x01000000
  127. . ABS_OFFSET=0x0000004C result[13]=0x01001100
  128. . ABS_OFFSET=0x00000050 result[14]=0x11001100
  129. . ABS_OFFSET=0x00000054 result[15]=0x11101110
  130. . ABS_OFFSET=0x00000058 result[16]=0x11101110
  131. . ABS_OFFSET=0x0000005C result[17]=0x11101111
  132. . ABS_OFFSET=0x00000060 result[18]=0x11101111
  133. . ABS_OFFSET=0x00000064 result[19]=0x11111111
  134. . ABS_OFFSET=0x00000068 result[1A]=0x11111111
  135. . ABS_OFFSET=0x0000006C result[1B]=0x11111111
  136. . ABS_OFFSET=0x00000070 result[1C]=0x11111111
  137. . ABS_OFFSET=0x00000074 result[1D]=0x11111111
  138. . ABS_OFFSET=0x00000078 result[1E]=0x11111111
  139. . ABS_OFFSET=0x0000007C result[1F]=0x11111111
  140.  
  141.  
  142. BYTE 0:
  143. Start: HC=0x01 ABS=0x30
  144. End: HC=0x03 ABS=0x58
  145. Mean: HC=0x02 ABS=0x44
  146. End-0.5*tCK: HC=0x02 ABS=0x58
  147. Final: HC=0x02 ABS=0x58
  148. BYTE 1:
  149. Start: HC=0x01 ABS=0x2C
  150. End: HC=0x03 ABS=0x50
  151. Mean: HC=0x02 ABS=0x3E
  152. End-0.5*tCK: HC=0x02 ABS=0x50
  153. Final: HC=0x02 ABS=0x50
  154. BYTE 2:
  155. Start: HC=0x00 ABS=0x10
  156. End: HC=0x03 ABS=0x48
  157. Mean: HC=0x01 ABS=0x6B
  158. End-0.5*tCK: HC=0x02 ABS=0x48
  159. Final: HC=0x02 ABS=0x48
  160. BYTE 3:
  161. Start: HC=0x01 ABS=0x18
  162. End: HC=0x03 ABS=0x48
  163. Mean: HC=0x02 ABS=0x30
  164. End-0.5*tCK: HC=0x02 ABS=0x48
  165. Final: HC=0x02 ABS=0x48
  166. BYTE 4:
  167. Start: HC=0x01 ABS=0x34
  168. End: HC=0x03 ABS=0x60
  169. Mean: HC=0x02 ABS=0x4A
  170. End-0.5*tCK: HC=0x02 ABS=0x60
  171. Final: HC=0x02 ABS=0x60
  172. BYTE 5:
  173. Start: HC=0x01 ABS=0x30
  174. End: HC=0x03 ABS=0x50
  175. Mean: HC=0x02 ABS=0x40
  176. End-0.5*tCK: HC=0x02 ABS=0x50
  177. Final: HC=0x02 ABS=0x50
  178. BYTE 6:
  179. Start: HC=0x01 ABS=0x04
  180. End: HC=0x03 ABS=0x28
  181. Mean: HC=0x02 ABS=0x16
  182. End-0.5*tCK: HC=0x02 ABS=0x28
  183. Final: HC=0x02 ABS=0x28
  184. BYTE 7:
  185. Start: HC=0x01 ABS=0x1C
  186. End: HC=0x03 ABS=0x4C
  187. Mean: HC=0x02 ABS=0x34
  188. End-0.5*tCK: HC=0x02 ABS=0x4C
  189. Final: HC=0x02 ABS=0x4C
  190.  
  191. DQS calibration MMDC0 MPDGCTRL0 = 0x02500258, MPDGCTRL1 = 0x02480248
  192.  
  193. DQS calibration MMDC1 MPDGCTRL0 = 0x02500260, MPDGCTRL1 = 0x024C0228
  194.  
  195. Note: Array result[] holds the DRAM test result of each byte.
  196. 0: test pass. 1: test fail
  197. 4 bits respresent the result of 1 byte.
  198. result 00000001:byte 0 fail.
  199. result 00000011:byte 0, 1 fail.
  200.  
  201. Starting Read calibration...
  202.  
  203. ABS_OFFSET=0x00000000 result[00]=0x11111111
  204. ABS_OFFSET=0x04040404 result[01]=0x11111111
  205. ABS_OFFSET=0x08080808 result[02]=0x11111111
  206. ABS_OFFSET=0x0C0C0C0C result[03]=0x11111111
  207. ABS_OFFSET=0x10101010 result[04]=0x11011001
  208. ABS_OFFSET=0x14141414 result[05]=0x00011000
  209. ABS_OFFSET=0x18181818 result[06]=0x00010000
  210. ABS_OFFSET=0x1C1C1C1C result[07]=0x00000000
  211. ABS_OFFSET=0x20202020 result[08]=0x00000000
  212. ABS_OFFSET=0x24242424 result[09]=0x00000000
  213. ABS_OFFSET=0x28282828 result[0A]=0x00000000
  214. ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000
  215. ABS_OFFSET=0x30303030 result[0C]=0x00000000
  216. ABS_OFFSET=0x34343434 result[0D]=0x00000000
  217. ABS_OFFSET=0x38383838 result[0E]=0x00000000
  218. ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000
  219. ABS_OFFSET=0x40404040 result[10]=0x00000000
  220. ABS_OFFSET=0x44444444 result[11]=0x00000000
  221. ABS_OFFSET=0x48484848 result[12]=0x00000000
  222. ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000
  223. ABS_OFFSET=0x50505050 result[14]=0x00000000
  224. ABS_OFFSET=0x54545454 result[15]=0x00000000
  225. ABS_OFFSET=0x58585858 result[16]=0x00000000
  226. ABS_OFFSET=0x5C5C5C5C result[17]=0x00000000
  227. ABS_OFFSET=0x60606060 result[18]=0x00000000
  228. ABS_OFFSET=0x64646464 result[19]=0x01100000
  229. ABS_OFFSET=0x68686868 result[1A]=0x01100111
  230. ABS_OFFSET=0x6C6C6C6C result[1B]=0x11100111
  231. ABS_OFFSET=0x70707070 result[1C]=0x11111111
  232. ABS_OFFSET=0x74747474 result[1D]=0x11111111
  233. ABS_OFFSET=0x78787878 result[1E]=0x11111111
  234. ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111
  235.  
  236. Byte 0: (0x14 - 0x64), middle value:0x3c
  237. Byte 1: (0x10 - 0x64), middle value:0x3a
  238. Byte 2: (0x10 - 0x64), middle value:0x3a
  239. Byte 3: (0x18 - 0x6c), middle value:0x42
  240. Byte 4: (0x1c - 0x6c), middle value:0x44
  241. Byte 5: (0x10 - 0x60), middle value:0x38
  242. Byte 6: (0x14 - 0x60), middle value:0x3a
  243. Byte 7: (0x14 - 0x68), middle value:0x3e
  244.  
  245. MMDC0 MPRDDLCTL = 0x423A3A3C, MMDC1 MPRDDLCTL = 0x3E3A3844
  246.  
  247. Starting Write calibration...
  248.  
  249. ABS_OFFSET=0x00000000 result[00]=0x11111111
  250. ABS_OFFSET=0x04040404 result[01]=0x10111111
  251. ABS_OFFSET=0x08080808 result[02]=0x10110111
  252. ABS_OFFSET=0x0C0C0C0C result[03]=0x10110010
  253. ABS_OFFSET=0x10101010 result[04]=0x10100010
  254. ABS_OFFSET=0x14141414 result[05]=0x00000000
  255. ABS_OFFSET=0x18181818 result[06]=0x00000000
  256. ABS_OFFSET=0x1C1C1C1C result[07]=0x00000000
  257. ABS_OFFSET=0x20202020 result[08]=0x00000000
  258. ABS_OFFSET=0x24242424 result[09]=0x00000000
  259. ABS_OFFSET=0x28282828 result[0A]=0x00000000
  260. ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000
  261. ABS_OFFSET=0x30303030 result[0C]=0x00000000
  262. ABS_OFFSET=0x34343434 result[0D]=0x00000000
  263. ABS_OFFSET=0x38383838 result[0E]=0x00000000
  264. ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000
  265. ABS_OFFSET=0x40404040 result[10]=0x00000000
  266. ABS_OFFSET=0x44444444 result[11]=0x00000000
  267. ABS_OFFSET=0x48484848 result[12]=0x00000000
  268. ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000
  269. ABS_OFFSET=0x50505050 result[14]=0x00000000
  270. ABS_OFFSET=0x54545454 result[15]=0x00000000
  271. ABS_OFFSET=0x58585858 result[16]=0x00000000
  272. ABS_OFFSET=0x5C5C5C5C result[17]=0x00000000
  273. ABS_OFFSET=0x60606060 result[18]=0x01000000
  274. ABS_OFFSET=0x64646464 result[19]=0x01000000
  275. ABS_OFFSET=0x68686868 result[1A]=0x01011110
  276. ABS_OFFSET=0x6C6C6C6C result[1B]=0x01111111
  277. ABS_OFFSET=0x70707070 result[1C]=0x11111111
  278. ABS_OFFSET=0x74747474 result[1D]=0x11111111
  279. ABS_OFFSET=0x78787878 result[1E]=0x11111111
  280. ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111
  281.  
  282. Byte 0: (0x0c - 0x68), middle value:0x3a
  283. Byte 1: (0x14 - 0x64), middle value:0x3c
  284. Byte 2: (0x0c - 0x64), middle value:0x38
  285.  
  286.  
  287. (0x14 - 0x68), middle value:0x3e
  288. Byte 6: (0x04 - 0x5c), middle value:0x30
  289. Byte 7: (0x14 - 0x6c), middle value:0x40
  290.  
  291. MMDC0 MPWRDLCTL = 0x36383C3A,MMDC1 MPWRDLCTL = 0x40303E3A
  292.  
  293.  
  294. MMDC registers updated from calibration
  295.  
  296. Write leveling calibration
  297. MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x0013001B
  298. MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x001F0011
  299. MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x000D0017
  300. MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x0013001D
  301.  
  302. Read DQS Gating calibration
  303. MPDGCTRL0 PHY0 (0x021b083c) = 0x02500258
  304. MPDGCTRL1 PHY0 (0x021b0840) = 0x02480248
  305. MPDGCTRL0 PHY1 (0x021b483c) = 0x02500260
  306. MPDGCTRL1 PHY1 (0x021b4840) = 0x024C0228
  307.  
  308. Read calibration
  309. MPRDDLCTL PHY0 (0x021b0848) = 0x423A3A3C
  310. MPRDDLCTL PHY1 (0x021b4848) = 0x3E3A3844
  311.  
  312. Write calibration
  313. MPWRDLCTL PHY0 (0x021b0850) = 0x36383C3A
  314. MPWRDLCTL PHY1 (0x021b4850) = 0x40303E3A
  315.  
  316.  
  317. Success: DDR calibration completed!!!
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