API tools faq
paste
Advertisement
Guest User

Untitled

a guest
Oct 17th, 2018
211
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
SystemVerilog 23.36 KB | None | 0 0
raw download clone embed print report
  1. //////////////////////////////////////////////////////////////////////
  2. //
  3. // ORPSoC top for de0_nano board
  4. //
  5. // Instantiates modules, depending on ORPSoC defines file
  6. //
  7. // Copyright (C) 2013 Stefan Kristiansson
  8. //  <stefan.kristiansson@saunalahti.fi
  9. //
  10. // Based on de1 board by
  11. // Franck Jullien, franck.jullien@gmail.com
  12. // Which probably was based on the or1200-generic board by
  13. // Olof Kindgren, which in turn was based on orpsocv2 boards by
  14. // Julius Baxter.
  15. //
  16. //////////////////////////////////////////////////////////////////////
  17. //
  18. // This source file may be used and distributed without
  19. // restriction provided that this copyright statement is not
  20. // removed from the file and that any derivative work contains
  21. // the original copyright notice and the associated disclaimer.
  22. //
  23. // This source file is free software; you can redistribute it
  24. // and/or modify it under the terms of the GNU Lesser General
  25. // Public License as published by the Free Software Foundation;
  26. // either version 2.1 of the License, or (at your option) any
  27. // later version.
  28. //
  29. // This source is distributed in the hope that it will be
  30. // useful, but WITHOUT ANY WARRANTY; without even the implied
  31. // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
  32. // PURPOSE.  See the GNU Lesser General Public License for more
  33. // details.
  34. //
  35. // You should have received a copy of the GNU Lesser General
  36. // Public License along with this source; if not, download it
  37. // from http://www.opencores.org/lgpl.shtml
  38. //
  39. //////////////////////////////////////////////////////////////////////
  40.  
  41. `include "orpsoc-defines.v"
  42.  
  43. module orpsoc_top #(
  44.     parameter       bootrom_file = "../src/ulx3s_0/sw/spi_uimage_loader.vh"
  45. )(
  46.     input       sys_clk_pad_i,
  47.     input       btn_pad_i,
  48.  
  49.     output      tdo_pad_o,
  50.     input       tms_pad_i,
  51.     input       tck_pad_i,
  52.     input       tdi_pad_i,
  53.  
  54.     output  [1:0]   sdram_ba_pad_o,
  55.     output  [12:0]  sdram_a_pad_o,
  56.     output      sdram_cs_n_pad_o,
  57.     output      sdram_ras_pad_o,
  58.     output      sdram_cas_pad_o,
  59.     output      sdram_we_pad_o,
  60.     inout   [15:0]  sdram_dq_pad_io,
  61.     output  [1:0]   sdram_dqm_pad_o,
  62.     output      sdram_cke_pad_o,
  63.     output      sdram_clk_pad_o,
  64.  
  65.     input       uart0_srx_pad_i,
  66.     output      uart0_stx_pad_o,
  67.  
  68.     inout   [7:0]   gpio0_io,
  69.  
  70.     output ulx3s_gpio0_pin
  71. );
  72.  
  73.  
  74.  
  75. parameter   IDCODE_VALUE = 32'h14951185;
  76.  
  77.  
  78. ////////////////////////////////////////////////////////////////////////
  79. //
  80. // Clock and reset generation module
  81. //
  82. ////////////////////////////////////////////////////////////////////////
  83.  
  84. wire    async_rst;
  85. wire    wb_clk, wb_rst;
  86. wire    dbg_tck;
  87. wire    sdram_clk;
  88. wire    sdram_rst;
  89.  
  90. wire sys_clk, btn;
  91.  
  92. (* LOC="G2" *) (* IO_TYPE="LVCMOS33" *)
  93. TRELLIS_IO #(.DIR("INPUT")) clk_buf (.B(sys_clk_pad_i), .O(sys_clk));
  94.  
  95. (* LOC="R1" *) (* IO_TYPE="LVCMOS33" *)
  96. TRELLIS_IO #(.DIR("INPUT")) btn_buf (.B(btn_pad_i), .O(btn));
  97.  
  98. (* LOC="L2" *) (* IO_TYPE="LVCMOS33" *)
  99. TRELLIS_IO #(.DIR("OUTPUT")) ulx_gpio0_buf (.B(ulx3s_gpio0_pin), .I(1'b1));
  100.  
  101.  
  102. clkgen clkgen0 (
  103.     .sys_clk_pad_i  (sys_clk),
  104.     .rst_n_pad_i    (!btn),
  105.     .async_rst_o    (async_rst),
  106.     .wb_clk_o   (wb_clk),
  107.     .wb_rst_o   (wb_rst),
  108.     .sdram_clk_o    (sdram_clk),
  109.     .sdram_rst_o    (sdram_rst)
  110. );
  111.  
  112. ////////////////////////////////////////////////////////////////////////
  113. //
  114. // Modules interconnections
  115. //
  116. ////////////////////////////////////////////////////////////////////////
  117. `include "wb_intercon_dbg.vh"
  118. `include "wb_intercon.vh"
  119.  
  120. ////////////////////////////////////////////////////////////////////////
  121. //
  122. // GENERIC JTAG TAP
  123. //
  124. ////////////////////////////////////////////////////////////////////////
  125.  
  126. wire    dbg_if_select;
  127. wire    dbg_if_tdo;
  128. wire    jtag_tap_tdo;
  129. wire    jtag_tap_shift_dr;
  130. wire    jtag_tap_pause_dr;
  131. wire    jtag_tap_update_dr;
  132. wire    jtag_tap_capture_dr;
  133.  
  134. wire tdo_o, tdo_oe, tms_i, tck_i, tdi_i;
  135.  
  136. /*
  137. TDO 0+
  138. TDI 1+
  139. TMS 2+
  140. TCK 3+
  141. */
  142.  
  143. (* LOC="B11" *) (* IO_TYPE="LVCMOS33" *)
  144. TRELLIS_IO #(.DIR("OUTPUT")) tdo_buf (.B(tdo_pad_o), .I(tdo_o), .T(!tdo_oe));
  145. (* LOC="A10" *) (* IO_TYPE="LVCMOS33" *)
  146. TRELLIS_IO #(.DIR("INPUT")) tdi_buf (.B(tdi_pad_i), .O(tdi_i));
  147. (* LOC="A9" *) (* IO_TYPE="LVCMOS33" *)
  148. TRELLIS_IO #(.DIR("INPUT")) tms_buf (.B(tms_pad_i), .O(tms_i));
  149. (* LOC="B9" *) (* IO_TYPE="LVCMOS33" *)
  150. TRELLIS_IO #(.DIR("INPUT")) tck_buf (.B(tck_pad_i), .O(tck_i));
  151.  
  152.  
  153. tap_top jtag_tap0 (
  154.     .tdo_pad_o          (tdo_o),
  155.     .tms_pad_i          (tms_i),
  156.     .tck_pad_i          (tck_i),
  157.     .trst_pad_i         (async_rst),
  158.     .tdi_pad_i          (tdi_i),
  159.  
  160.     .tdo_padoe_o            (tdo_oe),
  161.  
  162.     .tdo_o              (jtag_tap_tdo),
  163.  
  164.     .shift_dr_o         (jtag_tap_shift_dr),
  165.     .pause_dr_o         (jtag_tap_pause_dr),
  166.     .update_dr_o            (jtag_tap_update_dr),
  167.     .capture_dr_o           (jtag_tap_capture_dr),
  168.  
  169.     .extest_select_o        (),
  170.     .sample_preload_select_o    (),
  171.     .mbist_select_o         (),
  172.     .debug_select_o         (dbg_if_select),
  173.  
  174.  
  175.     .bs_chain_tdi_i         (1'b0),
  176.     .mbist_tdi_i            (1'b0),
  177.     .debug_tdi_i            (dbg_if_tdo)
  178. );
  179.  
  180.  
  181. ////////////////////////////////////////////////////////////////////////
  182. //
  183. // OR1K CPU
  184. //
  185. ////////////////////////////////////////////////////////////////////////
  186.  
  187. wire    [31:0]  or1k_irq;
  188.  
  189. wire    [31:0]  or1k_dbg_dat_i;
  190. wire    [31:0]  or1k_dbg_adr_i;
  191. wire        or1k_dbg_we_i;
  192. wire        or1k_dbg_stb_i;
  193. wire        or1k_dbg_ack_o;
  194. wire    [31:0]  or1k_dbg_dat_o;
  195.  
  196. wire        or1k_dbg_stall_i;
  197. wire        or1k_dbg_ewt_i;
  198. wire    [3:0]   or1k_dbg_lss_o;
  199. wire    [1:0]   or1k_dbg_is_o;
  200. wire    [10:0]  or1k_dbg_wp_o;
  201. wire        or1k_dbg_bp_o;
  202. wire        or1k_dbg_rst;
  203.  
  204. wire        sig_tick;
  205. wire        or1k_rst;
  206.  
  207. assign or1k_rst = wb_rst | or1k_dbg_rst;
  208.  
  209. `ifdef OR1200
  210.  
  211. or1200_top #(.boot_adr(32'hf0000000))
  212. or1200_top0 (
  213.     // Instruction bus, clocks, reset
  214.     .iwb_clk_i          (wb_clk),
  215.     .iwb_rst_i          (wb_rst),
  216.     .iwb_ack_i          (wb_s2m_or1k_i_ack),
  217.     .iwb_err_i          (wb_s2m_or1k_i_err),
  218.     .iwb_rty_i          (wb_s2m_or1k_i_rty),
  219.     .iwb_dat_i          (wb_s2m_or1k_i_dat),
  220.  
  221.     .iwb_cyc_o          (wb_m2s_or1k_i_cyc),
  222.     .iwb_adr_o          (wb_m2s_or1k_i_adr),
  223.     .iwb_stb_o          (wb_m2s_or1k_i_stb),
  224.     .iwb_we_o           (wb_m2s_or1k_i_we),
  225.     .iwb_sel_o          (wb_m2s_or1k_i_sel),
  226.     .iwb_dat_o          (wb_m2s_or1k_i_dat),
  227.     .iwb_cti_o          (wb_m2s_or1k_i_cti),
  228.     .iwb_bte_o          (wb_m2s_or1k_i_bte),
  229.  
  230.     // Data bus, clocks, reset
  231.     .dwb_clk_i          (wb_clk),
  232.     .dwb_rst_i          (wb_rst),
  233.     .dwb_ack_i          (wb_s2m_or1k_d_ack),
  234.     .dwb_err_i          (wb_s2m_or1k_d_err),
  235.     .dwb_rty_i          (wb_s2m_or1k_d_rty),
  236.     .dwb_dat_i          (wb_s2m_or1k_d_dat),
  237.  
  238.     .dwb_cyc_o          (wb_m2s_or1k_d_cyc),
  239.     .dwb_adr_o          (wb_m2s_or1k_d_adr),
  240.     .dwb_stb_o          (wb_m2s_or1k_d_stb),
  241.     .dwb_we_o           (wb_m2s_or1k_d_we),
  242.     .dwb_sel_o          (wb_m2s_or1k_d_sel),
  243.     .dwb_dat_o          (wb_m2s_or1k_d_dat),
  244.     .dwb_cti_o          (wb_m2s_or1k_d_cti),
  245.     .dwb_bte_o          (wb_m2s_or1k_d_bte),
  246.  
  247.     // Debug interface ports
  248.     .dbg_stall_i            (or1k_dbg_stall_i),
  249.     .dbg_ewt_i          (1'b0),
  250.     .dbg_lss_o          (or1k_dbg_lss_o),
  251.     .dbg_is_o           (or1k_dbg_is_o),
  252.     .dbg_wp_o           (or1k_dbg_wp_o),
  253.     .dbg_bp_o           (or1k_dbg_bp_o),
  254.  
  255.     .dbg_adr_i          (or1k_dbg_adr_i),
  256.     .dbg_we_i           (or1k_dbg_we_i),
  257.     .dbg_stb_i          (or1k_dbg_stb_i),
  258.     .dbg_dat_i          (or1k_dbg_dat_i),
  259.     .dbg_dat_o          (or1k_dbg_dat_o),
  260.     .dbg_ack_o          (or1k_dbg_ack_o),
  261.  
  262.     .pm_clksd_o         (),
  263.     .pm_dc_gate_o           (),
  264.     .pm_ic_gate_o           (),
  265.     .pm_dmmu_gate_o         (),
  266.     .pm_immu_gate_o         (),
  267.     .pm_tt_gate_o           (),
  268.     .pm_cpu_gate_o          (),
  269.     .pm_wakeup_o            (),
  270.     .pm_lvolt_o         (),
  271.  
  272.     // Core clocks, resets
  273.     .clk_i              (wb_clk),
  274.     .rst_i              (or1k_rst),
  275.  
  276.     .clmode_i           (2'b00),
  277.  
  278.     // Interrupts
  279.     .pic_ints_i         (or1k_irq),
  280.     .sig_tick           (sig_tick),
  281.  
  282.     .pm_cpustall_i          (1'b0)
  283. );
  284. `endif
  285.  
  286. `ifdef MOR1KX
  287. mor1kx #(
  288.     .FEATURE_DEBUGUNIT("ENABLED"),
  289.     .FEATURE_CMOV("ENABLED"),
  290.     .FEATURE_INSTRUCTIONCACHE("ENABLED"),
  291.     .OPTION_ICACHE_BLOCK_WIDTH(5),
  292.     .OPTION_ICACHE_SET_WIDTH(8),
  293.     .OPTION_ICACHE_WAYS(2),
  294.     .OPTION_ICACHE_LIMIT_WIDTH(32),
  295.     .FEATURE_IMMU("ENABLED"),
  296.     .FEATURE_DATACACHE("ENABLED"),
  297.     .OPTION_DCACHE_BLOCK_WIDTH(5),
  298.     .OPTION_DCACHE_SET_WIDTH(8),
  299.     .OPTION_DCACHE_WAYS(2),
  300.     .OPTION_DCACHE_LIMIT_WIDTH(31),
  301.     .FEATURE_DMMU("ENABLED"),
  302.     .OPTION_PIC_TRIGGER("LATCHED_LEVEL"),
  303.  
  304.     .IBUS_WB_TYPE("B3_REGISTERED_FEEDBACK"),
  305.     .DBUS_WB_TYPE("B3_REGISTERED_FEEDBACK"),
  306.     .OPTION_CPU0("CAPPUCCINO"),
  307.     .OPTION_RESET_PC(32'hf0000000)
  308. ) mor1kx0 (
  309.     .iwbm_adr_o(wb_m2s_or1k_i_adr),
  310.     .iwbm_stb_o(wb_m2s_or1k_i_stb),
  311.     .iwbm_cyc_o(wb_m2s_or1k_i_cyc),
  312.     .iwbm_sel_o(wb_m2s_or1k_i_sel),
  313.     .iwbm_we_o (wb_m2s_or1k_i_we),
  314.     .iwbm_cti_o(wb_m2s_or1k_i_cti),
  315.     .iwbm_bte_o(wb_m2s_or1k_i_bte),
  316.     .iwbm_dat_o(wb_m2s_or1k_i_dat),
  317.  
  318.     .dwbm_adr_o(wb_m2s_or1k_d_adr),
  319.     .dwbm_stb_o(wb_m2s_or1k_d_stb),
  320.     .dwbm_cyc_o(wb_m2s_or1k_d_cyc),
  321.     .dwbm_sel_o(wb_m2s_or1k_d_sel),
  322.     .dwbm_we_o (wb_m2s_or1k_d_we ),
  323.     .dwbm_cti_o(wb_m2s_or1k_d_cti),
  324.     .dwbm_bte_o(wb_m2s_or1k_d_bte),
  325.     .dwbm_dat_o(wb_m2s_or1k_d_dat),
  326.  
  327.     .clk(wb_clk),
  328.     .rst(or1k_rst),
  329.  
  330.     .iwbm_err_i(wb_s2m_or1k_i_err),
  331.     .iwbm_ack_i(wb_s2m_or1k_i_ack),
  332.     .iwbm_dat_i(wb_s2m_or1k_i_dat),
  333.     .iwbm_rty_i(wb_s2m_or1k_i_rty),
  334.  
  335.     .dwbm_err_i(wb_s2m_or1k_d_err),
  336.     .dwbm_ack_i(wb_s2m_or1k_d_ack),
  337.     .dwbm_dat_i(wb_s2m_or1k_d_dat),
  338.     .dwbm_rty_i(wb_s2m_or1k_d_rty),
  339.  
  340.     .avm_d_address_o (),
  341.     .avm_d_byteenable_o (),
  342.     .avm_d_read_o (),
  343.     .avm_d_readdata_i (32'h00000000),
  344.     .avm_d_burstcount_o (),
  345.     .avm_d_write_o (),
  346.     .avm_d_writedata_o (),
  347.     .avm_d_waitrequest_i (1'b0),
  348.     .avm_d_readdatavalid_i (1'b0),
  349.  
  350.     .avm_i_address_o (),
  351.     .avm_i_byteenable_o (),
  352.     .avm_i_read_o (),
  353.     .avm_i_readdata_i (32'h00000000),
  354.     .avm_i_burstcount_o (),
  355.     .avm_i_waitrequest_i (1'b0),
  356.     .avm_i_readdatavalid_i (1'b0),
  357.  
  358.     .irq_i(or1k_irq),
  359.  
  360.     .traceport_exec_valid_o  (),
  361.     .traceport_exec_pc_o     (),
  362.     .traceport_exec_insn_o   (),
  363.     .traceport_exec_wbdata_o (),
  364.     .traceport_exec_wbreg_o  (),
  365.     .traceport_exec_wben_o   (),
  366.  
  367.     .multicore_coreid_i   (32'd0),
  368.     .multicore_numcores_i (32'd0),
  369.  
  370.     .snoop_adr_i (32'd0),
  371.     .snoop_en_i  (1'b0),
  372.  
  373.     .du_addr_i(or1k_dbg_adr_i[15:0]),
  374.     .du_stb_i(or1k_dbg_stb_i),
  375.     .du_dat_i(or1k_dbg_dat_i),
  376.     .du_we_i(or1k_dbg_we_i),
  377.     .du_dat_o(or1k_dbg_dat_o),
  378.     .du_ack_o(or1k_dbg_ack_o),
  379.     .du_stall_i(or1k_dbg_stall_i),
  380.     .du_stall_o(or1k_dbg_bp_o)
  381. );
  382.  
  383. `endif
  384. ////////////////////////////////////////////////////////////////////////
  385. //
  386. // Debug Interface
  387. //
  388. ////////////////////////////////////////////////////////////////////////
  389.  
  390. adbg_top dbg_if0 (
  391.     // OR1K interface
  392.     .cpu0_clk_i (wb_clk),
  393.     .cpu0_rst_o (or1k_dbg_rst),
  394.     .cpu0_addr_o    (or1k_dbg_adr_i),
  395.     .cpu0_data_o    (or1k_dbg_dat_i),
  396.     .cpu0_stb_o (or1k_dbg_stb_i),
  397.     .cpu0_we_o  (or1k_dbg_we_i),
  398.     .cpu0_data_i    (or1k_dbg_dat_o),
  399.     .cpu0_ack_i (or1k_dbg_ack_o),
  400.     .cpu0_stall_o   (or1k_dbg_stall_i),
  401.     .cpu0_bp_i  (or1k_dbg_bp_o),
  402.  
  403.     // TAP interface
  404.     .tck_i      (tck_i),
  405.     .tdi_i      (jtag_tap_tdo),
  406.     .tdo_o      (dbg_if_tdo),
  407.     .rst_i      (wb_rst),
  408.     .capture_dr_i   (jtag_tap_capture_dr),
  409.     .shift_dr_i (jtag_tap_shift_dr),
  410.     .pause_dr_i (jtag_tap_pause_dr),
  411.     .update_dr_i    (jtag_tap_update_dr),
  412.     .debug_select_i (dbg_if_select),
  413.  
  414.     // Wishbone debug master
  415.     .wb_clk_i   (wb_clk),
  416.     .wb_rst_i       (1'b0),
  417.     .wb_dat_i   (wb_s2m_dbg_dat),
  418.     .wb_ack_i   (wb_s2m_dbg_ack),
  419.     .wb_err_i   (wb_s2m_dbg_err),
  420.  
  421.     .wb_adr_o   (wb_m2s_dbg_adr),
  422.     .wb_dat_o   (wb_m2s_dbg_dat),
  423.     .wb_cyc_o   (wb_m2s_dbg_cyc),
  424.     .wb_stb_o   (wb_m2s_dbg_stb),
  425.     .wb_sel_o   (wb_m2s_dbg_sel),
  426.     .wb_we_o    (wb_m2s_dbg_we),
  427.     .wb_cab_o       (),
  428.     .wb_cti_o   (wb_m2s_dbg_cti),
  429.     .wb_bte_o   (wb_m2s_dbg_bte),
  430.  
  431.     .wb_jsp_adr_i (32'd0),
  432.     .wb_jsp_dat_i (32'd0),
  433.     .wb_jsp_cyc_i (1'b0),
  434.     .wb_jsp_stb_i (1'b0),
  435.     .wb_jsp_sel_i (4'h0),
  436.     .wb_jsp_we_i  (1'b0),
  437.     .wb_jsp_cab_i (1'b0),
  438.     .wb_jsp_cti_i (3'd0),
  439.     .wb_jsp_bte_i (2'd0),
  440.     .wb_jsp_dat_o (),
  441.     .wb_jsp_ack_o (),
  442.     .wb_jsp_err_o (),
  443.  
  444.     .int_o ()
  445. );
  446.  
  447. ////////////////////////////////////////////////////////////////////////
  448. //
  449. // ROM
  450. //
  451. ////////////////////////////////////////////////////////////////////////
  452.  
  453.    localparam WB_BOOTROM_MEM_DEPTH = 1024;
  454.  
  455. wb_bootrom
  456.   #(.DEPTH (WB_BOOTROM_MEM_DEPTH),
  457.     .MEMFILE (bootrom_file))
  458.    bootrom
  459.      (//Wishbone Master interface
  460.       .wb_clk_i (wb_clk),
  461.       .wb_rst_i (wb_rst),
  462.       .wb_adr_i (wb_m2s_rom0_adr),
  463.       .wb_cyc_i (wb_m2s_rom0_cyc),
  464.       .wb_stb_i (wb_m2s_rom0_stb),
  465.       .wb_dat_o (wb_s2m_rom0_dat),
  466.       .wb_ack_o (wb_s2m_rom0_ack));
  467.  
  468.    assign wb_s2m_rom0_err = 1'b0;
  469.    assign wb_s2m_rom0_rty = 1'b0;
  470.  
  471. ////////////////////////////////////////////////////////////////////////
  472. //
  473. // SDRAM Memory Controller
  474. //
  475. ////////////////////////////////////////////////////////////////////////
  476.  
  477. wire    [15:0]  sdram_dq_i;
  478. wire    [15:0]  sdram_dq_o;
  479. wire        sdram_dq_oe;
  480. wire    [1:0]   sdram_dqm_o;
  481.  
  482. wire [1:0] sdram_ba_o;
  483. wire [12:0] sdram_a_o;
  484. wire sdram_cs_n_o, sdram_ras_o, sdram_cas_o, sdram_we_o, sdram_cke_o;
  485.  
  486. (* LOC="P19" *) (* IO_TYPE="LVCMOS33" *)
  487. TRELLIS_IO #(.DIR("OUTPUT")) sdram_ba_buf_0 (.B(sdram_ba_pad_o[0]), .I(sdram_ba_o[0]));
  488. (* LOC="N20" *) (* IO_TYPE="LVCMOS33" *)
  489. TRELLIS_IO #(.DIR("OUTPUT")) sdram_ba_buf_1 (.B(sdram_ba_pad_o[1]), .I(sdram_ba_o[1]));
  490.  
  491. (* LOC="M20" *) (* IO_TYPE="LVCMOS33" *)
  492. TRELLIS_IO #(.DIR("OUTPUT")) sdram_a_buf_0 (.B(sdram_a_pad_o[0]), .I(sdram_a_o[0]));
  493. (* LOC="M19" *) (* IO_TYPE="LVCMOS33" *)
  494. TRELLIS_IO #(.DIR("OUTPUT")) sdram_a_buf_1 (.B(sdram_a_pad_o[1]), .I(sdram_a_o[1]));
  495. (* LOC="L20" *) (* IO_TYPE="LVCMOS33" *)
  496. TRELLIS_IO #(.DIR("OUTPUT")) sdram_a_buf_2 (.B(sdram_a_pad_o[2]), .I(sdram_a_o[2]));
  497. (* LOC="L19" *) (* IO_TYPE="LVCMOS33" *)
  498. TRELLIS_IO #(.DIR("OUTPUT")) sdram_a_buf_3 (.B(sdram_a_pad_o[3]), .I(sdram_a_o[3]));
  499. (* LOC="K20" *) (* IO_TYPE="LVCMOS33" *)
  500. TRELLIS_IO #(.DIR("OUTPUT")) sdram_a_buf_4 (.B(sdram_a_pad_o[4]), .I(sdram_a_o[4]));
  501. (* LOC="K19" *) (* IO_TYPE="LVCMOS33" *)
  502. TRELLIS_IO #(.DIR("OUTPUT")) sdram_a_buf_5 (.B(sdram_a_pad_o[5]), .I(sdram_a_o[5]));
  503. (* LOC="K18" *) (* IO_TYPE="LVCMOS33" *)
  504. TRELLIS_IO #(.DIR("OUTPUT")) sdram_a_buf_6 (.B(sdram_a_pad_o[6]), .I(sdram_a_o[6]));
  505. (* LOC="J20" *) (* IO_TYPE="LVCMOS33" *)
  506. TRELLIS_IO #(.DIR("OUTPUT")) sdram_a_buf_7 (.B(sdram_a_pad_o[7]), .I(sdram_a_o[7]));
  507. (* LOC="J19" *) (* IO_TYPE="LVCMOS33" *)
  508. TRELLIS_IO #(.DIR("OUTPUT")) sdram_a_buf_8 (.B(sdram_a_pad_o[8]), .I(sdram_a_o[8]));
  509. (* LOC="H20" *) (* IO_TYPE="LVCMOS33" *)
  510. TRELLIS_IO #(.DIR("OUTPUT")) sdram_a_buf_9 (.B(sdram_a_pad_o[9]), .I(sdram_a_o[9]));
  511. (* LOC="N19" *) (* IO_TYPE="LVCMOS33" *)
  512. TRELLIS_IO #(.DIR("OUTPUT")) sdram_a_buf_10 (.B(sdram_a_pad_o[10]), .I(sdram_a_o[10]));
  513. (* LOC="G20" *) (* IO_TYPE="LVCMOS33" *)
  514. TRELLIS_IO #(.DIR("OUTPUT")) sdram_a_buf_11 (.B(sdram_a_pad_o[11]), .I(sdram_a_o[11]));
  515. (* LOC="G19" *) (* IO_TYPE="LVCMOS33" *)
  516. TRELLIS_IO #(.DIR("OUTPUT")) sdram_a_buf_12 (.B(sdram_a_pad_o[12]), .I(sdram_a_o[12]));
  517.  
  518. (* LOC="F19" *) (* IO_TYPE="LVCMOS33" *)
  519. TRELLIS_IO #(.DIR("OUTPUT")) sdram_clk_buf (.B(sdram_clk_pad_o), .I(sdram_clk));
  520. (* LOC="F20" *) (* IO_TYPE="LVCMOS33" *)
  521. TRELLIS_IO #(.DIR("OUTPUT")) sdram_cke_buf (.B(sdram_cke_pad_o), .I(sdram_cke_o));
  522. (* LOC="P20" *) (* IO_TYPE="LVCMOS33" *)
  523. TRELLIS_IO #(.DIR("OUTPUT")) sdram_csn_buf (.B(sdram_cs_n_pad_o), .I(sdram_cs_n_o));
  524. (* LOC="T20" *) (* IO_TYPE="LVCMOS33" *)
  525. TRELLIS_IO #(.DIR("OUTPUT")) sdram_wen_buf (.B(sdram_we_pad_o), .I(sdram_we_o));
  526. (* LOC="R20" *) (* IO_TYPE="LVCMOS33" *)
  527. TRELLIS_IO #(.DIR("OUTPUT")) sdram_ras_buf (.B(sdram_ras_pad_o), .I(sdram_ras_o));
  528. (* LOC="T19" *) (* IO_TYPE="LVCMOS33" *)
  529. TRELLIS_IO #(.DIR("OUTPUT")) sdram_cas_buf (.B(sdram_cas_pad_o), .I(sdram_cas_o));
  530.  
  531. (* LOC="U19" *) (* IO_TYPE="LVCMOS33" *)
  532. TRELLIS_IO #(.DIR("OUTPUT")) sdram_dqm_buf_0 (.B(sdram_dqm_pad_o[0]), .I(sdram_dqm_o[0]));
  533. (* LOC="E20" *) (* IO_TYPE="LVCMOS33" *)
  534. TRELLIS_IO #(.DIR("OUTPUT")) sdram_dqm_buf_1 (.B(sdram_dqm_pad_o[1]), .I(sdram_dqm_o[1]));
  535.  
  536. (* LOC="J16" *) (* IO_TYPE="LVCMOS33" *)
  537. TRELLIS_IO #(.DIR("BIDIR")) sdram_dq_buf_0 (.B(sdram_dq_pad_io[0]), .I(sdram_dq_o[0]), .O(sdram_dq_i[0]), .T(!sdram_dq_oe));
  538. (* LOC="L18" *) (* IO_TYPE="LVCMOS33" *)
  539. TRELLIS_IO #(.DIR("BIDIR")) sdram_dq_buf_1 (.B(sdram_dq_pad_io[1]), .I(sdram_dq_o[1]), .O(sdram_dq_i[1]), .T(!sdram_dq_oe));
  540. (* LOC="M18" *) (* IO_TYPE="LVCMOS33" *)
  541. TRELLIS_IO #(.DIR("BIDIR")) sdram_dq_buf_2 (.B(sdram_dq_pad_io[2]), .I(sdram_dq_o[2]), .O(sdram_dq_i[2]), .T(!sdram_dq_oe));
  542. (* LOC="N18" *) (* IO_TYPE="LVCMOS33" *)
  543. TRELLIS_IO #(.DIR("BIDIR")) sdram_dq_buf_3 (.B(sdram_dq_pad_io[3]), .I(sdram_dq_o[3]), .O(sdram_dq_i[3]), .T(!sdram_dq_oe));
  544. (* LOC="P18" *) (* IO_TYPE="LVCMOS33" *)
  545. TRELLIS_IO #(.DIR("BIDIR")) sdram_dq_buf_4 (.B(sdram_dq_pad_io[4]), .I(sdram_dq_o[4]), .O(sdram_dq_i[4]), .T(!sdram_dq_oe));
  546. (* LOC="T18" *) (* IO_TYPE="LVCMOS33" *)
  547. TRELLIS_IO #(.DIR("BIDIR")) sdram_dq_buf_5 (.B(sdram_dq_pad_io[5]), .I(sdram_dq_o[5]), .O(sdram_dq_i[5]), .T(!sdram_dq_oe));
  548. (* LOC="T17" *) (* IO_TYPE="LVCMOS33" *)
  549. TRELLIS_IO #(.DIR("BIDIR")) sdram_dq_buf_6 (.B(sdram_dq_pad_io[6]), .I(sdram_dq_o[6]), .O(sdram_dq_i[6]), .T(!sdram_dq_oe));
  550. (* LOC="U20" *) (* IO_TYPE="LVCMOS33" *)
  551. TRELLIS_IO #(.DIR("BIDIR")) sdram_dq_buf_7 (.B(sdram_dq_pad_io[7]), .I(sdram_dq_o[7]), .O(sdram_dq_i[7]), .T(!sdram_dq_oe));
  552. (* LOC="E19" *) (* IO_TYPE="LVCMOS33" *)
  553. TRELLIS_IO #(.DIR("BIDIR")) sdram_dq_buf_8 (.B(sdram_dq_pad_io[8]), .I(sdram_dq_o[8]), .O(sdram_dq_i[8]), .T(!sdram_dq_oe));
  554. (* LOC="D20" *) (* IO_TYPE="LVCMOS33" *)
  555. TRELLIS_IO #(.DIR("BIDIR")) sdram_dq_buf_9 (.B(sdram_dq_pad_io[9]), .I(sdram_dq_o[9]), .O(sdram_dq_i[9]), .T(!sdram_dq_oe));
  556. (* LOC="D19" *) (* IO_TYPE="LVCMOS33" *)
  557. TRELLIS_IO #(.DIR("BIDIR")) sdram_dq_buf_10 (.B(sdram_dq_pad_io[10]), .I(sdram_dq_o[10]), .O(sdram_dq_i[10]), .T(!sdram_dq_oe));
  558. (* LOC="C20" *) (* IO_TYPE="LVCMOS33" *)
  559. TRELLIS_IO #(.DIR("BIDIR")) sdram_dq_buf_11 (.B(sdram_dq_pad_io[11]), .I(sdram_dq_o[11]), .O(sdram_dq_i[11]), .T(!sdram_dq_oe));
  560. (* LOC="E18" *) (* IO_TYPE="LVCMOS33" *)
  561. TRELLIS_IO #(.DIR("BIDIR")) sdram_dq_buf_12 (.B(sdram_dq_pad_io[12]), .I(sdram_dq_o[12]), .O(sdram_dq_i[12]), .T(!sdram_dq_oe));
  562. (* LOC="F18" *) (* IO_TYPE="LVCMOS33" *)
  563. TRELLIS_IO #(.DIR("BIDIR")) sdram_dq_buf_13 (.B(sdram_dq_pad_io[13]), .I(sdram_dq_o[13]), .O(sdram_dq_i[13]), .T(!sdram_dq_oe));
  564. (* LOC="J18" *) (* IO_TYPE="LVCMOS33" *)
  565. TRELLIS_IO #(.DIR("BIDIR")) sdram_dq_buf_14 (.B(sdram_dq_pad_io[14]), .I(sdram_dq_o[14]), .O(sdram_dq_i[14]), .T(!sdram_dq_oe));
  566. (* LOC="J17" *) (* IO_TYPE="LVCMOS33" *)
  567. TRELLIS_IO #(.DIR("BIDIR")) sdram_dq_buf_15 (.B(sdram_dq_pad_io[15]), .I(sdram_dq_o[15]), .O(sdram_dq_i[15]), .T(!sdram_dq_oe));
  568.  
  569. assign  wb_s2m_sdram_ibus_err = 0;
  570. assign  wb_s2m_sdram_ibus_rty = 0;
  571.  
  572. assign  wb_s2m_sdram_dbus_err = 0;
  573. assign  wb_s2m_sdram_dbus_rty = 0;
  574.  
  575. wb_sdram_ctrl #(
  576.     .TECHNOLOGY         ("ECP5"),
  577.     .CLK_FREQ_MHZ           (25),   // sdram_clk freq in MHZ
  578.     .POWERUP_DELAY          (200),  // power up delay in us
  579.     .REFRESH_MS         (32),   // delay between refresh cycles im ms
  580.     .WB_PORTS           (2),    // Number of wishbone ports
  581.     .ROW_WIDTH          (13),   // Row width
  582.     .COL_WIDTH          (9),    // Column width
  583.     .BA_WIDTH           (2),    // Ba width
  584.     .tCAC               (2),    // CAS Latency
  585.     .tRAC               (5),    // RAS Latency
  586.     .tRP                (2),    // Command Period (PRE to ACT)
  587.     .tRC                (7),    // Command Period (REF to REF / ACT to ACT)
  588.     .tMRD               (2) // Mode Register Set To Command Delay time
  589. )
  590.  
  591. wb_sdram_ctrl0 (
  592.     // External SDRAM interface
  593.     .ba_pad_o   (sdram_ba_o[1:0]),
  594.     .a_pad_o    (sdram_a_o[12:0]),
  595.     .cs_n_pad_o (sdram_cs_n_o),
  596.     .ras_pad_o  (sdram_ras_o),
  597.     .cas_pad_o  (sdram_cas_o),
  598.     .we_pad_o   (sdram_we_o),
  599.     .dq_i       (sdram_dq_i[15:0]),
  600.     .dq_o       (sdram_dq_o[15:0]),
  601.     .dqm_pad_o  (sdram_dqm_o[1:0]),
  602.     .dq_oe      (sdram_dq_oe),
  603.     .cke_pad_o  (sdram_cke_o),
  604.     .sdram_clk  (sdram_clk),
  605.     .sdram_rst  (sdram_rst),
  606.  
  607.     .wb_clk     (wb_clk),
  608.     .wb_rst     (wb_rst),
  609.  
  610.     .wb_adr_i   ({wb_m2s_sdram_ibus_adr, wb_m2s_sdram_dbus_adr}),
  611.     .wb_stb_i   ({wb_m2s_sdram_ibus_stb, wb_m2s_sdram_dbus_stb}),
  612.     .wb_cyc_i   ({wb_m2s_sdram_ibus_cyc, wb_m2s_sdram_dbus_cyc}),
  613.     .wb_cti_i   ({wb_m2s_sdram_ibus_cti, wb_m2s_sdram_dbus_cti}),
  614.     .wb_bte_i   ({wb_m2s_sdram_ibus_bte, wb_m2s_sdram_dbus_bte}),
  615.     .wb_we_i    ({wb_m2s_sdram_ibus_we,  wb_m2s_sdram_dbus_we }),
  616.     .wb_sel_i   ({wb_m2s_sdram_ibus_sel, wb_m2s_sdram_dbus_sel}),
  617.     .wb_dat_i   ({wb_m2s_sdram_ibus_dat, wb_m2s_sdram_dbus_dat}),
  618.     .wb_dat_o   ({wb_s2m_sdram_ibus_dat, wb_s2m_sdram_dbus_dat}),
  619.     .wb_ack_o   ({wb_s2m_sdram_ibus_ack, wb_s2m_sdram_dbus_ack})
  620. );
  621.  
  622. ////////////////////////////////////////////////////////////////////////
  623. //
  624. // UART0
  625. //
  626. ////////////////////////////////////////////////////////////////////////
  627.  
  628. wire    uart0_irq;
  629. wire  uart0_stx_o, uart0_srx_i;
  630.  
  631. (* LOC="L4" *) (* IO_TYPE="LVCMOS33" *)
  632. TRELLIS_IO #(.DIR("OUTPUT")) utx_buf (.B(uart0_stx_pad_o), .I(uart0_stx_o));
  633. (* LOC="M1" *) (* IO_TYPE="LVCMOS33" *)
  634. TRELLIS_IO #(.DIR("INPUT")) urx_buf (.B(uart0_srx_pad_i), .O(uart0_srx_i));
  635.  
  636. assign  wb_s2m_uart0_err = 0;
  637. assign  wb_s2m_uart0_rty = 0;
  638.  
  639. uart_top uart16550_0 (
  640.     // Wishbone slave interface
  641.     .wb_clk_i   (wb_clk),
  642.     .wb_rst_i   (wb_rst),
  643.     .wb_adr_i   (wb_m2s_uart0_adr[2:0]),
  644.     .wb_dat_i   (wb_m2s_uart0_dat),
  645.     .wb_we_i    (wb_m2s_uart0_we),
  646.     .wb_stb_i   (wb_m2s_uart0_stb),
  647.     .wb_cyc_i   (wb_m2s_uart0_cyc),
  648.     .wb_sel_i   (4'b0), // Not used in 8-bit mode
  649.     .wb_dat_o   (wb_s2m_uart0_dat),
  650.     .wb_ack_o   (wb_s2m_uart0_ack),
  651.  
  652.     // Outputs
  653.     .int_o      (uart0_irq),
  654.     .stx_pad_o  (uart0_stx_o),
  655.     .rts_pad_o  (),
  656.     .dtr_pad_o  (),
  657.  
  658.     // Inputs
  659.     .srx_pad_i  (uart0_srx_i),
  660.     .cts_pad_i  (1'b0),
  661.     .dsr_pad_i  (1'b0),
  662.     .ri_pad_i   (1'b0),
  663.     .dcd_pad_i  (1'b0)
  664. );
  665.  
  666.  
  667. ////////////////////////////////////////////////////////////////////////
  668. //
  669. // GPIO 0
  670. //
  671. ////////////////////////////////////////////////////////////////////////
  672.  
  673. (* LOC="B2" *) (* IO_TYPE="LVCMOS33" *)
  674. TRELLIS_IO #(.DIR("OUTPUT")) led_buf_0 (.B(gpio0_io[0]), .I(gpio0_out[0]));
  675. (* LOC="C2" *) (* IO_TYPE="LVCMOS33" *)
  676. TRELLIS_IO #(.DIR("OUTPUT")) led_buf_1 (.B(gpio0_io[1]), .I(gpio0_out[1]));
  677. (* LOC="C1" *) (* IO_TYPE="LVCMOS33" *)
  678. TRELLIS_IO #(.DIR("OUTPUT")) led_buf_2 (.B(gpio0_io[2]), .I(gpio0_out[2]));
  679. (* LOC="D2" *) (* IO_TYPE="LVCMOS33" *)
  680. TRELLIS_IO #(.DIR("OUTPUT")) led_buf_3 (.B(gpio0_io[3]), .I(gpio0_out[3]));
  681.  
  682. (* LOC="D1" *) (* IO_TYPE="LVCMOS33" *)
  683. TRELLIS_IO #(.DIR("OUTPUT")) led_buf_4 (.B(gpio0_io[4]), .I(gpio0_out[4]));
  684. (* LOC="E2" *) (* IO_TYPE="LVCMOS33" *)
  685. TRELLIS_IO #(.DIR("OUTPUT")) led_buf_5 (.B(gpio0_io[5]), .I(gpio0_out[5]));
  686. (* LOC="E1" *) (* IO_TYPE="LVCMOS33" *)
  687. TRELLIS_IO #(.DIR("OUTPUT")) led_buf_6 (.B(gpio0_io[6]), .I(gpio0_out[6]));
  688. (* LOC="H3" *) (* IO_TYPE="LVCMOS33" *)
  689. TRELLIS_IO #(.DIR("OUTPUT")) led_buf_7 (.B(gpio0_io[7]), .I(gpio0_out[7]));
  690.  
  691. wire [7:0]  gpio0_out;
  692.  
  693. gpio gpio0 (
  694.     // GPIO bus
  695.     .gpio_i     (8'b0),
  696.     .gpio_o     (gpio0_out),
  697.     .gpio_dir_o (),
  698.     // Wishbone slave interface
  699.     .wb_adr_i   (wb_m2s_gpio0_adr[0]),
  700.     .wb_dat_i   (wb_m2s_gpio0_dat),
  701.     .wb_we_i    (wb_m2s_gpio0_we),
  702.     .wb_cyc_i   (wb_m2s_gpio0_cyc),
  703.     .wb_stb_i   (wb_m2s_gpio0_stb),
  704.     .wb_cti_i   (wb_m2s_gpio0_cti),
  705.     .wb_bte_i   (wb_m2s_gpio0_bte),
  706.     .wb_dat_o   (wb_s2m_gpio0_dat),
  707.     .wb_ack_o   (wb_s2m_gpio0_ack),
  708.     .wb_err_o   (wb_s2m_gpio0_err),
  709.     .wb_rty_o   (wb_s2m_gpio0_rty),
  710.  
  711.     .wb_clk     (wb_clk),
  712.     .wb_rst     (wb_rst)
  713. );
  714.  
  715.  
  716. ////////////////////////////////////////////////////////////////////////
  717. //
  718. // Interrupt assignment
  719. //
  720. ////////////////////////////////////////////////////////////////////////
  721.  
  722. assign or1k_irq[0] = 0; // Non-maskable inside OR1K
  723. assign or1k_irq[1] = 0; // Non-maskable inside OR1K
  724. assign or1k_irq[2] = uart0_irq;
  725. assign or1k_irq[3] = 0;
  726. assign or1k_irq[4] = 0;
  727. assign or1k_irq[5] = 0;
  728. assign or1k_irq[6] = 0;
  729. assign or1k_irq[7] = 0;
  730. assign or1k_irq[8] = 0;
  731. assign or1k_irq[9] = 0;
  732. assign or1k_irq[10] = 0;
  733. assign or1k_irq[11] = 0;
  734. assign or1k_irq[12] = 0;
  735. assign or1k_irq[13] = 0;
  736. assign or1k_irq[14] = 0;
  737. assign or1k_irq[15] = 0;
  738. assign or1k_irq[16] = 0;
  739. assign or1k_irq[17] = 0;
  740. assign or1k_irq[18] = 0;
  741. assign or1k_irq[19] = 0;
  742. assign or1k_irq[20] = 0;
  743. assign or1k_irq[21] = 0;
  744. assign or1k_irq[22] = 0;
  745. assign or1k_irq[23] = 0;
  746. assign or1k_irq[24] = 0;
  747. assign or1k_irq[25] = 0;
  748. assign or1k_irq[26] = 0;
  749. assign or1k_irq[27] = 0;
  750. assign or1k_irq[28] = 0;
  751. assign or1k_irq[29] = 0;
  752. assign or1k_irq[30] = 0;
  753. assign or1k_irq[31] = 0;
  754.  
  755. endmodule // orpsoc_top
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!