{
	"files": [
		{
			"file_type": "verilogSource",
			"is_include_file": false,
			"logical_name": "",
			"name": "../src/fusesoc_utils_blinky_0/blinky.v"
		},
		{
			"file_type": "cppSource",
			"is_include_file": false,
			"logical_name": "",
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		{
			"file_type": "user",
			"is_include_file": false,
			"logical_name": "",
			"name": "../src/fusesoc_utils_blinky_0/bench/testb.h"
		}
	],
	"hooks": {},
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	"parameters": {
		"clk_freq_hz": {
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			"default": 10000,
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		"vcd": {
			"datatype": "bool",
			"paramtype": "plusarg"
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			"verilator_options": [
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	"vpi": []
}