`timescale 1ns / 1ps
module rategen_1(
    input clk,
    output cy1
    );
reg [25:0] q = 0;
always @(posedge clk)
    if(~cy1)
        q <= q+1;
    else q <= 0;
//assign cy = (q == 49999999);
assign cy1 = (q == 4); //for testing purpose
endmodule

////////////////////////////////////////////////

`timescale 1ns / 1ps
module rategen_2(
    input clk,
    output cy2
    );
reg [25:0] q = 0;
always @(posedge clk)
    if(~cy2)
        q <= q+2;
    else q <= 0;
//assign cy = (q == 49999999);
assign cy2 = (q == 4); //for testing purpose
endmodule

///////////////////////////////////////////////

`timescale 1ns / 1ps
module melyik(
    input clk,
    input dir,
     input ce1,ce2,
    output led
    );
reg ld;
always @(posedge clk)
    if(dir==1)
        ld <= (~ce2);
    else
        ld <= ce1;
assign led=ld;
endmodule

//////////////////////////////////////////

`timescale 1ns / 1ps
module top_module(
    input clk,
    input SW0,
    output LED
    );
reg dir;
wire ce1, ce2;
always @(posedge clk)
    dir <= SW0;
rategen_1 gen1(
    .clk(clk),
    .cy1(ce1)
    );
rategen_2 gen2(
    .clk(clk),
    .cy2(ce2)
    );
melyik gen1_gen2(
    .clk(clk),
    .dir(dir),
     .ce1(ce1),
     .ce2(ce2),
    .led(LED)
    );
endmodule