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  1. /dts-v1/;
  2.  
  3. / {
  4. interrupt-parent = <0x01>;
  5. compatible = "qcom,ipq8064-ap161\0qcom,ipq8064";
  6. #size-cells = <0x01>;
  7. model = "QCA IPQ8064/AP161";
  8. #address-cells = <0x01>;
  9. cpu_type = <0x18010000>;
  10.  
  11. clock-controller {
  12. compatible = "qcom,krait-cc-v1";
  13. #clock-cells = <0x01>;
  14. phandle = <0x05>;
  15. linux,phandle = <0x05>;
  16. };
  17.  
  18. clocks {
  19.  
  20. sleep_clk {
  21. compatible = "fixed-clock";
  22. clock-frequency = <0x8000>;
  23. #clock-cells = <0x00>;
  24. phandle = <0x15>;
  25. linux,phandle = <0x15>;
  26. };
  27. };
  28.  
  29. memory {
  30. device_type = "memory";
  31. reg = <0x40000000 0x20000000>;
  32. };
  33.  
  34. cpus {
  35. #size-cells = <0x00>;
  36. #address-cells = <0x01>;
  37.  
  38. cpu@0 {
  39. device_type = "cpu";
  40. operating-points-0-5 = <0x1a5248 0x10c8e0 0x155cc0 0xfa3e8 0xf4240 0xe7ef0 0xc3500 0xdbba0 0x927c0 0xcf850 0x5dc00 0xc96a8>;
  41. cooling-max-state = <0x0a>;
  42. operating-points-0-6 = <0x1a5248 0x100590 0x155cc0 0xee098 0xf4240 0xdbba0 0xc3500 0xcf850 0x927c0 0xc3500 0x5dc00 0xbd358>;
  43. cooling-min-state = <0x00>;
  44. cpu_fab_threshold = <0x3b9aca00>;
  45. compatible = "qcom,krait";
  46. clocks = <0x05 0x00>;
  47. operating-points-0-1 = <0x1a5248 0x12b128 0x155cc0 0x118c30 0xf4240 0x106738 0xc3500 0xfa3e8 0x927c0 0xee098 0x5dc00 0xe7ef0>;
  48. core-supply = <0x06>;
  49. qcom,imem = <0x07>;
  50. operating-points-0-3 = <0x1a5248 0x11edd8 0x155cc0 0x10c8e0 0xf4240 0xfa3e8 0xc3500 0xee098 0x927c0 0xe1d48 0x5dc00 0xdbba0>;
  51. operating-points-0-0 = <0x1a5248 0x1343a4 0x155cc0 0x11edd8 0xf4240 0x10c8e0 0xc3500 0x100590 0x927c0 0xf4240 0x5dc00 0xee098>;
  52. clock-names = "cpu";
  53. operating-points-0-4 = <0x1a5248 0x118c30 0x155cc0 0x106738 0xf4240 0xf4240 0xc3500 0xe7ef0 0x927c0 0xdbba0 0x5dc00 0xd59f8>;
  54. #cooling-cells = <0x02>;
  55. operating-points-0-2 = <0x1a5248 0x124f80 0x155cc0 0x112a88 0xf4240 0x100590 0xc3500 0xf4240 0x927c0 0xe7ef0 0x5dc00 0xe1d48>;
  56. voltage-tolerance = <0x05>;
  57. reg = <0x00>;
  58. next-level-cache = <0x02>;
  59. qcom,acc = <0x03>;
  60. qcom,saw = <0x04>;
  61. clock-latency = <0x186a0>;
  62. enable-method = "qcom,kpss-acc-v1";
  63. };
  64.  
  65. cpu@1 {
  66. device_type = "cpu";
  67. operating-points-0-5 = <0x1a5248 0x10c8e0 0x155cc0 0xfa3e8 0xf4240 0xe7ef0 0xc3500 0xdbba0 0x927c0 0xcf850 0x5dc00 0xc96a8>;
  68. cooling-max-state = <0x0a>;
  69. operating-points-0-6 = <0x1a5248 0x100590 0x155cc0 0xee098 0xf4240 0xdbba0 0xc3500 0xcf850 0x927c0 0xc3500 0x5dc00 0xbd358>;
  70. cooling-min-state = <0x00>;
  71. cpu_fab_threshold = <0x3b9aca00>;
  72. compatible = "qcom,krait";
  73. clocks = <0x05 0x01>;
  74. operating-points-0-1 = <0x1a5248 0x12b128 0x155cc0 0x118c30 0xf4240 0x106738 0xc3500 0xfa3e8 0x927c0 0xee098 0x5dc00 0xe7ef0>;
  75. core-supply = <0x0a>;
  76. qcom,imem = <0x07>;
  77. operating-points-0-3 = <0x1a5248 0x11edd8 0x155cc0 0x10c8e0 0xf4240 0xfa3e8 0xc3500 0xee098 0x927c0 0xe1d48 0x5dc00 0xdbba0>;
  78. operating-points-0-0 = <0x1a5248 0x1343a4 0x155cc0 0x11edd8 0xf4240 0x10c8e0 0xc3500 0x100590 0x927c0 0xf4240 0x5dc00 0xee098>;
  79. clock-names = "cpu";
  80. operating-points-0-4 = <0x1a5248 0x118c30 0x155cc0 0x106738 0xf4240 0xf4240 0xc3500 0xe7ef0 0x927c0 0xdbba0 0x5dc00 0xd59f8>;
  81. #cooling-cells = <0x02>;
  82. operating-points-0-2 = <0x1a5248 0x124f80 0x155cc0 0x112a88 0xf4240 0x100590 0xc3500 0xf4240 0x927c0 0xe7ef0 0x5dc00 0xe1d48>;
  83. reg = <0x01>;
  84. next-level-cache = <0x02>;
  85. qcom,acc = <0x08>;
  86. qcom,saw = <0x09>;
  87. clock-latency = <0x186a0>;
  88. enable-method = "qcom,kpss-acc-v1";
  89. };
  90.  
  91. l2-cache {
  92. cache-level = <0x02>;
  93. compatible = "cache";
  94. clocks = <0x05 0x04>;
  95. clock-names = "cache";
  96. vdd_dig-supply = <0x0b>;
  97. phandle = <0x02>;
  98. cache-points-kHz = <0x124f80 0x118c30 0x124f80 0xf4240 0x10c8e0 0x927c0 0x5dc00 0x10c8e0 0x5dc00>;
  99. linux,phandle = <0x02>;
  100. };
  101. };
  102.  
  103. nss-common {
  104. nss_core_vdd_nominal = <0x10c8e0>;
  105. compatible = "qcom,nss-common";
  106. clocks = <0x0c 0x11b 0x0c 0x11a 0x0d 0x0e>;
  107. nss_core_threshold_freq = <0x2bb0b140>;
  108. nss_core_vdd_high = <0x118c30>;
  109. clock-names = "nss-core-clk\0nss-tcm-clk\0nss-fab0-clk\0nss-fab0-clk";
  110. reg = <0x3000000 0x1000>;
  111. nss_core-supply = <0x0f>;
  112. reg-names = "nss_fpb_base";
  113. };
  114.  
  115. chosen {
  116. bootargs-append = " console=ttyMSM0,115200n8";
  117. bootargs = "console=ttyHSL1,115200n8 ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs ubootversion=NUB.2D.12 readFlag=0";
  118. };
  119.  
  120. fab-scaling {
  121. compatible = "qcom,fab-scaling";
  122. clocks = <0x10 0x11>;
  123. fab_freq_high = <0x1fc4ef40>;
  124. clock-names = "apps-fab-clk\0ddr-fab-clk";
  125. fab_freq_nominal = <0x17d78400>;
  126. };
  127.  
  128. reserved-memory {
  129. #size-cells = <0x01>;
  130. ranges;
  131. #address-cells = <0x01>;
  132.  
  133. pstore@5fb00000 {
  134. no-map;
  135. reg = <0x5fb00000 0x100000>;
  136. };
  137.  
  138. rsvd@41200000 {
  139. no-map;
  140. reg = <0x41200000 0x300000>;
  141. };
  142.  
  143. wigig_dump@44400000 {
  144. no-map;
  145. reg = <0x44400000 0x200000>;
  146. };
  147.  
  148. smem@41000000 {
  149. no-map;
  150. reg = <0x41000000 0x200000>;
  151. };
  152.  
  153. wifi_dump@44000000 {
  154. no-map;
  155. reg = <0x44000000 0x600000>;
  156. };
  157.  
  158. nss@40000000 {
  159. no-map;
  160. reg = <0x40000000 0x1000000>;
  161. };
  162. };
  163.  
  164. cpu-pmu {
  165. compatible = "qcom,krait-pmu";
  166. interrupts = <0x01 0x0a 0x304>;
  167. };
  168.  
  169. soc {
  170. compatible = "simple-bus";
  171. #size-cells = <0x01>;
  172. ranges;
  173. #address-cells = <0x01>;
  174.  
  175. gsbi@1a200000 {
  176. compatible = "qcom,gsbi-v1.0.0";
  177. clocks = <0x0c 0x83>;
  178. status = "ok";
  179. #size-cells = <0x01>;
  180. ranges;
  181. qcom,mode = <0x03>;
  182. clock-names = "iface";
  183. reg = <0x1a200000 0x100>;
  184. #address-cells = <0x01>;
  185.  
  186. serial@1a240000 {
  187. compatible = "qcom,msm-uartdm-v1.3\0qcom,msm-uartdm";
  188. interrupts = <0x00 0x9a 0x00>;
  189. clocks = <0x0c 0x9d 0x0c 0x83>;
  190. status = "disabled";
  191. clock-names = "core\0iface";
  192. reg = <0x1a240000 0x1000 0x1a200000 0x1000>;
  193. };
  194.  
  195. i2c@1a280000 {
  196. compatible = "qcom,i2c-qup-v1.1.1";
  197. interrupts = <0x00 0x9b 0x00>;
  198. clocks = <0x0c 0x8f 0x0c 0x83>;
  199. status = "disabled";
  200. #size-cells = <0x00>;
  201. clock-names = "core\0iface";
  202. reg = <0x1a280000 0x1000>;
  203. #address-cells = <0x01>;
  204. };
  205.  
  206. spi@1a280000 {
  207. spi-max-frequency = <0x2faf080>;
  208. compatible = "qcom,spi-qup-v1.1.1";
  209. interrupts = <0x00 0x9b 0x00>;
  210. clocks = <0x0c 0x8f 0x0c 0x83>;
  211. status = "ok";
  212. #size-cells = <0x00>;
  213. dma-names = "rx\0tx";
  214. dmas = <0x1a 0x06 0x09 0x1a 0x05 0x0a>;
  215. clock-names = "core\0iface";
  216. pinctrl-0 = <0x18>;
  217. reg = <0x1a280000 0x1000>;
  218. cs-gpios = <0x19 0x14 0x00>;
  219. #address-cells = <0x01>;
  220. pinctrl-names = "default";
  221.  
  222. m25p80@0 {
  223. m25p,fast-read;
  224. spi-max-frequency = <0x2faf080>;
  225. compatible = "s25fl256s1";
  226. #size-cells = <0x01>;
  227. reg = <0x00>;
  228. #address-cells = <0x01>;
  229.  
  230. partition@1a0000 {
  231. reg = <0x1a0000 0x20000>;
  232. label = "0:RPM";
  233. };
  234.  
  235. partition@2e0000 {
  236. reg = <0x2e0000 0x40000>;
  237. label = "0:ART";
  238. };
  239.  
  240. partition@180000 {
  241. reg = <0x180000 0x10000>;
  242. label = "0:BOOTCONFIG1";
  243. };
  244.  
  245. partition@190000 {
  246. reg = <0x190000 0x10000>;
  247. label = "0:RES1";
  248. };
  249.  
  250. partition@20000 {
  251. reg = <0x20000 0x20000>;
  252. label = "0:MIBIB";
  253. };
  254.  
  255. partition@150000 {
  256. reg = <0x150000 0x30000>;
  257. label = "0:SBL3_1";
  258. };
  259.  
  260. partition@3f0000 {
  261. reg = <0x3f0000 0x10000>;
  262. label = "0:EID-B";
  263. };
  264.  
  265. partition@3e0000 {
  266. reg = <0x3e0000 0x10000>;
  267. label = "0:EID-A";
  268. };
  269.  
  270. partition@330000 {
  271. reg = <0x330000 0x10000>;
  272. label = "0:BOOTCONFIG";
  273. };
  274.  
  275. partition@b0000 {
  276. reg = <0xb0000 0x30000>;
  277. label = "0:SBL2_1";
  278. };
  279.  
  280. partition@2a0000 {
  281. reg = <0x2a0000 0x40000>;
  282. label = "0:APPSBLENV";
  283. };
  284.  
  285. partition@70000 {
  286. reg = <0x70000 0x10000>;
  287. label = "0:DDRCONFIG_1";
  288. };
  289.  
  290. partition@40000 {
  291. reg = <0x40000 0x30000>;
  292. label = "0:SBL2";
  293. };
  294.  
  295. partition@110000 {
  296. reg = <0x110000 0x10000>;
  297. label = "0:SSD";
  298. };
  299.  
  300. partition@1f0000 {
  301. reg = <0x1f0000 0x30000>;
  302. label = "0:RES2";
  303. };
  304.  
  305. partition@360000 {
  306. reg = <0x360000 0x80000>;
  307. label = "0:APPSBL_1";
  308. };
  309.  
  310. partition@340000 {
  311. reg = <0x340000 0x20000>;
  312. label = "0:RES4";
  313. };
  314.  
  315. partition@100000 {
  316. reg = <0x100000 0x10000>;
  317. label = "0:DDRCONFIG";
  318. };
  319.  
  320. partition@120000 {
  321. reg = <0x120000 0x30000>;
  322. label = "0:TZ";
  323. };
  324.  
  325. partition@320000 {
  326. reg = <0x320000 0x10000>;
  327. label = "0:RES3";
  328. };
  329.  
  330. partition@0 {
  331. reg = <0x00 0x20000>;
  332. label = "0:SBL1";
  333. };
  334.  
  335. partition@220000 {
  336. reg = <0x220000 0x80000>;
  337. label = "0:APPSBL";
  338. };
  339.  
  340. partition@80000 {
  341. reg = <0x80000 0x30000>;
  342. label = "0:SBL3";
  343. };
  344.  
  345. partition@1c0000 {
  346. reg = <0x1c0000 0x30000>;
  347. label = "0:TZ_1";
  348. };
  349.  
  350. partition@e0000 {
  351. reg = <0xe0000 0x20000>;
  352. label = "0:RPM_1";
  353. };
  354. };
  355. };
  356. };
  357.  
  358. gsbi@12480000 {
  359. compatible = "qcom,gsbi-v1.0.0";
  360. clocks = <0x0c 0x80>;
  361. status = "ok";
  362. #size-cells = <0x01>;
  363. ranges;
  364. qcom,mode = <0x02>;
  365. clock-names = "iface";
  366. reg = <0x12480000 0x100>;
  367. #address-cells = <0x01>;
  368.  
  369. serial@12490000 {
  370. compatible = "qcom,msm-uartdm-v1.3\0qcom,msm-uartdm";
  371. interrupts = <0x00 0xc3 0x00>;
  372. clocks = <0x0c 0x97 0x0c 0x80>;
  373. status = "disabled";
  374. clock-names = "core\0iface";
  375. reg = <0x12490000 0x1000 0x12480000 0x1000>;
  376. };
  377.  
  378. i2c@124a0000 {
  379. compatible = "qcom,i2c-qup-v1.1.1";
  380. interrupts = <0x00 0xc4 0x00>;
  381. clocks = <0x0c 0x89 0x0c 0x80>;
  382. status = "ok";
  383. #size-cells = <0x00>;
  384. clock-frequency = <0x186a0>;
  385. clock-names = "core\0iface";
  386. pinctrl-0 = <0x17>;
  387. reg = <0x124a0000 0x1000>;
  388. #address-cells = <0x01>;
  389. pinctrl-names = "default";
  390. };
  391.  
  392. hs_uart@12490000 {
  393. compatible = "qcom,msm-hsuart-v13";
  394. interrupts = <0x00 0xc3 0x00>;
  395. clocks = <0x0c 0x97 0x0c 0x80>;
  396. status = "disabled";
  397. clock-names = "core\0iface";
  398. reg = <0x12490000 0x1000 0x12480000 0x1000>;
  399. };
  400. };
  401.  
  402. usb30@0 {
  403. resets = <0x0c 0x67>;
  404. compatible = "qcom,dwc3";
  405. clocks = <0x0c 0x10b>;
  406. status = "ok";
  407. #size-cells = <0x01>;
  408. ranges;
  409. clock-names = "core";
  410. #address-cells = <0x01>;
  411. reset-names = "usb30_mstr_rst";
  412.  
  413. dwc3@11000000 {
  414. dis_u3_susphy_quirk;
  415. compatible = "snps,dwc3";
  416. interrupts = <0x00 0x6e 0x04>;
  417. usb-phy = <0x20 0x21>;
  418. phy-names = "usb2-phy\0usb3-phy";
  419. dr_mode = "host";
  420. tx-fifo-resize;
  421. reg = <0x11000000 0xcd00>;
  422. };
  423. };
  424.  
  425. phy@100f8830 {
  426. tx_deamp_3_5db = <0x20>;
  427. rx_eq = <0x02>;
  428. compatible = "qcom,dwc3-ssphy\0qcom,dwc3-ssphy-ipq8064";
  429. clocks = <0x0c 0x10c>;
  430. status = "ok";
  431. mpll = <0xa0>;
  432. clock-names = "ref";
  433. reg = <0x100f8830 0x30>;
  434. phandle = <0x23>;
  435. linux,phandle = <0x23>;
  436. };
  437.  
  438. clock-controller@2098000 {
  439. clock-output-names = "acpu1_aux";
  440. compatible = "qcom,kpss-acc-v1";
  441. reg = <0x2098000 0x1000 0x2008000 0x1000>;
  442. phandle = <0x08>;
  443. linux,phandle = <0x08>;
  444. };
  445.  
  446. tsens-ipq806x {
  447. qcom,tsens_factor = <0x3e8>;
  448. qcom,slope = <0x498 0x498 0x482 0x498 0x457 0x46c 0x46c 0x4af 0x46c 0x4af 0x46c>;
  449. compatible = "qcom,ipq806x-tsens";
  450. interrupts = <0x00 0xb2 0x00>;
  451. qcom,sensors = <0x0b>;
  452. reg = <0x900000 0x3678 0x700000 0x420>;
  453. reg-names = "tsens_physical\0tsens_eeprom_physical";
  454. };
  455.  
  456. gsbi@12440000 {
  457. compatible = "qcom,gsbi-v1.0.0";
  458. clocks = <0x0c 0x7f>;
  459. status = "ok";
  460. #size-cells = <0x01>;
  461. ranges;
  462. qcom,mode = <0x02>;
  463. clock-names = "iface";
  464. reg = <0x12440000 0x1000>;
  465. #address-cells = <0x01>;
  466.  
  467. i2c@12460000 {
  468. compatible = "qcom,i2c-qup-v1.1.1";
  469. interrupts = <0x00 0xc2 0x00>;
  470. clocks = <0x0c 0x87 0x0c 0x7f>;
  471. status = "disabled";
  472. #size-cells = <0x00>;
  473. clock-names = "core\0iface";
  474. pinctrl-0 = <0x16>;
  475. reg = <0x12460000 0x1000>;
  476. #address-cells = <0x01>;
  477. pinctrl-names = "default";
  478. };
  479. };
  480.  
  481. timer@200a000 {
  482. compatible = "qcom,kpss-timer\0qcom,msm-timer";
  483. interrupts = <0x01 0x01 0x301 0x01 0x02 0x301 0x01 0x03 0x301>;
  484. cpu-offset = <0x80000>;
  485. clock-frequency = <0x17d7840 0x8000>;
  486. reg = <0x200a000 0x100>;
  487. };
  488.  
  489. phy@110f8800 {
  490. compatible = "qcom,dwc3-hsphy\0qcom,dwc3-hsphy-ipq8064";
  491. clocks = <0x0c 0x108>;
  492. status = "ok";
  493. clock-names = "utmi";
  494. reg = <0x110f8800 0x30>;
  495. phandle = <0x20>;
  496. linux,phandle = <0x20>;
  497. };
  498.  
  499. rpm@108000 {
  500. qcom,ipc = <0x12 0x08 0x02>;
  501. compatible = "qcom,rpm-ipq8064";
  502. interrupts = <0x00 0x13 0x00 0x00 0x15 0x00 0x00 0x16 0x00>;
  503. #size-cells = <0x00>;
  504. interrupt-names = "ack\0err\0wakeup";
  505. reg = <0x108000 0x1000>;
  506. #address-cells = <0x01>;
  507.  
  508. pxo-clk {
  509. compatible = "qcom,rpm-clk";
  510. qcom,rpm-clk-name = "pxo";
  511. #clock-cells = <0x00>;
  512. reg = <0x7b>;
  513. qcom,rpm-clk-freq = <0x17d7840>;
  514. qcom,rpm-clk-active-only;
  515. };
  516.  
  517. apps-fabric-clk {
  518. compatible = "qcom,rpm-clk";
  519. qcom,rpm-clk-name = "apps-fabric";
  520. #clock-cells = <0x00>;
  521. reg = <0x02>;
  522. phandle = <0x10>;
  523. qcom,rpm-clk-freq = <0x1fc4ef40>;
  524. linux,phandle = <0x10>;
  525. qcom,rpm-clk-active-only;
  526. };
  527.  
  528. nss-fabric1-clk {
  529. compatible = "qcom,rpm-clk";
  530. qcom,rpm-clk-name = "nss-fabric1";
  531. #clock-cells = <0x00>;
  532. reg = <0x87>;
  533. phandle = <0x0e>;
  534. qcom,rpm-clk-freq = <0xfe277a0>;
  535. linux,phandle = <0x0e>;
  536. qcom,rpm-clk-active-only;
  537. };
  538.  
  539. smb208-s2a {
  540. qcom,switch-mode-frequency = <0x124f80>;
  541. compatible = "qcom,rpm-smb208";
  542. regulator-max-microvolt = <0x137478>;
  543. reg = <0x8a>;
  544. phandle = <0x06>;
  545. regulator-min-microvolt = <0xc3500>;
  546. linux,phandle = <0x06>;
  547. };
  548.  
  549. ebi1-clk {
  550. compatible = "qcom,rpm-clk";
  551. qcom,rpm-clk-name = "ebi1";
  552. #clock-cells = <0x00>;
  553. reg = <0x0c>;
  554. phandle = <0x11>;
  555. qcom,rpm-clk-freq = <0x1fc4ef40>;
  556. linux,phandle = <0x11>;
  557. qcom,rpm-clk-active-only;
  558. };
  559.  
  560. smb208-s1b {
  561. qcom,switch-mode-frequency = <0x124f80>;
  562. compatible = "qcom,rpm-smb208";
  563. regulator-max-microvolt = <0x118c30>;
  564. reg = <0x89>;
  565. phandle = <0x0f>;
  566. regulator-min-microvolt = <0x100590>;
  567. linux,phandle = <0x0f>;
  568. };
  569.  
  570. nss-fabric0-clk {
  571. compatible = "qcom,rpm-clk";
  572. qcom,rpm-clk-name = "nss-fabric0";
  573. #clock-cells = <0x00>;
  574. reg = <0x86>;
  575. phandle = <0x0d>;
  576. qcom,rpm-clk-freq = <0x1fc4ef40>;
  577. linux,phandle = <0x0d>;
  578. qcom,rpm-clk-active-only;
  579. };
  580.  
  581. smb208-s2b {
  582. qcom,switch-mode-frequency = <0x124f80>;
  583. compatible = "qcom,rpm-smb208";
  584. regulator-max-microvolt = <0x137478>;
  585. reg = <0x8b>;
  586. phandle = <0x0a>;
  587. regulator-min-microvolt = <0xc3500>;
  588. linux,phandle = <0x0a>;
  589. };
  590.  
  591. smb208-s1a {
  592. qcom,switch-mode-frequency = <0x124f80>;
  593. compatible = "qcom,rpm-smb208";
  594. regulator-max-microvolt = <0x118c30>;
  595. reg = <0x88>;
  596. phandle = <0x0b>;
  597. regulator-min-microvolt = <0x100590>;
  598. linux,phandle = <0x0b>;
  599. };
  600.  
  601. cxo-clk {
  602. compatible = "qcom,rpm-clk";
  603. qcom,rpm-clk-name = "cxo";
  604. #clock-cells = <0x00>;
  605. reg = <0x09>;
  606. qcom,rpm-clk-freq = <0x17d7840>;
  607. qcom,rpm-clk-active-only;
  608. };
  609. };
  610.  
  611. amba {
  612. compatible = "arm,amba-bus";
  613. #size-cells = <0x01>;
  614. ranges;
  615. #address-cells = <0x01>;
  616.  
  617. sdcc@12180000 {
  618. cap-mmc-highspeed;
  619. vqmmc-supply = <0x24>;
  620. compatible = "arm,pl18x\0arm,primecell";
  621. interrupts = <0x00 0x66 0x04>;
  622. clocks = <0x0c 0x6b 0x0c 0x64>;
  623. status = "disabled";
  624. dma-names = "tx\0rx";
  625. dmas = <0x26 0x02 0x26 0x01>;
  626. sd-uhs-sdr104;
  627. clock-names = "mclk\0apb_pclk";
  628. cap-sd-highspeed;
  629. interrupt-names = "cmd_irq";
  630. #mmc-ddr-1_8v;
  631. reg = <0x12180000 0x2000>;
  632. bus-width = <0x08>;
  633. arm,primecell-periphid = <0x51180>;
  634. max-frequency = <0xb71b000>;
  635. sd-uhs-ddr50;
  636. };
  637.  
  638. sdcc@12400000 {
  639. cap-mmc-highspeed;
  640. vmmc-supply = <0x24>;
  641. mmc-ddr-1_8v;
  642. compatible = "arm,pl18x\0arm,primecell";
  643. interrupts = <0x00 0x68 0x04>;
  644. clocks = <0x0c 0x67 0x0c 0x62>;
  645. status = "disabled";
  646. dma-names = "tx\0rx";
  647. dmas = <0x25 0x02 0x25 0x01>;
  648. clock-names = "mclk\0apb_pclk";
  649. cap-sd-highspeed;
  650. interrupt-names = "cmd_irq";
  651. reg = <0x12400000 0x2000>;
  652. bus-width = <0x08>;
  653. arm,primecell-periphid = <0x51180>;
  654. max-frequency = <0x5b8d800>;
  655. non-removable;
  656. };
  657. };
  658.  
  659. qcom,restart_reason {
  660. compatible = "qcom,restart_reason";
  661. };
  662.  
  663. qcom,ssbi@500000 {
  664. compatible = "qcom,ssbi";
  665. qcom,controller-type = "pmic-arbiter";
  666. reg = <0x500000 0x1000>;
  667. };
  668.  
  669. phy@110f8830 {
  670. tx_deamp_3_5db = <0x20>;
  671. rx_eq = <0x02>;
  672. compatible = "qcom,dwc3-ssphy\0qcom,dwc3-ssphy-ipq8064";
  673. clocks = <0x0c 0x10b>;
  674. status = "ok";
  675. mpll = <0xa0>;
  676. clock-names = "ref";
  677. reg = <0x110f8830 0x30>;
  678. phandle = <0x21>;
  679. linux,phandle = <0x21>;
  680. };
  681.  
  682. rng@1a500000 {
  683. compatible = "qcom,prng";
  684. clocks = <0x0c 0xd2>;
  685. clock-names = "core";
  686. reg = <0x1a500000 0x200>;
  687. };
  688.  
  689. nss-gmac-common {
  690. compatible = "qcom,nss-gmac-common";
  691. reg = <0x3000000 0xffff 0x1bb00000 0xffff 0x900000 0x4000>;
  692. reg-names = "nss_reg_base\0qsgmii_reg_base\0clk_ctl_base";
  693. };
  694.  
  695. interrupt-controller@2000000 {
  696. compatible = "qcom,msm-qgic2";
  697. #interrupt-cells = <0x03>;
  698. interrupt-controller;
  699. reg = <0x2000000 0x1000 0x2002000 0x1000>;
  700. phandle = <0x01>;
  701. linux,phandle = <0x01>;
  702. };
  703.  
  704. phy@100f8800 {
  705. compatible = "qcom,dwc3-hsphy\0qcom,dwc3-hsphy-ipq8064";
  706. clocks = <0x0c 0x109>;
  707. status = "ok";
  708. clock-names = "utmi";
  709. reg = <0x100f8800 0x30>;
  710. phandle = <0x22>;
  711. linux,phandle = <0x22>;
  712. };
  713.  
  714. tcsr@1a400000 {
  715. compatible = "qcom,tcsr";
  716. status = "ok";
  717. reg = <0x1a400000 0x100>;
  718. };
  719.  
  720. clock-controller@900000 {
  721. #reset-cells = <0x01>;
  722. compatible = "qcom,gcc-ipq8064";
  723. #clock-cells = <0x01>;
  724. reg = <0x900000 0x4000>;
  725. phandle = <0x0c>;
  726. linux,phandle = <0x0c>;
  727. };
  728.  
  729. crypto@38000000 {
  730. resets = <0x0c 0x9d 0x0c 0xa1>;
  731. compatible = "qcom,nss-crypto";
  732. clocks = <0x0c 0xed 0x0c 0xeb 0x0c 0xec>;
  733. clock-names = "ce5_core\0ce5_aclk\0ce5_hclk";
  734. qcom,ee = <0x00>;
  735. reg = <0x38000000 0x20000 0x38004000 0x22000>;
  736. reg-names = "crypto_pbase\0bam_base";
  737. reset-names = "rst_eng\0rst_ahb";
  738. };
  739.  
  740. rpm_log@10c0c8 {
  741. rpm_log_len = <0x1800>;
  742. compatible = "qcom,rpm_log";
  743. reg = <0x10c0c8 0x2000>;
  744. reg-names = "rpm_log_base_addr";
  745. reg-offsets = <0x80 0xa0>;
  746. };
  747.  
  748. crypto@38400000 {
  749. resets = <0x0c 0x9e>;
  750. compatible = "qcom,nss-crypto";
  751. qcom,ee = <0x00>;
  752. reg = <0x38400000 0x20000 0x38404000 0x22000>;
  753. reg-names = "crypto_pbase\0bam_base";
  754. reset-names = "rst_eng";
  755. };
  756.  
  757. memory@700000 {
  758. compatible = "qcom,imem-ipq8064\0syscon";
  759. #size-cells = <0x01>;
  760. ranges = <0x00 0x700000 0x1000>;
  761. reg = <0x700000 0x1000>;
  762. phandle = <0x07>;
  763. #address-cells = <0x01>;
  764. linux,phandle = <0x07>;
  765. };
  766.  
  767. nss@40800000 {
  768. qcom,crypto-enabled;
  769. qcom,ipsec-enabled;
  770. resets = <0x0c 0x77 0x0c 0x78 0x0c 0x79 0x0c 0x7a>;
  771. qcom,turbo-frequency;
  772. qcom,max-frequency = <0x2faf0800>;
  773. compatible = "qcom,nss";
  774. interrupts = <0x00 0xd6 0x04 0x00 0xe9 0x04>;
  775. qcom,mid-frequency = <0x23c34600>;
  776. qcom,load-addr = <0x40800000>;
  777. qcom,id = <0x01>;
  778. qcom,num-irq = <0x02>;
  779. qcom,capwap-enabled;
  780. qcom,dtls-enabled;
  781. reg = <0x36400000 0x1000 0x39010000 0x10000>;
  782. qcom,low-frequency = <0x68e7780>;
  783. reg-names = "nphys\0vphys";
  784. reset-names = "clkrst-clamp\0clamp\0ahb\0axi";
  785. };
  786.  
  787. pci@1b500000 { //pcie0
  788. device_type = "pci";
  789. resets = <0x0c 0x1b
  790. 0x0c 0x1a
  791. 0x0c 0x19
  792. 0x0c 0x18
  793. 0x0c 0x17
  794. 0x0c 0x16>;
  795. compatible = "qcom,pcie-ipq8064-v2";
  796. interrupts = <0x00 0x23 0x00 0x00 0x24 0x00 0x00 0x25 0x00 0x00 0x26 0x00 0x00 0x27 0x00>;
  797. clocks = <0x0c 0x29
  798. 0x0c 0x2b
  799. 0x0c 0x2c
  800. 0x0c 0xf7
  801. 0x0c 0xf8
  802. 0x0c 0x2a>;
  803. status = "ok";
  804. #size-cells = <0x02>;
  805. ranges = <0x00 0x00 0x00 0xff00000 0x00 0x100000 0x81000000 0x00 0x00 0xfe00000 0x00 0x100000 0x82000000 0x00 0x00 0x8000000 0x00 0x7e00000>;
  806. clock-names = "core\0iface\0phy\0alt_src\0alt_clk\0aux";
  807. pinctrl-0 = <0x1c>;
  808. reset-gpio = <0x19 0x03 0x00>;
  809. reg = <0x1b500000 0x1000
  810. 0x1b502000 0x80
  811. 0x1b600000 0x100>;
  812. reg-names = "base\0elbi\0parf";
  813. #address-cells = <0x03>;
  814. reset-names = "axi\0ahb\0por\0pci\0phy\0ext";
  815. force_gen1 = <0x00>;
  816. pinctrl-names = "default";
  817.  
  818. pcie@0 {
  819. device_type = "pci";
  820. #size-cells = <0x02>;
  821. #interrupt-cells = <0x01>;
  822. reg = <0x00 0x00 0x00 0x00 0x00>;
  823. #address-cells = <0x03>;
  824.  
  825. ath10k@0,0 {
  826. device_type = "pci";
  827. qcom,cal-len = <0x2f20>;
  828. reg = <0x00 0x00 0x00 0x00 0x00>;
  829. qcom,mtd-name = "0:ART";
  830. qcom,cal-offset = <0x1000>;
  831. };
  832. };
  833. };
  834.  
  835. pci@1b700000 {
  836. device_type = "pci";
  837. resets = <0x0c 0x5b
  838. 0x0c 0x5a
  839. 0x0c 0x59
  840. 0x0c 0x58
  841. 0x0c 0x57
  842. 0x0c 0x56>;
  843. compatible = "qcom,pcie-ipq8064-v2";
  844. interrupts = <0x00 0x39 0x00 0x00 0x3a 0x00 0x00 0x3b 0x00 0x00 0x3c 0x00 0x00 0x3d 0x00>;
  845. clocks = <0x0c 0xf9 0x0c 0xfb 0x0c 0xfc 0x0c 0xfd 0x0c 0xfe 0x0c 0xfa>;
  846. status = "ok";
  847. #size-cells = <0x02>;
  848. ranges = <0x00 0x00 0x00 0x31f00000 0x00 0x100000 0x81000000 0x00 0x00 0x31e00000 0x00 0x100000 0x82000000 0x00 0x00 0x2e000000 0x00 0x3e00000>;
  849. clock-names = "core\0iface\0phy\0alt_src\0alt_clk\0aux";
  850. pinctrl-0 = <0x1d>;
  851. reset-gpio = <0x19 0x30 0x00>;
  852. reg = <0x1b700000 0x1000
  853. 0x1b702000 0x80
  854. 0x1b800000 0x100>;
  855. reg-names = "base\0elbi\0parf";
  856. #address-cells = <0x03>;
  857. reset-names = "axi\0ahb\0por\0pci\0phy\0ext";
  858. force_gen1 = <0x00>;
  859. pinctrl-names = "default";
  860.  
  861. pcie@0 {
  862. device_type = "pci";
  863. #size-cells = <0x02>;
  864. #interrupt-cells = <0x01>;
  865. reg = <0x00 0x00 0x00 0x00 0x00>;
  866. #address-cells = <0x03>;
  867.  
  868. ath10k@0,0 {
  869. device_type = "pci";
  870. qcom,cal-len = <0x2f20>;
  871. reg = <0x00 0x00 0x00 0x00 0x00>;
  872. qcom,mtd-name = "0:ART";
  873. qcom,cal-offset = <0x5000>;
  874. };
  875. };
  876. };
  877.  
  878. pci@1b900000 {
  879. device_type = "pci";
  880. resets = <0x0c 0x63 0x0c 0x62 0x0c 0x61 0x0c 0x60 0x0c 0x5f 0x0c 0x5e>;
  881. compatible = "qcom,pcie-ipq8064-v2";
  882. interrupts = <0x00 0x47 0x00 0x00 0x48 0x00 0x00 0x49 0x00 0x00 0x4a 0x00 0x00 0x4b 0x00>;
  883. clocks = <0x0c 0xff 0x0c 0x101 0x0c 0x102 0x0c 0x103 0x0c 0x104 0x0c 0x100>;
  884. status = "ok";
  885. #size-cells = <0x02>;
  886. ranges = <0x00 0x00 0x00 0x35f00000 0x00 0x100000 0x81000000 0x00 0x00 0x35e00000 0x00 0x100000 0x82000000 0x00 0x00 0x32000000 0x00 0x3e00000>;
  887. clock-names = "core\0iface\0phy\0alt_src\0alt_clk\0aux";
  888. pinctrl-0 = <0x1e>;
  889. reset-gpio = <0x19 0x3f 0x00>;
  890. reg = <0x1b900000 0x1000
  891. 0x1b902000 0x80
  892. 0x1ba00000 0x100>;
  893. reg-names = "base\0elbi\0parf";
  894. #address-cells = <0x03>;
  895. reset-names = "axi\0ahb\0por\0pci\0phy\0ext";
  896. force_gen1 = <0x00>;
  897. pinctrl-names = "default";
  898.  
  899. pcie@0 {
  900. device_type = "pci";
  901. #size-cells = <0x02>;
  902. #interrupt-cells = <0x01>;
  903. reg = <0x00 0x00 0x00 0x00 0x00>;
  904. #address-cells = <0x03>;
  905.  
  906. ath10k@0,0 {
  907. device_type = "pci";
  908. qcom,cal-len = <0x844>;
  909. reg = <0x00 0x00 0x00 0x00 0x00>;
  910. qcom,mtd-name = "0:ART";
  911. qcom,cal-offset = <0x9000>;
  912. };
  913. };
  914. };
  915.  
  916. pinmux@800000 {
  917. #gpio-cells = <0x02>;
  918. compatible = "qcom,ipq8064-pinctrl";
  919. interrupts = <0x00 0x10 0x04>;
  920. #interrupt-cells = <0x02>;
  921. pinctrl-0 = <0x13 0x14>;
  922. interrupt-controller;
  923. reg = <0x800000 0x4000>;
  924. phandle = <0x19>;
  925. linux,phandle = <0x19>;
  926. pinctrl-names = "default";
  927. gpio-controller;
  928.  
  929. hs_uart_pins {
  930. };
  931.  
  932. nand_pins {
  933. phandle = <0x1f>;
  934. linux,phandle = <0x1f>;
  935.  
  936. hold {
  937. bias-bus-hold;
  938. pins = "gpio40\0gpio41\0gpio42\0gpio43\0gpio44\0gpio45\0gpio46\0gpio47";
  939. };
  940.  
  941. mux {
  942. bias-disable;
  943. drive-strength = <0x0a>;
  944. pins = "gpio34\0gpio35\0gpio36\0gpio37\0gpio38\0gpio39\0gpio40\0gpio41\0gpio42\0gpio43\0gpio44\0gpio45\0gpio46\0gpio47";
  945. function = "nand";
  946. };
  947.  
  948. pullups {
  949. pins = "gpio39";
  950. bias-pull-up;
  951. };
  952. };
  953.  
  954. pcie1_pinmux {
  955. phandle = <0x1c>;
  956. linux,phandle = <0x1c>;
  957.  
  958. mux {
  959. bias-disable;
  960. drive-strength = <0x02>;
  961. pins = "gpio3";
  962. };
  963. };
  964.  
  965.  
  966. pcie2_pinmux {
  967. phandle = <0x1d>;
  968. linux,phandle = <0x1d>;
  969.  
  970. mux {
  971. bias-disable;
  972. drive-strength = <0x02>;
  973. pins = "gpio48";
  974. };
  975. };
  976.  
  977.  
  978. pcie3_pinmux {
  979. phandle = <0x1e>;
  980. linux,phandle = <0x1e>;
  981.  
  982. mux {
  983. bias-disable;
  984. drive-strength = <0x02>;
  985. pins = "gpio63";
  986. };
  987. };
  988.  
  989. rgmii2_pins_default {
  990. phandle = <0x13>;
  991. linux,phandle = <0x13>;
  992.  
  993. mux {
  994. bias-disable;
  995. drive-strength = <0x06>;
  996. pins = "gpio27\0gpio28\0gpio29\0gpio30\0gpio31\0gpio32\0gpio51\0gpio52\0gpio59\0gpio60\0gpio61\0gpio62";
  997. function = "rgmii2";
  998. };
  999. };
  1000.  
  1001. phy_rst_pins {
  1002.  
  1003. mux {
  1004. drive-strength = <0x0c>;
  1005. pins = "gpio8";
  1006. bias-pull-down;
  1007. function = "gpio";
  1008. output-low;
  1009. };
  1010. };
  1011.  
  1012. temp_pins {
  1013. phandle = <0x17>;
  1014. linux,phandle = <0x17>;
  1015.  
  1016. mux {
  1017. bias-disable;
  1018. drive-strength = <0x0c>;
  1019. pins = "gpio24\0gpio25";
  1020. function = "gsbi2";
  1021. };
  1022. };
  1023.  
  1024. spi_pins {
  1025. phandle = <0x18>;
  1026. linux,phandle = <0x18>;
  1027.  
  1028. mux {
  1029. drive-strength = <0x0a>;
  1030. pins = "gpio18\0gpio19\0gpio21";
  1031. function = "gsbi5";
  1032. bias-none;
  1033. };
  1034.  
  1035. cs {
  1036. drive-strength = <0x0c>;
  1037. pins = "gpio20";
  1038. };
  1039. };
  1040.  
  1041. i2c_pins {
  1042. phandle = <0x16>;
  1043. linux,phandle = <0x16>;
  1044. };
  1045.  
  1046. leds_pins {
  1047. phandle = <0x14>;
  1048. linux,phandle = <0x14>;
  1049.  
  1050. mux {
  1051. drive-strength = <0x02>;
  1052. pins = "gpio26\0gpio2\0gpio22\0gpio68\0gpio23\0gpio67\0gpio56\0gpio55\0gpio54\0gpio53\0gpio64\0gpio65";
  1053. bias-pull-down;
  1054. function = "gpio";
  1055. output-low;
  1056. };
  1057. };
  1058. };
  1059.  
  1060. sata-phy@1b400000 {
  1061. rx_eq = <0x04>;
  1062. tx_preemph_gen3 = <0x15>;
  1063. compatible = "qcom,ipq806x-sata-phy";
  1064. clocks = <0x0c 0xbb>;
  1065. status = "ok";
  1066. mpll = <0xa0>;
  1067. clock-names = "cfg";
  1068. reg = <0x1b400000 0x200>;
  1069. phandle = <0x1b>;
  1070. #phy-cells = <0x00>;
  1071. linux,phandle = <0x1b>;
  1072. term_off = <0x07>;
  1073. };
  1074.  
  1075. clock-controller@2088000 {
  1076. clock-output-names = "acpu0_aux";
  1077. compatible = "qcom,kpss-acc-v1";
  1078. reg = <0x2088000 0x1000 0x2008000 0x1000>;
  1079. phandle = <0x03>;
  1080. linux,phandle = <0x03>;
  1081. };
  1082.  
  1083. gpio_keys {
  1084. compatible = "gpio-keys";
  1085.  
  1086. button@1 {
  1087. gpios = <0x19 0x0f 0x01>;
  1088. debounce-interval = <0x3c>;
  1089. linux,code = <0x198>;
  1090. linux,input-type = <0x01>;
  1091. label = "reset";
  1092. };
  1093. };
  1094.  
  1095. qcom,msm-imem@2A03F000 {
  1096. compatible = "qcom,msm-imem";
  1097. #size-cells = <0x01>;
  1098. ranges = <0x00 0x2a03f000 0x1000>;
  1099. reg = <0x2a03f000 0x1000>;
  1100. #address-cells = <0x01>;
  1101.  
  1102. l2_dump_offset@14 {
  1103. compatible = "qcom,msm-imem-l2_dump_offset";
  1104. reg = <0x14 0x08>;
  1105. };
  1106.  
  1107. download_mode@0 {
  1108. compatible = "qcom,msm-imem-download_mode";
  1109. reg = <0x00 0x08>;
  1110. };
  1111.  
  1112. restart_reason@65c {
  1113. compatible = "qcom,msm-imem-restart_reason";
  1114. reg = <0x65c 0x04>;
  1115. };
  1116. };
  1117.  
  1118. mdio {
  1119. gpios = <0x19 0x01 0x00 0x19 0x00 0x00>;
  1120. compatible = "virtual,mdio-gpio";
  1121. #size-cells = <0x00>;
  1122. phandle = <0x27>;
  1123. #address-cells = <0x01>;
  1124. linux,phandle = <0x27>;
  1125.  
  1126. ethernet-phy@0 {
  1127. device_type = "ethernet-phy";
  1128. qca,ar8327-initvals = <0x04 0x7600000
  1129. 0x08 0x1000000
  1130. 0x0c 0x20080
  1131. 0xe4 0x6a545
  1132. 0xe0 0xc74164de
  1133. 0x7c 0x4e
  1134. 0x94 0x4e>;
  1135. reg = <0x00>;
  1136. };
  1137.  
  1138. ethernet-phy@1 {
  1139. device_type = "ethernet-phy";
  1140. reg = <0x01>;
  1141. };
  1142. };
  1143.  
  1144. sata@29000000 {
  1145. phys = <0x1b>;
  1146. compatible = "qcom,ipq806x-ahci";
  1147. interrupts = <0x00 0xd1 0x00>;
  1148. clocks = <0x0c 0x32 0x0c 0xb5 0x0c 0xba 0x0c 0xb6 0x0c 0xb7 0x0c 0xb8>;
  1149. status = "ok";
  1150. assigned-clocks = <0x0c 0xb7 0x0c 0xb8>;
  1151. phy-names = "sata-phy";
  1152. clock-names = "slave_face\0iface\0core\0src\0rxoob\0pmalive";
  1153. portmap = <0x01>;
  1154. reg = <0x29000000 0x180>;
  1155. assigned-clock-rates = <0x5f5e100 0x5f5e100>;
  1156. };
  1157.  
  1158. regulator@2099000 {
  1159. compatible = "qcom,saw2";
  1160. regulator;
  1161. reg = <0x2099000 0x1000 0x2009000 0x1000>;
  1162. phandle = <0x09>;
  1163. linux,phandle = <0x09>;
  1164. };
  1165.  
  1166. gsbi@16300000 {
  1167. compatible = "qcom,gsbi-v1.0.0";
  1168. clocks = <0x0c 0x82>;
  1169. status = "ok";
  1170. #size-cells = <0x01>;
  1171. ranges;
  1172. qcom,mode = <0x06>;
  1173. clock-names = "iface";
  1174. reg = <0x16300000 0x100>;
  1175. #address-cells = <0x01>;
  1176.  
  1177. serial@16340000 {
  1178. compatible = "qcom,msm-uartdm-v1.3\0qcom,msm-uartdm";
  1179. interrupts = <0x00 0x98 0x00>;
  1180. clocks = <0x0c 0x9b 0x0c 0x82>;
  1181. status = "ok";
  1182. clock-names = "core\0iface";
  1183. reg = <0x16340000 0x1000 0x16300000 0x1000>;
  1184. };
  1185.  
  1186. i2c@16380000 {
  1187. compatible = "qcom,i2c-qup-v1.1.1";
  1188. interrupts = <0x00 0x99 0x00>;
  1189. clocks = <0x0c 0x8d 0x0c 0x82>;
  1190. status = "disabled";
  1191. #size-cells = <0x00>;
  1192. clock-names = "core\0iface";
  1193. reg = <0x16380000 0x1000>;
  1194. #address-cells = <0x01>;
  1195. };
  1196. };
  1197.  
  1198. crypto@38C00000 {
  1199. resets = <0x0c 0xa0>;
  1200. compatible = "qcom,nss-crypto";
  1201. qcom,ee = <0x00>;
  1202. reg = <0x38c00000 0x20000 0x38c04000 0x22000>;
  1203. reg-names = "crypto_pbase\0bam_base";
  1204. reset-names = "rst_eng";
  1205. };
  1206.  
  1207. nand@0x1ac00000 {
  1208. compatible = "qcom,qcom_nand";
  1209. clocks = <0x0c 0x105>;
  1210. status = "ok";
  1211. #size-cells = <0x01>;
  1212. clock-names = "core_clk";
  1213. pinctrl-0 = <0x1f>;
  1214. reg = <0x1ac00000 0x800>;
  1215. #address-cells = <0x01>;
  1216. pinctrl-names = "default";
  1217.  
  1218. partition@8000000 {
  1219. reg = <0x8000000 0x8000000>;
  1220. label = "cfg";
  1221. };
  1222.  
  1223. partition@0 {
  1224. reg = <0x00 0x4000000>;
  1225. label = "rootfs";
  1226. };
  1227.  
  1228. partition@4000000 {
  1229. reg = <0x4000000 0x4000000>;
  1230. label = "rootfs_1";
  1231. };
  1232. };
  1233.  
  1234. crypto@38800000 {
  1235. resets = <0x0c 0x9f>;
  1236. compatible = "qcom,nss-crypto";
  1237. qcom,ee = <0x00>;
  1238. reg = <0x38800000 0x20000 0x38804000 0x22000>;
  1239. reg-names = "crypto_pbase\0bam_base";
  1240. reset-names = "rst_eng";
  1241. };
  1242.  
  1243. qcom,msm-thermal {
  1244. qcom,sensor-id = <0x00>;
  1245. qcom,core-control-mask = <0x0e>;
  1246. compatible = "qcom,msm-thermal";
  1247. qcom,freq-step = <0x02>;
  1248. qcom,limit-temp = <0x69>;
  1249. qcom,temp-hysteresis = <0x0a>;
  1250. qcom,core-limit-temp = <0x73>;
  1251. qcom,poll-ms = <0xfa>;
  1252. qcom,core-temp-hysteresis = <0x0a>;
  1253. };
  1254.  
  1255. regulator@2089000 {
  1256. compatible = "qcom,saw2";
  1257. regulator;
  1258. reg = <0x2089000 0x1000 0x2009000 0x1000>;
  1259. phandle = <0x04>;
  1260. linux,phandle = <0x04>;
  1261. };
  1262.  
  1263. dma@18300000 {
  1264. resets = <0x0c 0x0d 0x0c 0x0c 0x0c 0x0b 0x0c 0x0a 0x0c 0x09>;
  1265. #dma-cells = <0x02>;
  1266. compatible = "qcom,adm";
  1267. interrupts = <0x00 0xaa 0x00>;
  1268. clocks = <0x0c 0x25 0x0c 0x26>;
  1269. status = "ok";
  1270. clock-names = "core\0iface";
  1271. qcom,ee = <0x00>;
  1272. reg = <0x18300000 0x100000>;
  1273. phandle = <0x1a>;
  1274. linux,phandle = <0x1a>;
  1275. reset-names = "clk\0pbus\0c0\0c1\0c2";
  1276. };
  1277.  
  1278. usb30@1 {
  1279. compatible = "qcom,dwc3";
  1280. clocks = <0x0c 0x10c>;
  1281. status = "ok";
  1282. #size-cells = <0x01>;
  1283. ranges;
  1284. clock-names = "core";
  1285. #address-cells = <0x01>;
  1286.  
  1287. dwc3@10000000 {
  1288. dis_u3_susphy_quirk;
  1289. compatible = "snps,dwc3";
  1290. interrupts = <0x00 0xcd 0x04>;
  1291. usb-phy = <0x22 0x23>;
  1292. phy-names = "usb2-phy\0usb3-phy";
  1293. dr_mode = "host";
  1294. tx-fifo-resize;
  1295. reg = <0x10000000 0xcd00>;
  1296. };
  1297. };
  1298.  
  1299. vsdcc-regulator {
  1300. regulator-name = "SDCC Power";
  1301. compatible = "regulator-fixed";
  1302. regulator-max-microvolt = <0x325aa0>;
  1303. phandle = <0x24>;
  1304. regulator-min-microvolt = <0x325aa0>;
  1305. regulator-always-on;
  1306. linux,phandle = <0x24>;
  1307. };
  1308.  
  1309. clock-controller@2011000 {
  1310. clock-output-names = "acpu_l2_aux";
  1311. compatible = "qcom,kpss-gcc\0syscon";
  1312. reg = <0x2011000 0x1000>;
  1313. phandle = <0x12>;
  1314. linux,phandle = <0x12>;
  1315. };
  1316.  
  1317. ethernet@37000000 {
  1318. device_type = "network";
  1319. local-mac-address = [00 03 7f ba db 00];
  1320. qcom,phy-mdio-addr = <0x01>;
  1321. qcom,rgmii-delay = <0x01>;
  1322. compatible = "qcom,nss-gmac";
  1323. interrupts = <0x00 0xdc 0x04>;
  1324. qcom,pcs-chanid = <0x00>;
  1325. qcom,emulation = <0x00>;
  1326. qcom,id = <0x00>;
  1327. phy-mode = "rgmii";
  1328. qcom,socver = <0x00>;
  1329. qcom,forced-duplex = <0xff>;
  1330. reg = <0x37000000 0x200000>;
  1331. qcom,forced-speed = <0x00>;
  1332. qcom,poll-required = <0x01>;
  1333. mdiobus = <0x27>;
  1334. };
  1335.  
  1336. ethernet@37200000 {
  1337. device_type = "network";
  1338. local-mac-address = [00 03 7f ba db 01];
  1339. qcom,phy-mdio-addr = <0x00>;
  1340. qcom,rgmii-delay = <0x01>;
  1341. compatible = "qcom,nss-gmac";
  1342. interrupts = <0x00 0xdf 0x04>;
  1343. qcom,pcs-chanid = <0x01>;
  1344. qcom,emulation = <0x00>;
  1345. qcom,id = <0x01>;
  1346. phy-mode = "rgmii";
  1347. qcom,socver = <0x00>;
  1348. qcom,forced-duplex = <0xff>;
  1349. reg = <0x37200000 0x200000>;
  1350. qcom,forced-speed = <0x00>;
  1351. qcom,poll-required = <0x01>;
  1352. mdiobus = <0x27>;
  1353. };
  1354.  
  1355. dma@12182000 {
  1356. #dma-cells = <0x01>;
  1357. compatible = "qcom,bam-v1.3.0";
  1358. interrupts = <0x00 0x60 0x00>;
  1359. clocks = <0x0c 0x64>;
  1360. clock-names = "bam_clk";
  1361. qcom,ee = <0x00>;
  1362. reg = <0x12182000 0x8000>;
  1363. phandle = <0x26>;
  1364. linux,phandle = <0x26>;
  1365. };
  1366.  
  1367. dma@12402000 {
  1368. #dma-cells = <0x01>;
  1369. compatible = "qcom,bam-v1.3.0";
  1370. interrupts = <0x00 0x62 0x00>;
  1371. clocks = <0x0c 0x62>;
  1372. clock-names = "bam_clk";
  1373. qcom,ee = <0x00>;
  1374. reg = <0x12402000 0x8000>;
  1375. phandle = <0x25>;
  1376. linux,phandle = <0x25>;
  1377. };
  1378.  
  1379. qcom,cache_dump {
  1380. qcom,l2-dump-size = <0x200000>;
  1381. compatible = "qcom,cache_dump";
  1382. qcom,l1-dump-size = <0x100000>;
  1383. };
  1384.  
  1385. nss@40000000 {
  1386. qcom,wlanredirect-enabled;
  1387. resets = <0x0c 0x73 0x0c 0x74 0x0c 0x75 0x0c 0x76>;
  1388. qcom,turbo-frequency;
  1389. qcom,portid-enabled;
  1390. qcom,ipv6-enabled;
  1391. qcom,max-frequency = <0x2faf0800>;
  1392. compatible = "qcom,nss";
  1393. interrupts = <0x00 0xd5 0x04 0x00 0xe8 0x04>;
  1394. clocks = <0x0c 0x11b 0x0c 0x119 0x0c 0x11a 0x0d 0x0e>;
  1395. qcom,mid-frequency = <0x23c34600>;
  1396. qcom,map-t-enabled;
  1397. qcom,load-addr = <0x40000000>;
  1398. qcom,tunipip6-enabled;
  1399. qcom,id = <0x00>;
  1400. qcom,pptp-enabled;
  1401. clock-names = "nss-core-clk\0nss-tcm-src\0nss-tcm-clk\0nss-fab0-clk\0nss-fab1-clk";
  1402. qcom,shaping-enabled;
  1403. qcom,num-irq = <0x02>;
  1404. qcom,l2tpv2-enabled;
  1405. reg = <0x36000000 0x1000 0x39000000 0x10000>;
  1406. qcom,low-frequency = <0x68e7780>;
  1407. qcom,num-queue = <0x02>;
  1408. reg-names = "nphys\0vphys";
  1409. reset-names = "clkrst-clamp\0clamp\0ahb\0axi";
  1410. qcom,tun6rd-enabled;
  1411. qcom,ipv4-enabled;
  1412. qcom,wlan-dataplane-offload-enabled;
  1413. };
  1414.  
  1415. gpio-leds {
  1416. compatible = "gpio-leds";
  1417. pinctrl-0 = <0x14>;
  1418.  
  1419. ap161_red_lan1 {
  1420. default-state = "off";
  1421. gpios = <0x19 0x44 0x00>;
  1422. label = "ap161:red:lan1";
  1423. };
  1424.  
  1425. ap161_red_led2g {
  1426. default-state = "off";
  1427. gpios = <0x19 0x35 0x00>;
  1428. label = "ap161:red:led2g";
  1429. };
  1430.  
  1431. ap161_green_lan1 {
  1432. default-state = "off";
  1433. gpios = <0x19 0x16 0x01>;
  1434. label = "ap161:green:lan1";
  1435. };
  1436.  
  1437. ap161_red_ctrl {
  1438. default-state = "off";
  1439. gpios = <0x19 0x37 0x00>;
  1440. label = "ap161:red:ctrl";
  1441. };
  1442.  
  1443. ap161_red_lan2 {
  1444. default-state = "off";
  1445. gpios = <0x19 0x43 0x00>;
  1446. label = "ap161:red:lan2";
  1447. };
  1448.  
  1449. ap161_green_led2g {
  1450. default-state = "off";
  1451. gpios = <0x19 0x36 0x00>;
  1452. label = "ap161:green:led2g";
  1453. };
  1454.  
  1455. ap161_red_status {
  1456. default-state = "off";
  1457. gpios = <0x19 0x02 0x01>;
  1458. label = "ap161:red:status";
  1459. };
  1460.  
  1461. ap161_red_led5g {
  1462. default-state = "off";
  1463. gpios = <0x19 0x41 0x00>;
  1464. label = "ap161:red:led5g";
  1465. };
  1466.  
  1467. ap161_green_ctrl {
  1468. default-state = "off";
  1469. gpios = <0x19 0x38 0x00>;
  1470. label = "ap161:green:ctrl";
  1471. };
  1472.  
  1473. ap161_green_lan2 {
  1474. default-state = "off";
  1475. gpios = <0x19 0x17 0x01>;
  1476. label = "ap161:green:lan2";
  1477. };
  1478.  
  1479. ap161_green_status {
  1480. default-state = "off";
  1481. gpios = <0x19 0x1a 0x00>;
  1482. label = "ap161:green:status";
  1483. };
  1484.  
  1485. ap161_green_led5g {
  1486. default-state = "off";
  1487. gpios = <0x19 0x40 0x00>;
  1488. label = "ap161:green:led5g";
  1489. };
  1490. };
  1491.  
  1492. watchdog@208a038 {
  1493. compatible = "qcom,kpss-wdt-ipq8064";
  1494. clocks = <0x15>;
  1495. reg = <0x208a038 0x40>;
  1496. timeout-sec = <0x0a>;
  1497. };
  1498. };
  1499.  
  1500. aliases {
  1501. mdio-gpio0 = "/soc/mdio";
  1502. ethernet0 = "/soc/ethernet@37000000";
  1503. ethernet1 = "/soc/ethernet@37200000";
  1504. };
  1505. };
  1506.  
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