CPU.hdl

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/05/CPU.hdl

/**
 * The Hack CPU (Central Processing unit), consisting of an ALU,
 * two registers named A and D, and a program counter named PC.
 * The CPU is designed to fetch and execute instructions written in
 * the Hack machine language. In particular, functions as follows:
 * Executes the inputted instruction according to the Hack machine
 * language specification. The D and A in the language specification
 * refer to CPU-resident registers, while M refers to the external
 * memory location addressed by A, i.e. to Memory[A]. The inM input
 * holds the value of this location. If the current instruction needs
 * to write a value to M, the value is placed in outM, the address
 * of the target location is placed in the addressM output, and the
 * writeM control bit is asserted. (When writeM==0, any value may
 * appear in outM). The outM and writeM outputs are combinational:
 * they are affected instantaneously by the execution of the current
 * instruction. The addressM and pc outputs are clocked: although they
 * are affected by the execution of the current instruction, they commit
 * to their new values only in the next time step. If reset==1 then the
 * CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather
 * than to the address resulting from executing the current instruction.
 */

CHIP CPU {

    IN  inM[16],         // M value input  (M = contents of RAM[A])
        instruction[16], // Instruction for execution
        reset;           // Signals whether to re-start the current
                         // program (reset==1) or continue executing
                         // the current program (reset==0).

    OUT outM[16],        // M value output
        writeM,          // Write to M?
        addressM[15],    // Address in data memory (of M)
        pc[15];          // address of next instruction

    PARTS:
    // Put your code here:
    Mux16(a=instruction, b=fromalu, sel=instruction[15], out=toaregister);
    And(a=instruction[15], b=instruction[3], out=writeM);

    // A-Register
    // any a-instruction
    // c instruction with d1 set
    And(a=instruction[15], b=instruction[5], out=loadaregister);
    Not(in=instruction[15], out=notins);
    Or(a=notins, b=loadaregister, out=loadareg);

    ARegister(in=toaregister, load=loadareg, out=fromaregister, out[0..14]=addressM);

    // M/A only active during c instruction
    And(a=instruction[15], b=instruction[12], out=loadm);
    Mux16(a=fromaregister, b=inM, sel=loadm, out=frommora);

    // D-Register also active during c instruction
    And(a=instruction[15], b=instruction[4], out=loaddregister);
    DRegister(in=todregister, load=loaddregister, out=fromdregister);

    // ALU
    ALU(x=fromdregister, y=frommora, zx=instruction[11], nx=instruction[10], zy=instruction[9], ny=instruction[8], f=instruction[7], no=instruction[6], out=outM, out=fromalu, out=todregister, zr=outzr, ng=outng);

    // ALU status bit(zr, ng)
    Or(a=outzr, b=outng, out=outzrng);
    Not(in=outzrng, out=pos);

    //JGT
    And(a=pos, b=instruction[0], out=jgt);

    //JEQ
    And(a=outzr, b=instruction[1], out=jeq);

    //JGE
    Or(a=outzr, b=pos, out=zrorpos);
    And(a=zrorpos, b=instruction[0], out=jgefirst);
    And(a=jgefirst, b=instruction[1], out=jge);

    //JLT
    And(a=outng, b=instruction[2], out=jlt);

    //JNE
    Or(a=outng, b=pos, out=ngorpos);
    And(a=ngorpos, b=instruction[0], out=jnefirst);
    And(a=jnefirst, b=instruction[2], out=jne);

    //JLE
    Or(a=outng, b=outzr, out=ngorzr);
    And(a=ngorzr, b=instruction[1], out=jlefirst);
    And(a=jlefirst, b=instruction[2], out=jle);

    //JMP
    Or(a=outng, b=outzr, out=zrorng);
    Or(a=zrorng, b=pos, out=zrorngorpos);
    And(a=zrorngorpos, b=instruction[0], out=jmpfirst);
    And(a=jmpfirst, b=instruction[1], out=jmpsecond);
    And(a=jmpsecond, b=instruction[2], out=jmp);

    Or(a=jgt, b=jeq, out=firstload);
    Or(a=jge, b=jlt, out=secondload);
    Or(a=jne, b=jle, out=thirdload);

    Or(a=firstload, b=secondload, out=firstsecond);
    Or(a=thirdload, b=jmp, out=thirdjmp);

    Or(a=firstsecond, b=thirdjmp, out=loadjmp);

    And(a=instruction[15], b=loadjmp, out=loadto);

    PC(in=fromaregister, load=loadto, inc=true, reset=reset, out[0..14]=pc);
}