module DZ (input logic clk, sclr, output reg [2:0] q);

    always @ (posedge clk)

    begin
        if (sclr)
            q <= 0;
        else
            begin
                q[2] <= (~sclr)&(~q[2])&(~q[1])|(~sclr)&(~q[0])&(~q[2])|(q[1])&(q[0])&(q[2])&(~sclr);
                q[1] <= (~sclr)&(~q[1])&(q[0])|(~sclr)&(q[1])&(~q[0]);
                q[0] <= (~sclr)&(~q[0]);
            end

    end

endmodule