#update cpld
This operation will reset the switch on completion. Are you sure you would like to update the CPLD? (y/n) y

Issuing CPLD update command...
Warning: This operation will reset the switch on completion.
Processing virtual machine file "/mnt/application/cpld.vme"......

Diamond Deployment Tool 3.9
CREATION DATE: Tue Dec 19 13:16:40 2017



U-Boot SPL 2012.10-00079-g20827d2 (May 22 2017 - 16:58:14)
BENCH SCREENING TEST1
=========================================
IPROC_XGPLL_CTRL_3: 0x15400000
IPROC_XGPLL_STATUS: 0x80000287
DCO code: 40
PASS
=========================================
HWRev: 0xa5 AVS: 0x1 VOUT Init: 0x64 VOUT Set: 0x5f Steps: 5 Fail: 0
DEV ID= 0000dc14
SKU ID = 0x0
DDR type: DDR3
MEMC 0 DDR speed = 800MHz
ddr_init2: Calling soc_ddr40_set_shmoo_dram_config
ddr_init2: Calling soc_ddr40_phy_calibrate
C01. Check Power Up Reset_Bar
C02. Config and Release PLL from reset
C03. Poll PLL Lock
C04. Calibrate ZQ (ddr40_phy_calib_zq)
C05. DDR PHY VTT On (Virtual VTT setup) DISABLE all Virtual VTT
C06. DDR40_PHY_DDR3_MISC
C07. VDL Calibration
C07.1
C07.2
C07.4
C07.4.1
C07.4.4
VDL calibration result: 0x30000003 (cal_steps = 0)
C07.4.5
C07.4.6
C07.5
C08. DDR40_PHY_DDR3_MISC : Start DDR40_PHY_RDLY_ODT....
C09. Start ddr40_phy_autoidle_on (MEM_SYS_PARAM_PHY_AUTO_IDLE) ....
C10. Wait for Phy Ready
Programming controller register
ddr_init2: Calling soc_ddr40_shmoo_ctl
Validate Shmoo parameters stored in flash ..... OK
Press Ctrl-C to run Shmoo ..... skipped
Restoring Shmoo parameters from flash ..... done
Running simple memory test ..... OK
DDR Tune Completed
 Micron MT29F2G08ABAEA, 128 KiB blocks, 2 KiB pages, 16B OOB, 8-bit
NAND:   chipsize 256 MiB


U-Boot 2012.10-00079-g20827d2 (May 22 2017 - 16:58:14)

DRAM:  1 GiB
WARNING: Caches not enabled
NAND:   Micron MT29F2G08ABAEA, 128 KiB blocks, 2 KiB pages, 16B OOB, 8-bit
NAND:   chipsize 256 MiB
In:    serial
Out:   serial
Err:   serial
arm_clk=1000MHz, axi_clk=499MHz, apb_clk=124MHz, arm_periph_clk=500MHz
Net:   Registering eth
Broadcom BCM IPROC Ethernet driver 0.1
Using GMAC0 (0x18022000)
et0: ethHw_chipAttach: Chip ID: 0xdc14; phyaddr: 0x1
serdes_reset_core pbyaddr(0x1) id2(0xf)
bcmiproc_eth-0
boot in 3 s
Creating 1 MTD partitions on "nand0":
0x000000200000-0x00000f000000 : "mtd=4"
Loading file '/image1' to addr 0x70000000 with size 29693348 (0x01c515a4)...
Done
## Booting kernel from Legacy Image at 70000074 ...
   Image Name:   System for iproc_pct
   Image Type:   ARM Linux Multi-File Image (gzip compressed)
   Data Size:    29693168 Bytes = 28.3 MiB
   Load Address: 61008000
   Entry Point:  61008000
   Contents:
      Image 0: 2535230 Bytes = 2.4 MiB
      Image 1: 1813199 Bytes = 1.7 MiB
      Image 2: 474 Bytes = 474 Bytes
      Image 3: 25344240 Bytes = 24.2 MiB
   Verifying Checksum ... OK
## Loading init Ramdisk from multi component Legacy Image at 70000074 ...
   Uncompressing Multi-File Image ... OK
boot_prep_linux commandline: console=ttyS0,9600 maxcpus=2 mem=1024M root=/dev/ram mtdparts=nand_iproc.0:1024k(nboot),512k(nenv),256k(vpd),256k(shmoo),243712k(fs),16384k(diags) ubi.mtd=fs ethaddr=f8:b1:56:50:28:a1 quiet

Starting kernel ...


recovery_signal_init:vaddr=0xF0000000 mapped address=0x18000000
recovery_signal_init:setting GPIO-1 to output
recovery_signal_init:writing GPIO-1 high
starting pid 890, tty '': '/etc/init.d/rcS'
starting pid 1022, tty '/dev/ttyS0': '/etc/rc.d/rc.fastpath'
Legacy hardware detected
Mounting /dev/mtdblock4 at /mnt/fastpath...done.
Mounting tmpfs at /mnt/application...done.


Dell EMC Networking Boot Options
================================

Select a menu option within 3 seconds or the Operational Code will start automatically...

1 - Start Operational Code
2 - Display Boot Menu

Select (1, 2)#


Extracting Operational Code from .stk file...done.
Loading Operational Code...done.
Loading modules...
Decompressing Operational Code...done.
Uncompressing apps.lzma
Uncompressing python.lzma
Installing Python
DMA pool size: 16777216
AXI unit 0: Dev 0xb340, Rev 0x01, Chip BCM56340_A0, Driver BCM56340_A0
SOC unit 0 attached to PCI device BCM56340_A0
Using a clock divider of 25 for mac_cclk


<186> Apr  2 23:56:17 0.0.0.0-1 General[fp_main_task]: bootos.c(191) 7 %% CRIT Event(0xaaaaaaaa)                                                                                            started!

<185> Apr  2 23:56:17 0.0.0.0-1 SIM[Cnfgr_Thread ]: sim_util.c(3911) 9 %% ALRT Switch was reset due to power disruption or unexpected restart.(error[0x0]).

(Unit 1 - Waiting to select management unit)>
(Unit 1 - CLI unavailable - please connect to master on Unit 2)>