`timescale 1ns/1ps
module counter_test;
    reg clk, ena, clrn;
    wire [2:0] result;

    initial begin
        clk=0;
        forever #10 clk = ~clk;
    end

    initial begin
        ena=1;
        #300 ena = ~ena;
        #160 ena = ~ena;
        #20 ena = ~ena;
        #300 ena = ~ena;
    end

    initial begin
    clrn = 0;
    #15 clrn = 1;
    #1000 $stop;
    end

    lab3 test_dev(clk, clrn, ena, result);
endmodule