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phy-exynos5

Sep 18th, 2017
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  1. /*
  2. * Samsung EXYNOS5 SoC series USB DRD PHY driver
  3. *
  4. * Phy provider for USB 3.0 DRD controller on Exynos5 SoC series
  5. *
  6. * Copyright (C) 2014 Samsung Electronics Co., Ltd.
  7. * Author: Vivek Gautam <gautam.vivek@samsung.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13.  
  14. #include <linux/clk.h>
  15. #include <linux/delay.h>
  16. #include <linux/io.h>
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/of.h>
  20. #include <linux/of_address.h>
  21. #include <linux/of_device.h>
  22. #include <linux/phy/phy.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/mutex.h>
  25. #include <linux/mfd/syscon.h>
  26. #include <linux/regmap.h>
  27. #include <linux/regulator/consumer.h>
  28. #include <linux/soc/samsung/exynos-regs-pmu.h>
  29.  
  30. /* Exynos USB PHY registers */
  31. #define EXYNOS5_FSEL_9MHZ6 0x0
  32. #define EXYNOS5_FSEL_10MHZ 0x1
  33. #define EXYNOS5_FSEL_12MHZ 0x2
  34. #define EXYNOS5_FSEL_19MHZ2 0x3
  35. #define EXYNOS5_FSEL_20MHZ 0x4
  36. #define EXYNOS5_FSEL_24MHZ 0x5
  37. #define EXYNOS5_FSEL_50MHZ 0x7
  38.  
  39. /* EXYNOS5: USB 3.0 DRD PHY registers */
  40. #define EXYNOS5_DRD_LINKSYSTEM 0x04
  41. #define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
  42. #define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
  43. #define LINKSYSTEM_XHCI_VERSION_CONTROL BIT(27)
  44.  
  45. #define EXYNOS5_DRD_PHYUTMI 0x08
  46. #define PHYUTMI_VBUSVLDEXTSEL BIT(10)
  47. #define PHYUTMI_VBUSVLDEXT BIT(9)
  48. #define PHYUTMI_TXBITSTUFENH BIT(8)
  49. #define PHYUTMI_TXBITSTUEN BIT(7)
  50. #define PHYUTMI_OTGDISABLE BIT(6)
  51. #define PHYUTMI_IDPULLUP BIT(5)
  52. #define PHYUTMI_DRVVBUS BIT(4)
  53. #define PHYUTMI_DPPULLDOWND_M BIT(3)
  54. #define PHYUTMI_DPPULLDOWND_P BIT(2)
  55. #define PHYUTMI_FORCESUSPEND BIT(1)
  56. #define PHYUTMI_FORCESLEEP BIT(0)
  57.  
  58. #define EXYNOS5_DRD_PHYPIPE 0x0c
  59. #define PHYPIPE_LANE0_TX2RX_LOOPBK BIT(0)
  60.  
  61. #define EXYNOS5_DRD_PHYCLKRST 0x10
  62. #define PHYCLKRST_EN_UTMISUSPEND BIT(31)
  63. #define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
  64. #define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
  65. #define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
  66. #define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
  67. #define PHYCLKRST_SSC_EN BIT(20)
  68. #define PHYCLKRST_REF_SSP_EN BIT(19)
  69. #define PHYCLKRST_REF_CLKDIV2 BIT(18)
  70. #define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
  71. #define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
  72. #define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x32 << 11)
  73. #define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
  74. #define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
  75. #define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
  76. #define PHYCLKRST_FSEL_UTMI_MASK (0x7 << 5)
  77. #define PHYCLKRST_FSEL_PIPE_MASK (0x7 << 8)
  78. #define PHYCLKRST_FSEL(_x) ((_x) << 5)
  79. #define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
  80. #define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
  81. #define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
  82. #define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
  83. #define PHYCLKRST_RETENABLEN BIT(4)
  84. #define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
  85. #define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
  86. #define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
  87. #define PHYCLKRST_PORTRESET BIT(1)
  88. #define PHYCLKRST_COMMONONN BIT(0)
  89.  
  90. #define EXYNOS5_DRD_PHYREG0 0x14
  91. #define PHYREG0_SSC_REF_CLK_SEL BIT(21)
  92. #define PHYREG0_SSC_RANGE BIT(20)
  93. #define PHYREG0_CR_WRITE BIT(19)
  94. #define PHYREG0_CR_READ BIT(18)
  95. #define PHYREG0_CR_DATA_IN(_x) ((_x) << 2)
  96. #define PHYREG0_CR_CAP_DATA BIT(1)
  97. #define PHYREG0_CR_CAP_ADDR BIT(0)
  98.  
  99. #define EXYNOS5_DRD_PHYREG1 0x18
  100. #define PHYREG1_CR_DATA_OUT(_x) ((_x) << 1)
  101. #define PHYREG1_CR_ACK BIT(0)
  102.  
  103. #define EXYNOS5_DRD_PHYPARAM0 0x1c
  104. #define PHYPARAM0_REF_USE_PAD BIT(31)
  105. #define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
  106. #define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
  107. #define PHYPARAM0_TXVREFTUNE_MASK (0xf << 22)
  108. #define PHYPARAM0_TXVREFTUNE(_x) ((_x) << 22)
  109. #define PHYPARAM0_TXPREEMPAMPTUNE_MASK (0x3 << 15)
  110. #define PHYPARAM0_TXPREEMPAMPTUNE(_x) ((_x) << 15)
  111. #define PHYPARAM0_SQRXTUNE_MASK (0x7 << 6)
  112. #define PHYPARAM0_SQRXTUNE(_x) ((_x) << 6)
  113. #define PHYPARAM0_COMPDISTUNE_MASK (0x7 << 0)
  114. #define PHYPARAM0_COMPDISTUNE(_x) ((_x) << 0)
  115.  
  116. #define EXYNOS5_DRD_PHYPARAM1 0x20
  117. #define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
  118. #define PHYPARAM1_PCS_TXSWING_FULL_MASK (0x7f << 12)
  119. #define PHYPARAM1_PCS_TXSWING_FULL(_x) ((_x) << 12)
  120. #define PHYPARAM1_PCS_TXDEEMPH_3P5DB_MASK (0x3f << 0)
  121. #define PHYPARAM1_PCS_TXDEEMPH_3P5DB(_x) ((_x) << 0)
  122. #define PHYPARAM1_PCS_TXDEEMPH (0x1c)
  123.  
  124. #define EXYNOS5_DRD_PHYTERM 0x24
  125.  
  126. #define EXYNOS5_DRD_PHYTEST 0x28
  127. #define PHYTEST_POWERDOWN_SSP BIT(3)
  128. #define PHYTEST_POWERDOWN_HSP BIT(2)
  129.  
  130. #define EXYNOS5_DRD_PHYADP 0x2c
  131.  
  132. #define EXYNOS5_DRD_PHYUTMICLKSEL 0x30
  133. #define PHYUTMICLKSEL_UTMI_CLKSEL BIT(2)
  134.  
  135. #define EXYNOS5_DRD_PHYRESUME 0x34
  136. #define EXYNOS5_DRD_LINKPORT 0x44
  137.  
  138. /* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */
  139. #define EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN (0x15)
  140. #define LOSLEVEL_OVRD_IN_LOS_BIAS_5420 (0x5 << 13)
  141. #define LOSLEVEL_OVRD_IN_LOS_BIAS_DEFAULT (0x0 << 13)
  142. #define LOSLEVEL_OVRD_IN_EN (0x1 << 10)
  143. #define LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT (0x9 << 0)
  144.  
  145. #define EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN (0x12)
  146. #define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420 (0x5 << 13)
  147. #define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_DEFAULT (0x4 << 13)
  148.  
  149. #define EXYNOS5_DRD_CHARGE_PUMP_CURRENT (0x30)
  150. #define EXYNOS5_DRD_CHARGE_PUMP_CURRENT_VAL (0x80)
  151.  
  152. #define EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG (0x1010)
  153. #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M (0x4 << 4)
  154. #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M (0x8 << 4)
  155. #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_25M_26M (0x8 << 4)
  156. #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M (0x20 << 4)
  157. #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_62M5 (0x20 << 4)
  158. #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_96M_100M (0x40 << 4)
  159.  
  160. #define KHZ 1000
  161. #define MHZ (KHZ * KHZ)
  162.  
  163. enum exynos5_usbdrd_phy_id {
  164. EXYNOS5_DRDPHY_UTMI,
  165. EXYNOS5_DRDPHY_PIPE3,
  166. EXYNOS5_DRDPHYS_NUM,
  167. };
  168.  
  169. struct phy_usb_instance;
  170. struct exynos5_usbdrd_phy;
  171.  
  172. struct exynos5_usbdrd_phy_config {
  173. u32 id;
  174. void (*phy_isol)(struct phy_usb_instance *inst, u32 on);
  175. void (*phy_init)(struct exynos5_usbdrd_phy *phy_drd);
  176. unsigned int (*set_refclk)(struct phy_usb_instance *inst);
  177. int (*phy_calibrate)(struct phy_usb_instance *inst);
  178. };
  179.  
  180. struct exynos5_usbdrd_phy_drvdata {
  181. const struct exynos5_usbdrd_phy_config *phy_cfg;
  182. u32 pmu_offset_usbdrd0_phy;
  183. u32 pmu_offset_usbdrd1_phy;
  184. bool has_common_clk_gate;
  185. int (*phy_exynos_calibrate)(struct exynos5_usbdrd_phy *phy_drd);
  186. };
  187.  
  188. /**
  189. * struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY
  190. * @dev: pointer to device instance of this platform device
  191. * @reg_phy: usb phy controller register memory base
  192. * @clk: phy clock for register access
  193. * @pipeclk: clock for pipe3 phy
  194. * @utmiclk: clock for utmi+ phy
  195. * @itpclk: clock for ITP generation
  196. * @drv_data: pointer to SoC level driver data structure
  197. * @phys[]: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY
  198. * instances each with its 'phy' and 'phy_cfg'.
  199. * @extrefclk: frequency select settings when using 'separate
  200. * reference clocks' for SS and HS operations
  201. * @ref_clk: reference clock to PHY block from which PHY's
  202. * operational clocks are derived
  203. * vbus: VBUS regulator for phy
  204. * vbus_boost: Boost regulator for VBUS present on few Exynos boards
  205. */
  206. struct exynos5_usbdrd_phy {
  207. struct device *dev;
  208. void __iomem *reg_phy;
  209. struct clk *clk;
  210. struct clk *pipeclk;
  211. struct clk *utmiclk;
  212. struct clk *itpclk;
  213. const struct exynos5_usbdrd_phy_drvdata *drv_data;
  214. struct phy_usb_instance {
  215. struct phy *phy;
  216. u32 index;
  217. struct regmap *reg_pmu;
  218. u32 pmu_offset;
  219. const struct exynos5_usbdrd_phy_config *phy_cfg;
  220. } phys[EXYNOS5_DRDPHYS_NUM];
  221. u32 extrefclk;
  222. struct clk *ref_clk;
  223. struct regulator *vbus;
  224. struct regulator *vbus_boost;
  225. };
  226.  
  227. static inline
  228. struct exynos5_usbdrd_phy *to_usbdrd_phy(struct phy_usb_instance *inst)
  229. {
  230. return container_of((inst), struct exynos5_usbdrd_phy,
  231. phys[(inst)->index]);
  232. }
  233.  
  234. /*
  235. * exynos5_rate_to_clk() converts the supplied clock rate to the value that
  236. * can be written to the phy register.
  237. */
  238. static unsigned int exynos5_rate_to_clk(unsigned long rate, u32 *reg)
  239. {
  240. /* EXYNOS5_FSEL_MASK */
  241.  
  242. switch (rate) {
  243. case 9600 * KHZ:
  244. *reg = EXYNOS5_FSEL_9MHZ6;
  245. break;
  246. case 10 * MHZ:
  247. *reg = EXYNOS5_FSEL_10MHZ;
  248. break;
  249. case 12 * MHZ:
  250. *reg = EXYNOS5_FSEL_12MHZ;
  251. break;
  252. case 19200 * KHZ:
  253. *reg = EXYNOS5_FSEL_19MHZ2;
  254. break;
  255. case 20 * MHZ:
  256. *reg = EXYNOS5_FSEL_20MHZ;
  257. break;
  258. case 24 * MHZ:
  259. *reg = EXYNOS5_FSEL_24MHZ;
  260. break;
  261. case 50 * MHZ:
  262. *reg = EXYNOS5_FSEL_50MHZ;
  263. break;
  264. default:
  265. return -EINVAL;
  266. }
  267.  
  268. return 0;
  269. }
  270.  
  271. static void exynos5_usbdrd_phy_isol(struct phy_usb_instance *inst,
  272. unsigned int on)
  273. {
  274. unsigned int val;
  275.  
  276. if (!inst->reg_pmu)
  277. return;
  278.  
  279. val = on ? 0 : EXYNOS4_PHY_ENABLE;
  280.  
  281. regmap_update_bits(inst->reg_pmu, inst->pmu_offset,
  282. EXYNOS4_PHY_ENABLE, val);
  283. }
  284.  
  285. /*
  286. * Sets the pipe3 phy's clk as EXTREFCLK (XXTI) which is internal clock
  287. * from clock core. Further sets multiplier values and spread spectrum
  288. * clock settings for SuperSpeed operations.
  289. */
  290. static unsigned int
  291. exynos5_usbdrd_pipe3_set_refclk(struct phy_usb_instance *inst)
  292. {
  293. u32 reg;
  294. struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
  295.  
  296. /* restore any previous reference clock settings */
  297. reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
  298.  
  299. /* Use EXTREFCLK as ref clock */
  300. reg &= ~PHYCLKRST_REFCLKSEL_MASK;
  301. reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK;
  302.  
  303. /* FSEL settings corresponding to reference clock */
  304. reg &= ~PHYCLKRST_FSEL_PIPE_MASK |
  305. PHYCLKRST_MPLL_MULTIPLIER_MASK |
  306. PHYCLKRST_SSC_REFCLKSEL_MASK;
  307. switch (phy_drd->extrefclk) {
  308. case EXYNOS5_FSEL_50MHZ:
  309. reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
  310. PHYCLKRST_SSC_REFCLKSEL(0x00));
  311. break;
  312. case EXYNOS5_FSEL_24MHZ:
  313. reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
  314. PHYCLKRST_SSC_REFCLKSEL(0x88));
  315. break;
  316. case EXYNOS5_FSEL_20MHZ:
  317. reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF |
  318. PHYCLKRST_SSC_REFCLKSEL(0x00));
  319. break;
  320. case EXYNOS5_FSEL_19MHZ2:
  321. reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF |
  322. PHYCLKRST_SSC_REFCLKSEL(0x88));
  323. break;
  324. default:
  325. dev_dbg(phy_drd->dev, "unsupported ref clk\n");
  326. break;
  327. }
  328.  
  329. return reg;
  330. }
  331.  
  332. /*
  333. * Sets the utmi phy's clk as EXTREFCLK (XXTI) which is internal clock
  334. * from clock core. Further sets the FSEL values for HighSpeed operations.
  335. */
  336. static unsigned int
  337. exynos5_usbdrd_utmi_set_refclk(struct phy_usb_instance *inst)
  338. {
  339. u32 reg;
  340. struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
  341.  
  342. /* restore any previous reference clock settings */
  343. reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
  344.  
  345. reg &= ~PHYCLKRST_REFCLKSEL_MASK;
  346. reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK;
  347.  
  348. reg &= ~PHYCLKRST_FSEL_UTMI_MASK |
  349. PHYCLKRST_MPLL_MULTIPLIER_MASK |
  350. PHYCLKRST_SSC_REFCLKSEL_MASK;
  351. reg |= PHYCLKRST_FSEL(phy_drd->extrefclk);
  352.  
  353. return reg;
  354. }
  355.  
  356. static void exynos5_usbdrd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd)
  357. {
  358. u32 reg;
  359.  
  360. /* Set when this signal is asserted,data from the transmit
  361. predrive is looped to the receiver slicers */
  362. reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPIPE);
  363. reg |= PHYPIPE_LANE0_TX2RX_LOOPBK;
  364. writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPIPE);
  365.  
  366. reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
  367. /* Set Tx De-Emphasis level */
  368. reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
  369. reg |= PHYPARAM1_PCS_TXDEEMPH;
  370. reg &= ~PHYPARAM1_PCS_TXSWING_FULL_MASK;
  371. reg |= PHYPARAM1_PCS_TXSWING_FULL(0x7f);
  372. reg &= ~PHYPARAM1_PCS_TXDEEMPH_3P5DB_MASK;
  373. reg |= PHYPARAM1_PCS_TXDEEMPH_3P5DB(0x18);
  374. writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
  375.  
  376. reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
  377. reg &= ~PHYTEST_POWERDOWN_SSP;
  378. writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
  379. }
  380.  
  381. static void exynos5_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
  382. {
  383. u32 reg;
  384.  
  385. /* Release force sleep & force suspend setting for UTMI phy */
  386. reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
  387. reg &= ~(PHYUTMI_FORCESUSPEND | PHYUTMI_FORCESLEEP |
  388. PHYUTMI_DPPULLDOWND_M | PHYUTMI_DPPULLDOWND_P |
  389. PHYUTMI_DRVVBUS | PHYUTMI_OTGDISABLE);
  390. reg |= (PHYUTMI_IDPULLUP | PHYUTMI_DRVVBUS);
  391. writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
  392.  
  393. /* Tuning the USB3 HS Pre-empasis and TXVREFTUNE */
  394. reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
  395. /* Set Loss-of-Signal Detector sensitivity */
  396. reg &= ~PHYPARAM0_REF_LOSLEVEL_MASK;
  397. reg |= PHYPARAM0_REF_LOSLEVEL;
  398. reg &= ~PHYPARAM0_COMPDISTUNE_MASK;
  399. reg |= PHYPARAM0_COMPDISTUNE(0x7);
  400. reg &= ~PHYPARAM0_TXPREEMPAMPTUNE_MASK;
  401. reg |= PHYPARAM0_TXPREEMPAMPTUNE(0x0);
  402. reg &= ~PHYPARAM0_TXVREFTUNE_MASK;
  403. reg |= PHYPARAM0_TXVREFTUNE(0x1);
  404. reg &= ~PHYPARAM0_SQRXTUNE_MASK;
  405. reg |= PHYPARAM0_SQRXTUNE(0x3);
  406. writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
  407.  
  408. reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
  409. /* Set Tx De-Emphasis level */
  410. reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
  411. reg |= PHYPARAM1_PCS_TXDEEMPH;
  412. writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
  413.  
  414. /* UTMI Power Control */
  415. writel(PHYUTMI_OTGDISABLE, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
  416.  
  417. reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
  418. reg &= ~PHYTEST_POWERDOWN_HSP;
  419. writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
  420. }
  421.  
  422. static int exynos5_usbdrd_phy_init(struct phy *phy)
  423. {
  424. int ret;
  425. u32 reg;
  426. struct phy_usb_instance *inst = phy_get_drvdata(phy);
  427. struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
  428.  
  429. ret = clk_prepare_enable(phy_drd->clk);
  430. if (ret)
  431. return ret;
  432.  
  433. /* Reset USB 3.0 PHY */
  434. writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
  435. writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1);
  436. writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYRESUME);
  437.  
  438. /*
  439. * Setting the Frame length Adj value[6:1] to default 0x20
  440. * See xHCI 1.0 spec, 5.2.4
  441. */
  442. reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
  443. reg = LINKSYSTEM_XHCI_VERSION_CONTROL | LINKSYSTEM_FLADJ(0x20);
  444. writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
  445.  
  446. reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
  447. /* Select PHY CLK source */
  448. reg &= ~PHYPARAM0_REF_USE_PAD;
  449. writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
  450.  
  451. /* This bit must be set for both HS and SS operations */
  452. reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL);
  453. reg |= PHYUTMICLKSEL_UTMI_CLKSEL;
  454. writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL);
  455.  
  456. /* UTMI or PIPE3 specific init */
  457. inst->phy_cfg->phy_init(phy_drd);
  458.  
  459. /* reference clock settings */
  460. reg = inst->phy_cfg->set_refclk(inst);
  461.  
  462. /* Digital power supply in normal operating mode */
  463. reg |= PHYCLKRST_RETENABLEN |
  464. /* Enable ref clock for SS function */
  465. PHYCLKRST_REF_SSP_EN |
  466. /* Enable spread spectrum */
  467. PHYCLKRST_SSC_EN |
  468. /* Power down HS Bias and PLL blocks in suspend mode */
  469. PHYCLKRST_COMMONONN |
  470. /* Reset the port */
  471. PHYCLKRST_PORTRESET |
  472. /* Default 24Mhz crystal clock */
  473. PHYCLKRST_FSEL(EXYNOS5_FSEL_24MHZ) |
  474. PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
  475. PHYCLKRST_SSC_REFCLKSEL(0x88);
  476.  
  477. /* Disable utmi_suspend_com_n of LINK */
  478. reg &= ~(PHYCLKRST_EN_UTMISUSPEND);
  479. writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
  480.  
  481. udelay(10);
  482.  
  483. reg &= ~PHYCLKRST_PORTRESET;
  484. writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
  485.  
  486. /*
  487. * Calibrate some of the PHY parameters, using cr_port control
  488. * register, which are internal to PHY and are not exposed
  489. * directly to the outside world for configuring.
  490. */
  491. if (inst->phy_cfg->phy_calibrate) {
  492. ret = inst->phy_cfg->phy_calibrate(inst);
  493. if (ret)
  494. dev_err(phy_drd->dev,
  495. "Exiting init: Failed to calibrate PHY\n");
  496. }
  497.  
  498. return ret;
  499. }
  500.  
  501. static int exynos5_usbdrd_phy_exit(struct phy *phy)
  502. {
  503. u32 reg;
  504. struct phy_usb_instance *inst = phy_get_drvdata(phy);
  505. struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
  506.  
  507. /* Resetting the PHYUTMI enable bits */
  508. reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
  509. reg |= (PHYUTMI_OTGDISABLE | PHYUTMI_FORCESUSPEND |
  510. PHYUTMI_FORCESLEEP);
  511. reg &= ~(PHYUTMI_IDPULLUP | PHYUTMI_DRVVBUS);
  512. writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
  513.  
  514. /* Resetting the PHYCLKRST enable bits to reduce leakage current */
  515. reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
  516. reg &= ~(PHYCLKRST_REF_SSP_EN |
  517. PHYCLKRST_SSC_EN |
  518. PHYCLKRST_COMMONONN |
  519. PHYCLKRST_EN_UTMISUSPEND);
  520. writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
  521.  
  522. reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPIPE);
  523. reg &= ~PHYPIPE_LANE0_TX2RX_LOOPBK;
  524. writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPIPE);
  525.  
  526. /* Control PHYTEST to remove leakage current */
  527. reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
  528. reg |= PHYTEST_POWERDOWN_SSP |
  529. PHYTEST_POWERDOWN_HSP;
  530. writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
  531.  
  532. clk_disable_unprepare(phy_drd->clk);
  533.  
  534. return 0;
  535. }
  536.  
  537. static int exynos5_usbdrd_phy_power_on(struct phy *phy)
  538. {
  539. int ret;
  540. struct phy_usb_instance *inst = phy_get_drvdata(phy);
  541. struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
  542.  
  543. dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n");
  544.  
  545. clk_prepare_enable(phy_drd->ref_clk);
  546. if (!phy_drd->drv_data->has_common_clk_gate) {
  547. clk_prepare_enable(phy_drd->pipeclk);
  548. clk_prepare_enable(phy_drd->utmiclk);
  549. clk_prepare_enable(phy_drd->itpclk);
  550. }
  551.  
  552. /* Enable VBUS supply */
  553. if (phy_drd->vbus_boost) {
  554. ret = regulator_enable(phy_drd->vbus_boost);
  555. if (ret) {
  556. dev_err(phy_drd->dev,
  557. "Failed to enable VBUS boost supply\n");
  558. goto fail_vbus;
  559. }
  560. }
  561.  
  562. if (phy_drd->vbus) {
  563. ret = regulator_enable(phy_drd->vbus);
  564. if (ret) {
  565. dev_err(phy_drd->dev, "Failed to enable VBUS supply\n");
  566. goto fail_vbus_boost;
  567. }
  568. }
  569.  
  570. /* Power-on PHY*/
  571. inst->phy_cfg->phy_isol(inst, 0);
  572.  
  573. return 0;
  574.  
  575. fail_vbus_boost:
  576. if (phy_drd->vbus_boost)
  577. regulator_disable(phy_drd->vbus_boost);
  578.  
  579. fail_vbus:
  580. clk_disable_unprepare(phy_drd->ref_clk);
  581. if (!phy_drd->drv_data->has_common_clk_gate) {
  582. clk_disable_unprepare(phy_drd->itpclk);
  583. clk_disable_unprepare(phy_drd->utmiclk);
  584. clk_disable_unprepare(phy_drd->pipeclk);
  585. }
  586.  
  587. return ret;
  588. }
  589.  
  590. static int exynos5_usbdrd_phy_power_off(struct phy *phy)
  591. {
  592. struct phy_usb_instance *inst = phy_get_drvdata(phy);
  593. struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
  594.  
  595. dev_dbg(phy_drd->dev, "Request to power_off usbdrd_phy phy\n");
  596.  
  597. /* Power-off the PHY */
  598. inst->phy_cfg->phy_isol(inst, 1);
  599.  
  600. /* Disable VBUS supply */
  601. if (phy_drd->vbus)
  602. regulator_disable(phy_drd->vbus);
  603. if (phy_drd->vbus_boost)
  604. regulator_disable(phy_drd->vbus_boost);
  605.  
  606. clk_disable_unprepare(phy_drd->ref_clk);
  607. if (!phy_drd->drv_data->has_common_clk_gate) {
  608. clk_disable_unprepare(phy_drd->itpclk);
  609. clk_disable_unprepare(phy_drd->pipeclk);
  610. clk_disable_unprepare(phy_drd->utmiclk);
  611. }
  612.  
  613. return 0;
  614. }
  615.  
  616. static int crport_handshake(struct exynos5_usbdrd_phy *phy_drd,
  617. u32 val, u32 cmd)
  618. {
  619. u32 usec = 100;
  620. unsigned int result;
  621.  
  622. writel(val | cmd, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
  623.  
  624. do {
  625. result = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1);
  626. if (result & PHYREG1_CR_ACK)
  627. break;
  628.  
  629. udelay(1);
  630. } while (usec-- > 0);
  631.  
  632. if (!usec) {
  633. dev_err(phy_drd->dev,
  634. "CRPORT handshake timeout1 (0x%08x)\n", val);
  635. return -ETIME;
  636. }
  637.  
  638. usec = 100;
  639.  
  640. writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
  641.  
  642. do {
  643. result = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1);
  644. if (!(result & PHYREG1_CR_ACK))
  645. break;
  646.  
  647. udelay(1);
  648. } while (usec-- > 0);
  649.  
  650. if (!usec) {
  651. dev_err(phy_drd->dev,
  652. "CRPORT handshake timeout2 (0x%08x)\n", val);
  653. return -ETIME;
  654. }
  655.  
  656. return 0;
  657. }
  658.  
  659. static int crport_ctrl_write(struct exynos5_usbdrd_phy *phy_drd,
  660. u32 addr, u32 data)
  661. {
  662. int ret;
  663.  
  664. /* Write Address */
  665. writel(PHYREG0_CR_DATA_IN(addr),
  666. phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
  667. ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(addr),
  668. PHYREG0_CR_CAP_ADDR);
  669. if (ret)
  670. return ret;
  671.  
  672. /* Write Data */
  673. writel(PHYREG0_CR_DATA_IN(data),
  674. phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
  675. ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data),
  676. PHYREG0_CR_CAP_DATA);
  677. if (ret)
  678. return ret;
  679.  
  680. ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data),
  681. PHYREG0_CR_WRITE);
  682.  
  683. return ret;
  684. }
  685.  
  686. /*
  687. * Calibrate few PHY parameters using CR_PORT register to meet
  688. * SuperSpeed requirements on Exynos5420 and Exynos5800 systems,
  689. * which have 28nm USB 3.0 DRD PHY.
  690. */
  691. static int exynos5420_usbdrd_phy_calibrate(struct exynos5_usbdrd_phy *phy_drd)
  692. {
  693. unsigned int temp;
  694. int ret = 0;
  695.  
  696. /*
  697. * Change los_bias to (0x5) for 28nm PHY from a
  698. * default value (0x0); los_level is set as default
  699. * (0x9) as also reflected in los_level[30:26] bits
  700. * of PHYPARAM0 register.
  701. */
  702. temp = LOSLEVEL_OVRD_IN_LOS_BIAS_5420 |
  703. LOSLEVEL_OVRD_IN_EN |
  704. LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT;
  705. ret = crport_ctrl_write(phy_drd,
  706. EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN,
  707. temp);
  708. if (ret) {
  709. dev_err(phy_drd->dev,
  710. "Failed setting Loss-of-Signal level for SuperSpeed\n");
  711. return ret;
  712. }
  713.  
  714. /*
  715. * Set tx_vboost_lvl to (0x5) for 28nm PHY Tuning,
  716. * to raise Tx signal level from its default value of (0x4)
  717. */
  718. temp = TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420;
  719. ret = crport_ctrl_write(phy_drd,
  720. EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN,
  721. temp);
  722. if (ret) {
  723. dev_err(phy_drd->dev,
  724. "Failed setting Tx-Vboost-Level for SuperSpeed\n");
  725. return ret;
  726. }
  727.  
  728. /*
  729. * Set proper time to wait for RxDetect measurement, for
  730. * desired reference clock of PHY, by tuning the CR_PORT
  731. * register LANE0.TX_DEBUG which is internal to PHY.
  732. * This fixes issue with few USB 3.0 devices, which are
  733. * not detected (not even generate interrupts on the bus
  734. * on insertion) without this change.
  735. * e.g. Samsung SUM-TSB16S 3.0 USB drive.
  736. */
  737. switch (phy_drd->extrefclk) {
  738. case EXYNOS5_FSEL_50MHZ:
  739. temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M;
  740. break;
  741. case EXYNOS5_FSEL_20MHZ:
  742. case EXYNOS5_FSEL_19MHZ2:
  743. temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M;
  744. break;
  745. case EXYNOS5_FSEL_24MHZ:
  746. default:
  747. temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M;
  748. break;
  749. }
  750.  
  751. ret = crport_ctrl_write(phy_drd,
  752. EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG,
  753. temp);
  754. if (ret)
  755. dev_err(phy_drd->dev,
  756. "Failed setting RxDetect measurement time for SuperSpeed\n");
  757.  
  758. ret = crport_ctrl_write(phy_drd,
  759. EXYNOS5_DRD_CHARGE_PUMP_CURRENT,
  760. EXYNOS5_DRD_CHARGE_PUMP_CURRENT_VAL);
  761. if (ret)
  762. dev_err(phy_drd->dev,
  763. "Failed setting to set the charge pump proportional current\n");
  764.  
  765. return ret;
  766. }
  767.  
  768. /* Calibrate PIPE3 PHY settings, if any */
  769. static int exynos5_usbdrd_pipe3_calibrate(struct phy_usb_instance *inst)
  770. {
  771. struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
  772.  
  773. /* Call respective phy_calibrate given by certain platform */
  774. if (phy_drd->drv_data->phy_exynos_calibrate)
  775. return phy_drd->drv_data->phy_exynos_calibrate(phy_drd);
  776.  
  777. return -ENODEV;
  778. }
  779.  
  780. static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev,
  781. struct of_phandle_args *args)
  782. {
  783. struct exynos5_usbdrd_phy *phy_drd = dev_get_drvdata(dev);
  784.  
  785. if (WARN_ON(args->args[0] >= EXYNOS5_DRDPHYS_NUM))
  786. return ERR_PTR(-ENODEV);
  787.  
  788. return phy_drd->phys[args->args[0]].phy;
  789. }
  790.  
  791. static const struct phy_ops exynos5_usbdrd_phy_ops = {
  792. .init = exynos5_usbdrd_phy_init,
  793. .exit = exynos5_usbdrd_phy_exit,
  794. .power_on = exynos5_usbdrd_phy_power_on,
  795. .power_off = exynos5_usbdrd_phy_power_off,
  796. .owner = THIS_MODULE,
  797. };
  798.  
  799. static int exynos5_usbdrd_phy_clk_handle(struct exynos5_usbdrd_phy *phy_drd)
  800. {
  801. unsigned long ref_rate;
  802. int ret;
  803.  
  804. phy_drd->clk = devm_clk_get(phy_drd->dev, "phy");
  805. if (IS_ERR(phy_drd->clk)) {
  806. dev_err(phy_drd->dev, "Failed to get phy clock\n");
  807. return PTR_ERR(phy_drd->clk);
  808. }
  809.  
  810. phy_drd->ref_clk = devm_clk_get(phy_drd->dev, "ref");
  811. if (IS_ERR(phy_drd->ref_clk)) {
  812. dev_err(phy_drd->dev, "Failed to get phy reference clock\n");
  813. return PTR_ERR(phy_drd->ref_clk);
  814. }
  815. ref_rate = clk_get_rate(phy_drd->ref_clk);
  816.  
  817. ret = exynos5_rate_to_clk(ref_rate, &phy_drd->extrefclk);
  818. if (ret) {
  819. dev_err(phy_drd->dev, "Clock rate (%ld) not supported\n",
  820. ref_rate);
  821. return ret;
  822. }
  823.  
  824. if (!phy_drd->drv_data->has_common_clk_gate) {
  825. phy_drd->pipeclk = devm_clk_get(phy_drd->dev, "phy_pipe");
  826. if (IS_ERR(phy_drd->pipeclk)) {
  827. dev_info(phy_drd->dev,
  828. "PIPE3 phy operational clock not specified\n");
  829. phy_drd->pipeclk = NULL;
  830. }
  831.  
  832. phy_drd->utmiclk = devm_clk_get(phy_drd->dev, "phy_utmi");
  833. if (IS_ERR(phy_drd->utmiclk)) {
  834. dev_info(phy_drd->dev,
  835. "UTMI phy operational clock not specified\n");
  836. phy_drd->utmiclk = NULL;
  837. }
  838.  
  839. phy_drd->itpclk = devm_clk_get(phy_drd->dev, "itp");
  840. if (IS_ERR(phy_drd->itpclk)) {
  841. dev_info(phy_drd->dev,
  842. "ITP clock from main OSC not specified\n");
  843. phy_drd->itpclk = NULL;
  844. }
  845. }
  846.  
  847. return 0;
  848. }
  849.  
  850. static const struct exynos5_usbdrd_phy_config phy_cfg_exynos5[] = {
  851. {
  852. .id = EXYNOS5_DRDPHY_UTMI,
  853. .phy_isol = exynos5_usbdrd_phy_isol,
  854. .phy_init = exynos5_usbdrd_utmi_init,
  855. .set_refclk = exynos5_usbdrd_utmi_set_refclk,
  856. },
  857. {
  858. .id = EXYNOS5_DRDPHY_PIPE3,
  859. .phy_isol = exynos5_usbdrd_phy_isol,
  860. .phy_init = exynos5_usbdrd_pipe3_init,
  861. .set_refclk = exynos5_usbdrd_pipe3_set_refclk,
  862. .phy_calibrate = exynos5_usbdrd_pipe3_calibrate,
  863. },
  864. };
  865.  
  866. static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = {
  867. .phy_cfg = phy_cfg_exynos5,
  868. .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
  869. .pmu_offset_usbdrd1_phy = EXYNOS5420_USBDRD1_PHY_CONTROL,
  870. .phy_exynos_calibrate = exynos5420_usbdrd_phy_calibrate,
  871. .has_common_clk_gate = true,
  872. };
  873.  
  874. static const struct exynos5_usbdrd_phy_drvdata exynos5250_usbdrd_phy = {
  875. .phy_cfg = phy_cfg_exynos5,
  876. .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
  877. .has_common_clk_gate = true,
  878. };
  879.  
  880. static const struct exynos5_usbdrd_phy_drvdata exynos5433_usbdrd_phy = {
  881. .phy_cfg = phy_cfg_exynos5,
  882. .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
  883. .pmu_offset_usbdrd1_phy = EXYNOS5433_USBHOST30_PHY_CONTROL,
  884. .has_common_clk_gate = false,
  885. };
  886.  
  887. static const struct exynos5_usbdrd_phy_drvdata exynos7_usbdrd_phy = {
  888. .phy_cfg = phy_cfg_exynos5,
  889. .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
  890. .has_common_clk_gate = false,
  891. };
  892.  
  893. static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
  894. {
  895. .compatible = "samsung,exynos5250-usbdrd-phy",
  896. .data = &exynos5250_usbdrd_phy
  897. }, {
  898. .compatible = "samsung,exynos5420-usbdrd-phy",
  899. .data = &exynos5420_usbdrd_phy
  900. }, {
  901. .compatible = "samsung,exynos5433-usbdrd-phy",
  902. .data = &exynos5433_usbdrd_phy
  903. }, {
  904. .compatible = "samsung,exynos7-usbdrd-phy",
  905. .data = &exynos7_usbdrd_phy
  906. },
  907. { },
  908. };
  909. MODULE_DEVICE_TABLE(of, exynos5_usbdrd_phy_of_match);
  910.  
  911. static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
  912. {
  913. struct device *dev = &pdev->dev;
  914. struct device_node *node = dev->of_node;
  915. struct exynos5_usbdrd_phy *phy_drd;
  916. struct phy_provider *phy_provider;
  917. struct resource *res;
  918. const struct exynos5_usbdrd_phy_drvdata *drv_data;
  919. struct regmap *reg_pmu;
  920. u32 pmu_offset;
  921. int i, ret;
  922. int channel;
  923.  
  924. phy_drd = devm_kzalloc(dev, sizeof(*phy_drd), GFP_KERNEL);
  925. if (!phy_drd)
  926. return -ENOMEM;
  927.  
  928. dev_set_drvdata(dev, phy_drd);
  929. phy_drd->dev = dev;
  930.  
  931. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  932. phy_drd->reg_phy = devm_ioremap_resource(dev, res);
  933. if (IS_ERR(phy_drd->reg_phy))
  934. return PTR_ERR(phy_drd->reg_phy);
  935.  
  936. drv_data = of_device_get_match_data(dev);
  937. if (!drv_data)
  938. return -EINVAL;
  939.  
  940. phy_drd->drv_data = drv_data;
  941.  
  942. ret = exynos5_usbdrd_phy_clk_handle(phy_drd);
  943. if (ret) {
  944. dev_err(dev, "Failed to initialize clocks\n");
  945. return ret;
  946. }
  947.  
  948. reg_pmu = syscon_regmap_lookup_by_phandle(dev->of_node,
  949. "samsung,pmu-syscon");
  950. if (IS_ERR(reg_pmu)) {
  951. dev_err(dev, "Failed to lookup PMU regmap\n");
  952. return PTR_ERR(reg_pmu);
  953. }
  954.  
  955. /*
  956. * Exynos5420 SoC has multiple channels for USB 3.0 PHY, with
  957. * each having separate power control registers.
  958. * 'channel' facilitates to set such registers.
  959. */
  960. channel = of_alias_get_id(node, "usbdrdphy");
  961. if (channel < 0)
  962. dev_dbg(dev, "Not a multi-controller usbdrd phy\n");
  963.  
  964. switch (channel) {
  965. case 1:
  966. pmu_offset = phy_drd->drv_data->pmu_offset_usbdrd1_phy;
  967. break;
  968. case 0:
  969. default:
  970. pmu_offset = phy_drd->drv_data->pmu_offset_usbdrd0_phy;
  971. break;
  972. }
  973.  
  974. /* Get Vbus regulators */
  975. phy_drd->vbus = devm_regulator_get(dev, "vbus");
  976. if (IS_ERR(phy_drd->vbus)) {
  977. ret = PTR_ERR(phy_drd->vbus);
  978. if (ret == -EPROBE_DEFER)
  979. return ret;
  980.  
  981. dev_warn(dev, "Failed to get VBUS supply regulator\n");
  982. phy_drd->vbus = NULL;
  983. }
  984.  
  985. phy_drd->vbus_boost = devm_regulator_get(dev, "vbus-boost");
  986. if (IS_ERR(phy_drd->vbus_boost)) {
  987. ret = PTR_ERR(phy_drd->vbus_boost);
  988. if (ret == -EPROBE_DEFER)
  989. return ret;
  990.  
  991. dev_warn(dev, "Failed to get VBUS boost supply regulator\n");
  992. phy_drd->vbus_boost = NULL;
  993. }
  994.  
  995. dev_vdbg(dev, "Creating usbdrd_phy phy\n");
  996.  
  997. for (i = 0; i < EXYNOS5_DRDPHYS_NUM; i++) {
  998. struct phy *phy = devm_phy_create(dev, NULL,
  999. &exynos5_usbdrd_phy_ops);
  1000. if (IS_ERR(phy)) {
  1001. dev_err(dev, "Failed to create usbdrd_phy phy\n");
  1002. return PTR_ERR(phy);
  1003. }
  1004.  
  1005. phy_drd->phys[i].phy = phy;
  1006. phy_drd->phys[i].index = i;
  1007. phy_drd->phys[i].reg_pmu = reg_pmu;
  1008. phy_drd->phys[i].pmu_offset = pmu_offset;
  1009. phy_drd->phys[i].phy_cfg = &drv_data->phy_cfg[i];
  1010. phy_set_drvdata(phy, &phy_drd->phys[i]);
  1011. }
  1012.  
  1013. phy_provider = devm_of_phy_provider_register(dev,
  1014. exynos5_usbdrd_phy_xlate);
  1015. if (IS_ERR(phy_provider)) {
  1016. dev_err(phy_drd->dev, "Failed to register phy provider\n");
  1017. return PTR_ERR(phy_provider);
  1018. }
  1019.  
  1020. return 0;
  1021. }
  1022.  
  1023. static struct platform_driver exynos5_usb3drd_phy = {
  1024. .probe = exynos5_usbdrd_phy_probe,
  1025. .driver = {
  1026. .of_match_table = exynos5_usbdrd_phy_of_match,
  1027. .name = "exynos5_usb3drd_phy",
  1028. }
  1029. };
  1030.  
  1031. module_platform_driver(exynos5_usb3drd_phy);
  1032. MODULE_DESCRIPTION("Samsung EXYNOS5 SoCs USB 3.0 DRD controller PHY driver");
  1033. MODULE_AUTHOR("Vivek Gautam <gautam.vivek@samsung.com>");
  1034. MODULE_LICENSE("GPL v2");
  1035. MODULE_ALIAS("platform:exynos5_usb3drd_phy");
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