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  1. [piotro@minimyth-armv8 allwinner]$ cat sun50i-h6.dtsi
  2. // SPDX-License-Identifier: (GPL-2.0+ or MIT)
  3. /*
  4. * Copyright (C) 2017 Icenowy Zheng <[email protected]>
  5. */
  6.  
  7. #include <dt-bindings/interrupt-controller/arm-gic.h>
  8. #include <dt-bindings/clock/sun50i-h6-ccu.h>
  9. #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
  10. #include <dt-bindings/clock/sun8i-de2.h>
  11. #include <dt-bindings/clock/sun8i-tcon-top.h>
  12. #include <dt-bindings/reset/sun50i-h6-ccu.h>
  13. #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
  14. #include <dt-bindings/reset/sun8i-de2.h>
  15. #include <dt-bindings/thermal/thermal.h>
  16.  
  17. / {
  18. interrupt-parent = <&gic>;
  19. #address-cells = <1>;
  20. #size-cells = <1>;
  21.  
  22. ac200_pwm_clk: ac200_clk {
  23. compatible = "pwm-clock";
  24. #clock-cells = <0>;
  25. clock-frequency = <24000000>;
  26. pinctrl-names = "default";
  27. pinctrl-0 = <&pwm1_pin>;
  28. pwms = <&pwm 1 42 0>;
  29. };
  30.  
  31. cpus {
  32. #address-cells = <1>;
  33. #size-cells = <0>;
  34.  
  35. cpu0: cpu@0 {
  36. compatible = "arm,cortex-a53";
  37. device_type = "cpu";
  38. reg = <0>;
  39. enable-method = "psci";
  40. clocks = <&ccu CLK_CPUX>;
  41. clock-latency-ns = <244144>; /* 8 32k periods */
  42. operating-points-v2 = <&cpu_opp_table>;
  43. #cooling-cells = <2>;
  44. };
  45.  
  46. cpu1: cpu@1 {
  47. compatible = "arm,cortex-a53";
  48. device_type = "cpu";
  49. reg = <1>;
  50. enable-method = "psci";
  51. clocks = <&ccu CLK_CPUX>;
  52. clock-latency-ns = <244144>; /* 8 32k periods */
  53. operating-points-v2 = <&cpu_opp_table>;
  54. #cooling-cells = <2>;
  55. };
  56.  
  57. cpu2: cpu@2 {
  58. compatible = "arm,cortex-a53";
  59. device_type = "cpu";
  60. reg = <2>;
  61. enable-method = "psci";
  62. clocks = <&ccu CLK_CPUX>;
  63. clock-latency-ns = <244144>; /* 8 32k periods */
  64. operating-points-v2 = <&cpu_opp_table>;
  65. #cooling-cells = <2>;
  66. };
  67.  
  68. cpu3: cpu@3 {
  69. compatible = "arm,cortex-a53";
  70. device_type = "cpu";
  71. reg = <3>;
  72. enable-method = "psci";
  73. clocks = <&ccu CLK_CPUX>;
  74. clock-latency-ns = <244144>; /* 8 32k periods */
  75. operating-points-v2 = <&cpu_opp_table>;
  76. #cooling-cells = <2>;
  77. };
  78. };
  79.  
  80. cpu_opp_table: opp_table {
  81. compatible = "operating-points-v2";
  82. opp-shared;
  83.  
  84. opp@480000000 {
  85. opp-hz = /bits/ 64 <480000000>;
  86. opp-microvolt = <880000 880000 880000>;
  87. clock-latency-ns = <244144>; /* 8 32k periods */
  88. };
  89.  
  90. opp@720000000 {
  91. opp-hz = /bits/ 64 <720000000>;
  92. opp-microvolt = <880000 880000 880000>;
  93. clock-latency-ns = <244144>; /* 8 32k periods */
  94. };
  95.  
  96. opp@816000000 {
  97. opp-hz = /bits/ 64 <816000000>;
  98. opp-microvolt = <880000 880000 880000>;
  99. clock-latency-ns = <244144>; /* 8 32k periods */
  100. };
  101.  
  102. opp@888000000 {
  103. opp-hz = /bits/ 64 <888000000>;
  104. opp-microvolt = <880000 880000 880000>;
  105. clock-latency-ns = <244144>; /* 8 32k periods */
  106. };
  107.  
  108. opp@1080000000 {
  109. opp-hz = /bits/ 64 <1080000000>;
  110. opp-microvolt = <940000 940000 940000>;
  111. clock-latency-ns = <244144>; /* 8 32k periods */
  112. };
  113.  
  114. opp@1320000000 {
  115. opp-hz = /bits/ 64 <1320000000>;
  116. opp-microvolt = <1000000 1000000 1000000>;
  117. clock-latency-ns = <244144>; /* 8 32k periods */
  118. };
  119.  
  120. opp@1488000000 {
  121. opp-hz = /bits/ 64 <1488000000>;
  122. opp-microvolt = <1060000 1060000 1060000>;
  123. clock-latency-ns = <244144>; /* 8 32k periods */
  124. };
  125.  
  126. opp@1800000000 {
  127. opp-hz = /bits/ 64 <1800000000>;
  128. opp-microvolt = <1160000 1160000 1160000>;
  129. clock-latency-ns = <244144>; /* 8 32k periods */
  130. };
  131. };
  132.  
  133. de: display-engine {
  134. compatible = "allwinner,sun50i-h6-display-engine";
  135. allwinner,pipelines = <&mixer0>;
  136. status = "disabled";
  137. };
  138.  
  139. osc24M: osc24M_clk {
  140. #clock-cells = <0>;
  141. compatible = "fixed-clock";
  142. clock-frequency = <24000000>;
  143. clock-output-names = "osc24M";
  144. };
  145.  
  146. ext_osc32k: ext_osc32k_clk {
  147. #clock-cells = <0>;
  148. compatible = "fixed-clock";
  149. clock-frequency = <32768>;
  150. clock-output-names = "ext_osc32k";
  151. };
  152.  
  153. psci {
  154. compatible = "arm,psci-0.2";
  155. method = "smc";
  156. };
  157.  
  158. timer {
  159. compatible = "arm,armv8-timer";
  160. interrupts = <GIC_PPI 13
  161. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  162. <GIC_PPI 14
  163. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  164. <GIC_PPI 11
  165. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  166. <GIC_PPI 10
  167. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  168. };
  169.  
  170. sound_hdmi: sound {
  171. compatible = "simple-audio-card";
  172. simple-audio-card,format = "i2s";
  173. simple-audio-card,name = "allwinner-hdmi";
  174. simple-audio-card,mclk-fs = <256>;
  175.  
  176. simple-audio-card,codec {
  177. sound-dai = <&hdmi>;
  178. };
  179.  
  180. simple-audio-card,cpu {
  181. sound-dai = <&i2s1>;
  182. dai-tdm-slot-num = <2>;
  183. dai-tdm-slot-width = <32>;
  184. };
  185. };
  186.  
  187. soc {
  188. compatible = "simple-bus";
  189. #address-cells = <1>;
  190. #size-cells = <1>;
  191. ranges;
  192.  
  193. bus@1000000 {
  194. compatible = "allwinner,sun50i-h6-de3",
  195. "allwinner,sun50i-a64-de2";
  196. reg = <0x1000000 0x400000>;
  197. allwinner,sram = <&de2_sram 1>;
  198. #address-cells = <1>;
  199. #size-cells = <1>;
  200. ranges = <0 0x1000000 0x400000>;
  201.  
  202. display_clocks: clock@0 {
  203. compatible = "allwinner,sun50i-h6-de3-clk";
  204. reg = <0x0 0x10000>;
  205. clocks = <&ccu CLK_DE>,
  206. <&ccu CLK_BUS_DE>;
  207. clock-names = "mod",
  208. "bus";
  209. resets = <&ccu RST_BUS_DE>;
  210. #clock-cells = <1>;
  211. #reset-cells = <1>;
  212. };
  213.  
  214. mixer0: mixer@100000 {
  215. compatible = "allwinner,sun50i-h6-de3-mixer-0";
  216. reg = <0x100000 0x100000>;
  217. clocks = <&display_clocks CLK_BUS_MIXER0>,
  218. <&display_clocks CLK_MIXER0>;
  219. clock-names = "bus",
  220. "mod";
  221. resets = <&display_clocks RST_MIXER0>;
  222.  
  223. ports {
  224. #address-cells = <1>;
  225. #size-cells = <0>;
  226.  
  227. mixer0_out: port@1 {
  228. reg = <1>;
  229.  
  230. mixer0_out_tcon_top_mixer0: endpoint {
  231. remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
  232. };
  233. };
  234. };
  235. };
  236. };
  237.  
  238. video-codec@1c0e000 {
  239. compatible = "allwinner,sun50i-h6-video-engine";
  240. reg = <0x01c0e000 0x2000>;
  241. clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
  242. <&ccu CLK_MBUS_VE>;
  243. clock-names = "ahb", "mod", "ram";
  244. resets = <&ccu RST_BUS_VE>;
  245. interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
  246. allwinner,sram = <&ve_sram 1>;
  247. };
  248.  
  249. gpu: gpu@1800000 {
  250. compatible = "allwinner,sun50i-h6-mali",
  251. "arm,mali-t720";
  252. reg = <0x01800000 0x4000>;
  253. interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
  254. <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
  255. <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  256. interrupt-names = "job", "mmu", "gpu";
  257. clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
  258. clock-names = "core", "bus";
  259. resets = <&ccu RST_BUS_GPU>;
  260. status = "disabled";
  261. };
  262.  
  263. syscon: syscon@3000000 {
  264. compatible = "allwinner,sun50i-h6-system-control",
  265. "allwinner,sun50i-a64-system-control";
  266. reg = <0x03000000 0x1000>;
  267. #address-cells = <1>;
  268. #size-cells = <1>;
  269. ranges;
  270.  
  271. sram_c: sram@28000 {
  272. compatible = "mmio-sram";
  273. reg = <0x00028000 0x1e000>;
  274. #address-cells = <1>;
  275. #size-cells = <1>;
  276. ranges = <0 0x00028000 0x1e000>;
  277.  
  278. de2_sram: sram-section@0 {
  279. compatible = "allwinner,sun50i-h6-sram-c",
  280. "allwinner,sun50i-a64-sram-c";
  281. reg = <0x0000 0x1e000>;
  282. };
  283. };
  284.  
  285. sram_c1: sram@1a00000 {
  286. compatible = "mmio-sram";
  287. reg = <0x01a00000 0x200000>;
  288. #address-cells = <1>;
  289. #size-cells = <1>;
  290. ranges = <0 0x01a00000 0x200000>;
  291.  
  292. ve_sram: sram-section@0 {
  293. compatible = "allwinner,sun50i-h6-sram-c1",
  294. "allwinner,sun4i-a10-sram-c1";
  295. reg = <0x000000 0x200000>;
  296. };
  297. };
  298. };
  299.  
  300. ccu: clock@3001000 {
  301. compatible = "allwinner,sun50i-h6-ccu";
  302. reg = <0x03001000 0x1000>;
  303. clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
  304. clock-names = "hosc", "losc", "iosc";
  305. #clock-cells = <1>;
  306. #reset-cells = <1>;
  307. };
  308.  
  309. dma: dma-controller@3002000 {
  310. compatible = "allwinner,sun50i-h6-dma";
  311. reg = <0x03002000 0x1000>;
  312. interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
  313. clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
  314. clock-names = "bus", "mbus";
  315. dma-channels = <16>;
  316. dma-requests = <46>;
  317. resets = <&ccu RST_BUS_DMA>;
  318. #dma-cells = <1>;
  319. };
  320.  
  321. sid: sid@3006000 {
  322. compatible = "allwinner,sun50i-h6-sid";
  323. reg = <0x03006000 0x400>;
  324. #address-cells = <1>;
  325. #size-cells = <1>;
  326.  
  327. ephy_calib: ephy_calib@2c {
  328. reg = <0x2c 0x2>;
  329. };
  330.  
  331. ths_calibration: thermal-sensor-calibration@14 {
  332. reg = <0x14 0x6>;
  333. };
  334. };
  335.  
  336. watchdog: watchdog@30090a0 {
  337. compatible = "allwinner,sun50i-h6-wdt",
  338. "allwinner,sun6i-a31-wdt";
  339. reg = <0x030090a0 0x20>;
  340. interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
  341. /* Broken on some H6 boards */
  342. status = "disabled";
  343. };
  344.  
  345. pwm: pwm@300a000 {
  346. compatible = "allwinner,sun50i-h6-pwm";
  347. reg = <0x0300a000 0x400>;
  348. clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
  349. clock-names = "pwm", "bus";
  350. resets = <&ccu RST_BUS_PWM>;
  351. #pwm-cells = <3>;
  352. status = "disabled";
  353. };
  354.  
  355. pio: pinctrl@300b000 {
  356. compatible = "allwinner,sun50i-h6-pinctrl";
  357. reg = <0x0300b000 0x400>;
  358. interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
  359. <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
  360. <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
  361. <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
  362. clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
  363. clock-names = "apb", "hosc", "losc";
  364. gpio-controller;
  365. #gpio-cells = <3>;
  366. interrupt-controller;
  367. #interrupt-cells = <3>;
  368.  
  369. ext_rgmii_pins: rgmii-pins {
  370. pins = "PD0", "PD1", "PD2", "PD3", "PD4",
  371. "PD5", "PD7", "PD8", "PD9", "PD10",
  372. "PD11", "PD12", "PD13", "PD19", "PD20";
  373. function = "emac";
  374. drive-strength = <40>;
  375. };
  376.  
  377. ext_rmii_pins: rmii_pins {
  378. pins = "PA0", "PA1", "PA2", "PA3", "PA4",
  379. "PA5", "PA6", "PA7", "PA8", "PA9";
  380. function = "emac";
  381. drive-strength = <40>;
  382. };
  383.  
  384. hdmi_pins: hdmi-pins {
  385. pins = "PH8", "PH9", "PH10";
  386. function = "hdmi";
  387. };
  388.  
  389. mmc0_pins: mmc0-pins {
  390. pins = "PF0", "PF1", "PF2", "PF3",
  391. "PF4", "PF5";
  392. function = "mmc0";
  393. drive-strength = <30>;
  394. bias-pull-up;
  395. };
  396.  
  397. /omit-if-no-ref/
  398. mmc1_pins: mmc1-pins {
  399. pins = "PG0", "PG1", "PG2", "PG3",
  400. "PG4", "PG5";
  401. function = "mmc1";
  402. drive-strength = <30>;
  403. bias-pull-up;
  404. };
  405.  
  406. mmc2_pins: mmc2-pins {
  407. pins = "PC1", "PC4", "PC5", "PC6",
  408. "PC7", "PC8", "PC9", "PC10",
  409. "PC11", "PC12", "PC13", "PC14";
  410. function = "mmc2";
  411. drive-strength = <30>;
  412. bias-pull-up;
  413. };
  414.  
  415. uart0_ph_pins: uart0-ph-pins {
  416. pins = "PH0", "PH1";
  417. function = "uart0";
  418. };
  419.  
  420. i2c3_pins: i2c3-pins {
  421. pins = "PB17", "PB18";
  422. function = "i2c3";
  423. };
  424.  
  425. pwm1_pin: pwm1-pin {
  426. pins = "PB19";
  427. function = "pwm1";
  428. };
  429. };
  430.  
  431. gic: interrupt-controller@3021000 {
  432. compatible = "arm,gic-400";
  433. reg = <0x03021000 0x1000>,
  434. <0x03022000 0x2000>,
  435. <0x03024000 0x2000>,
  436. <0x03026000 0x2000>;
  437. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  438. interrupt-controller;
  439. #interrupt-cells = <3>;
  440. };
  441.  
  442. mmc0: mmc@4020000 {
  443. compatible = "allwinner,sun50i-h6-mmc",
  444. "allwinner,sun50i-a64-mmc";
  445. reg = <0x04020000 0x1000>;
  446. clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
  447. clock-names = "ahb", "mmc";
  448. resets = <&ccu RST_BUS_MMC0>;
  449. reset-names = "ahb";
  450. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  451. pinctrl-names = "default";
  452. pinctrl-0 = <&mmc0_pins>;
  453. status = "disabled";
  454. #address-cells = <1>;
  455. #size-cells = <0>;
  456. };
  457.  
  458. mmc1: mmc@4021000 {
  459. compatible = "allwinner,sun50i-h6-mmc",
  460. "allwinner,sun50i-a64-mmc";
  461. reg = <0x04021000 0x1000>;
  462. clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
  463. clock-names = "ahb", "mmc";
  464. resets = <&ccu RST_BUS_MMC1>;
  465. reset-names = "ahb";
  466. interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  467. pinctrl-names = "default";
  468. pinctrl-0 = <&mmc1_pins>;
  469. status = "disabled";
  470. #address-cells = <1>;
  471. #size-cells = <0>;
  472. };
  473.  
  474. mmc2: mmc@4022000 {
  475. compatible = "allwinner,sun50i-h6-emmc",
  476. "allwinner,sun50i-a64-emmc";
  477. reg = <0x04022000 0x1000>;
  478. clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
  479. clock-names = "ahb", "mmc";
  480. resets = <&ccu RST_BUS_MMC2>;
  481. reset-names = "ahb";
  482. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  483. pinctrl-names = "default";
  484. pinctrl-0 = <&mmc2_pins>;
  485. status = "disabled";
  486. #address-cells = <1>;
  487. #size-cells = <0>;
  488. };
  489.  
  490. uart0: serial@5000000 {
  491. compatible = "snps,dw-apb-uart";
  492. reg = <0x05000000 0x400>;
  493. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  494. reg-shift = <2>;
  495. reg-io-width = <4>;
  496. clocks = <&ccu CLK_BUS_UART0>;
  497. resets = <&ccu RST_BUS_UART0>;
  498. status = "disabled";
  499. };
  500.  
  501. uart1: serial@5000400 {
  502. compatible = "snps,dw-apb-uart";
  503. reg = <0x05000400 0x400>;
  504. interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  505. reg-shift = <2>;
  506. reg-io-width = <4>;
  507. clocks = <&ccu CLK_BUS_UART1>;
  508. resets = <&ccu RST_BUS_UART1>;
  509. status = "disabled";
  510. };
  511.  
  512. uart2: serial@5000800 {
  513. compatible = "snps,dw-apb-uart";
  514. reg = <0x05000800 0x400>;
  515. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  516. reg-shift = <2>;
  517. reg-io-width = <4>;
  518. clocks = <&ccu CLK_BUS_UART2>;
  519. resets = <&ccu RST_BUS_UART2>;
  520. status = "disabled";
  521. };
  522.  
  523. uart3: serial@5000c00 {
  524. compatible = "snps,dw-apb-uart";
  525. reg = <0x05000c00 0x400>;
  526. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  527. reg-shift = <2>;
  528. reg-io-width = <4>;
  529. clocks = <&ccu CLK_BUS_UART3>;
  530. resets = <&ccu RST_BUS_UART3>;
  531. status = "disabled";
  532. };
  533.  
  534. i2c3: i2c@5002c00 {
  535. compatible = "allwinner,sun6i-a31-i2c";
  536. reg = <0x05002c00 0x400>;
  537. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  538. clocks = <&ccu CLK_BUS_I2C3>;
  539. resets = <&ccu RST_BUS_I2C3>;
  540. pinctrl-names = "default";
  541. pinctrl-0 = <&i2c3_pins>;
  542. #address-cells = <1>;
  543. #size-cells = <0>;
  544.  
  545. ac200: mfd@10 {
  546. compatible = "x-powers,ac200";
  547. reg = <0x10>;
  548. clocks = <&ac200_pwm_clk>;
  549.  
  550. ac200_ephy: phy {
  551. compatible = "x-powers,ac200-ephy";
  552. nvmem-cells = <&ephy_calib>;
  553. nvmem-cell-names = "ephy_calib";
  554. };
  555. };
  556. };
  557.  
  558. emac: ethernet@5020000 {
  559. compatible = "allwinner,sun50i-h6-emac",
  560. "allwinner,sun50i-a64-emac";
  561. syscon = <&syscon>;
  562. reg = <0x05020000 0x10000>;
  563. interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  564. interrupt-names = "macirq";
  565. resets = <&ccu RST_BUS_EMAC>;
  566. reset-names = "stmmaceth";
  567. clocks = <&ccu CLK_BUS_EMAC>;
  568. clock-names = "stmmaceth";
  569. status = "disabled";
  570.  
  571. mdio: mdio {
  572. compatible = "snps,dwmac-mdio";
  573. #address-cells = <1>;
  574. #size-cells = <0>;
  575. };
  576. };
  577.  
  578. i2s1: i2s@5091000 {
  579. #sound-dai-cells = <0>;
  580. compatible = "allwinner,sun8i-h3-i2s";
  581. reg = <0x05091000 0x1000>;
  582. interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  583. clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
  584. clock-names = "apb", "mod";
  585. dmas = <&dma 4>, <&dma 4>;
  586. resets = <&ccu RST_BUS_I2S1>;
  587. dma-names = "rx", "tx";
  588. };
  589.  
  590. usb2otg: usb@5100000 {
  591. compatible = "allwinner,sun50i-h6-musb",
  592. "allwinner,sun8i-a33-musb";
  593. reg = <0x05100000 0x0400>;
  594. clocks = <&ccu CLK_BUS_OTG>;
  595. resets = <&ccu RST_BUS_OTG>;
  596. interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  597. interrupt-names = "mc";
  598. phys = <&usb2phy 0>;
  599. phy-names = "usb";
  600. extcon = <&usb2phy 0>;
  601. status = "disabled";
  602. };
  603.  
  604. usb2phy: phy@5100400 {
  605. compatible = "allwinner,sun50i-h6-usb-phy";
  606. reg = <0x05100400 0x24>,
  607. <0x05101800 0x4>,
  608. <0x05311800 0x4>;
  609. reg-names = "phy_ctrl",
  610. "pmu0",
  611. "pmu3";
  612. clocks = <&ccu CLK_USB_PHY0>,
  613. <&ccu CLK_USB_PHY3>;
  614. clock-names = "usb0_phy",
  615. "usb3_phy";
  616. resets = <&ccu RST_USB_PHY0>,
  617. <&ccu RST_USB_PHY3>;
  618. reset-names = "usb0_reset",
  619. "usb3_reset";
  620. status = "disabled";
  621. #phy-cells = <1>;
  622. };
  623.  
  624. ehci0: usb@5101000 {
  625. compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
  626. reg = <0x05101000 0x100>;
  627. interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
  628. clocks = <&ccu CLK_BUS_OHCI0>,
  629. <&ccu CLK_BUS_EHCI0>,
  630. <&ccu CLK_USB_OHCI0>;
  631. resets = <&ccu RST_BUS_OHCI0>,
  632. <&ccu RST_BUS_EHCI0>;
  633. status = "disabled";
  634. };
  635.  
  636. ohci0: usb@5101400 {
  637. compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
  638. reg = <0x05101400 0x100>;
  639. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  640. clocks = <&ccu CLK_BUS_OHCI0>,
  641. <&ccu CLK_USB_OHCI0>;
  642. resets = <&ccu RST_BUS_OHCI0>;
  643. status = "disabled";
  644. };
  645.  
  646. dwc3: dwc3@5200000 {
  647. compatible = "snps,dwc3";
  648. reg = <0x05200000 0x10000>;
  649. interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  650. clocks = <&ccu CLK_BUS_XHCI>,
  651. <&ccu CLK_BUS_XHCI>,
  652. <&ext_osc32k>;
  653. clock-names = "ref", "bus_early", "suspend";
  654. resets = <&ccu RST_BUS_XHCI>;
  655. /*
  656. * The datasheet of the chip doesn't declare the
  657. * peripheral function, and there's no boards known
  658. * to have a USB Type-B port routed to the port.
  659. * In addition, no one has tested the peripheral
  660. * function yet.
  661. * So set the dr_mode to "host" in the DTSI file.
  662. */
  663. dr_mode = "host";
  664. phys = <&usb3phy>;
  665. phy-names = "usb3-phy";
  666. status = "disabled";
  667. };
  668.  
  669. usb3phy: phy@5210000 {
  670. compatible = "allwinner,sun50i-h6-usb3-phy";
  671. reg = <0x5210000 0x10000>;
  672. clocks = <&ccu CLK_USB_PHY1>;
  673. resets = <&ccu RST_USB_PHY1>;
  674. #phy-cells = <0>;
  675. status = "disabled";
  676. };
  677.  
  678. ehci3: usb@5311000 {
  679. compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
  680. reg = <0x05311000 0x100>;
  681. interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  682. clocks = <&ccu CLK_BUS_OHCI3>,
  683. <&ccu CLK_BUS_EHCI3>,
  684. <&ccu CLK_USB_OHCI3>;
  685. resets = <&ccu RST_BUS_OHCI3>,
  686. <&ccu RST_BUS_EHCI3>;
  687. phys = <&usb2phy 3>;
  688. status = "disabled";
  689. };
  690.  
  691. ohci3: usb@5311400 {
  692. compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
  693. reg = <0x05311400 0x100>;
  694. interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  695. clocks = <&ccu CLK_BUS_OHCI3>,
  696. <&ccu CLK_USB_OHCI3>;
  697. resets = <&ccu RST_BUS_OHCI3>;
  698. phys = <&usb2phy 3>;
  699. status = "disabled";
  700. };
  701.  
  702. hdmi: hdmi@6000000 {
  703. #sound-dai-cells = <0>;
  704. compatible = "allwinner,sun50i-h6-dw-hdmi";
  705. reg = <0x06000000 0x10000>;
  706. reg-io-width = <1>;
  707. interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
  708. clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
  709. <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
  710. <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
  711. clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
  712. "hdcp-bus";
  713. resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
  714. reset-names = "ctrl", "hdcp";
  715. phys = <&hdmi_phy>;
  716. phy-names = "hdmi-phy";
  717. pinctrl-names = "default";
  718. pinctrl-0 = <&hdmi_pins>;
  719. status = "disabled";
  720.  
  721. ports {
  722. #address-cells = <1>;
  723. #size-cells = <0>;
  724.  
  725. hdmi_in: port@0 {
  726. reg = <0>;
  727.  
  728. hdmi_in_tcon_top: endpoint {
  729. remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
  730. };
  731. };
  732.  
  733. hdmi_out: port@1 {
  734. reg = <1>;
  735. };
  736. };
  737. };
  738.  
  739. hdmi_phy: hdmi-phy@6010000 {
  740. compatible = "allwinner,sun50i-h6-hdmi-phy";
  741. reg = <0x06010000 0x10000>;
  742. clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
  743. clock-names = "bus", "mod";
  744. resets = <&ccu RST_BUS_HDMI>;
  745. reset-names = "phy";
  746. #phy-cells = <0>;
  747. };
  748.  
  749. tcon_top: tcon-top@6510000 {
  750. compatible = "allwinner,sun50i-h6-tcon-top";
  751. reg = <0x06510000 0x1000>;
  752. clocks = <&ccu CLK_BUS_TCON_TOP>,
  753. <&ccu CLK_TCON_TV0>;
  754. clock-names = "bus",
  755. "tcon-tv0";
  756. clock-output-names = "tcon-top-tv0";
  757. resets = <&ccu RST_BUS_TCON_TOP>;
  758. reset-names = "rst";
  759. #clock-cells = <1>;
  760.  
  761. ports {
  762. #address-cells = <1>;
  763. #size-cells = <0>;
  764.  
  765. tcon_top_mixer0_in: port@0 {
  766. #address-cells = <1>;
  767. #size-cells = <0>;
  768. reg = <0>;
  769.  
  770. tcon_top_mixer0_in_mixer0: endpoint@0 {
  771. reg = <0>;
  772. remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
  773. };
  774. };
  775.  
  776. tcon_top_mixer0_out: port@1 {
  777. #address-cells = <1>;
  778. #size-cells = <0>;
  779. reg = <1>;
  780.  
  781. tcon_top_mixer0_out_tcon_tv: endpoint@2 {
  782. reg = <2>;
  783. remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
  784. };
  785. };
  786.  
  787. tcon_top_hdmi_in: port@4 {
  788. #address-cells = <1>;
  789. #size-cells = <0>;
  790. reg = <4>;
  791.  
  792. tcon_top_hdmi_in_tcon_tv: endpoint@0 {
  793. reg = <0>;
  794. remote-endpoint = <&tcon_tv_out_tcon_top>;
  795. };
  796. };
  797.  
  798. tcon_top_hdmi_out: port@5 {
  799. reg = <5>;
  800.  
  801. tcon_top_hdmi_out_hdmi: endpoint {
  802. remote-endpoint = <&hdmi_in_tcon_top>;
  803. };
  804. };
  805. };
  806. };
  807.  
  808. tcon_tv: lcd-controller@6515000 {
  809. compatible = "allwinner,sun50i-h6-tcon-tv",
  810. "allwinner,sun8i-r40-tcon-tv";
  811. reg = <0x06515000 0x1000>;
  812. interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
  813. clocks = <&ccu CLK_BUS_TCON_TV0>,
  814. <&tcon_top CLK_TCON_TOP_TV0>;
  815. clock-names = "ahb",
  816. "tcon-ch1";
  817. resets = <&ccu RST_BUS_TCON_TV0>;
  818. reset-names = "lcd";
  819.  
  820. ports {
  821. #address-cells = <1>;
  822. #size-cells = <0>;
  823.  
  824. tcon_tv_in: port@0 {
  825. reg = <0>;
  826.  
  827. tcon_tv_in_tcon_top_mixer0: endpoint {
  828. remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
  829. };
  830. };
  831.  
  832. tcon_tv_out: port@1 {
  833. #address-cells = <1>;
  834. #size-cells = <0>;
  835. reg = <1>;
  836.  
  837. tcon_tv_out_tcon_top: endpoint@1 {
  838. reg = <1>;
  839. remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
  840. };
  841. };
  842. };
  843. };
  844.  
  845. rtc: rtc@7000000 {
  846. compatible = "allwinner,sun50i-h6-rtc";
  847. reg = <0x07000000 0x400>;
  848. interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
  849. <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
  850. clock-output-names = "osc32k", "osc32k-out", "iosc";
  851. clocks = <&ext_osc32k>;
  852. #clock-cells = <1>;
  853. };
  854.  
  855. r_ccu: clock@7010000 {
  856. compatible = "allwinner,sun50i-h6-r-ccu";
  857. reg = <0x07010000 0x400>;
  858. clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
  859. <&ccu CLK_PLL_PERIPH0>;
  860. clock-names = "hosc", "losc", "iosc", "pll-periph";
  861. #clock-cells = <1>;
  862. #reset-cells = <1>;
  863. };
  864.  
  865. r_watchdog: watchdog@7020400 {
  866. compatible = "allwinner,sun50i-h6-wdt",
  867. "allwinner,sun6i-a31-wdt";
  868. reg = <0x07020400 0x20>;
  869. interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
  870. };
  871.  
  872. r_intc: interrupt-controller@7021000 {
  873. compatible = "allwinner,sun50i-h6-r-intc",
  874. "allwinner,sun6i-a31-r-intc";
  875. interrupt-controller;
  876. #interrupt-cells = <2>;
  877. reg = <0x07021000 0x400>;
  878. interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  879. };
  880.  
  881. r_pio: pinctrl@7022000 {
  882. compatible = "allwinner,sun50i-h6-r-pinctrl";
  883. reg = <0x07022000 0x400>;
  884. interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
  885. <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
  886. clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
  887. clock-names = "apb", "hosc", "losc";
  888. gpio-controller;
  889. #gpio-cells = <3>;
  890. interrupt-controller;
  891. #interrupt-cells = <3>;
  892.  
  893. r_i2c_pins: r-i2c-pins {
  894. pins = "PL0", "PL1";
  895. function = "s_i2c";
  896. };
  897.  
  898. r_ir_rx_pin: r-ir-rx-pin {
  899. pins = "PL9";
  900. function = "s_cir_rx";
  901. };
  902. };
  903.  
  904. r_ir: ir@7040000 {
  905. compatible = "allwinner,sun50i-h6-ir",
  906. "allwinner,sun6i-a31-ir";
  907. reg = <0x07040000 0x400>;
  908. interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
  909. clocks = <&r_ccu CLK_R_APB1_IR>,
  910. <&r_ccu CLK_IR>;
  911. clock-names = "apb", "ir";
  912. resets = <&r_ccu RST_R_APB1_IR>;
  913. pinctrl-names = "default";
  914. pinctrl-0 = <&r_ir_rx_pin>;
  915. status = "disabled";
  916. };
  917.  
  918. r_i2c: i2c@7081400 {
  919. compatible = "allwinner,sun6i-a31-i2c";
  920. reg = <0x07081400 0x400>;
  921. interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
  922. clocks = <&r_ccu CLK_R_APB2_I2C>;
  923. resets = <&r_ccu RST_R_APB2_I2C>;
  924. pinctrl-names = "default";
  925. pinctrl-0 = <&r_i2c_pins>;
  926. status = "disabled";
  927. #address-cells = <1>;
  928. #size-cells = <0>;
  929. };
  930.  
  931. ths: ths@5070400 {
  932. compatible = "allwinner,sun50i-h6-ths";
  933. reg = <0x05070400 0x100>;
  934. interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
  935. clocks = <&ccu CLK_BUS_THS>;
  936. clock-names = "bus";
  937. resets = <&ccu RST_BUS_THS>;
  938. nvmem-cells = <&ths_calibration>;
  939. nvmem-cell-names = "calibration";
  940. #thermal-sensor-cells = <1>;
  941. };
  942. };
  943.  
  944. thermal-zones {
  945. cpu-thermal {
  946. polling-delay-passive = <0>;
  947. polling-delay = <0>;
  948. thermal-sensors = <&ths 0>;
  949.  
  950. trips {
  951. cpu_hot_trip: cpu-hot {
  952. temperature = <80000>;
  953. hysteresis = <2000>;
  954. type = "passive";
  955. };
  956.  
  957. cpu_very_hot_trip: cpu-very-hot {
  958. temperature = <100000>;
  959. hysteresis = <0>;
  960. type = "critical";
  961. };
  962. };
  963.  
  964. cooling-maps {
  965. cpu-hot-limit {
  966. trip = <&cpu_hot_trip>;
  967. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  968. <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  969. <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  970. <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  971. };
  972. };
  973. };
  974.  
  975. gpu-thermal {
  976. polling-delay-passive = <0>;
  977. polling-delay = <0>;
  978. thermal-sensors = <&ths 1>;
  979. };
  980. };
  981. };
  982. [piotro@minimyth-armv8 allwinner]$
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