module Nor2(inp1,inp2,outp);
  input inp1,inp2;
  output outp;
  reg outp;
  assign #5 outp = ~(inp1 | inp2);
endmodule;

module Nor3(inp1,inp2,inp3,outp);
  input inp1,inp2,inp3;
  output outp;
  reg outp;
  assign #5 outp = ~(inp1 | inp2 | inp3);
endmodule;

module inventor(inp,outp);
  input inp;
  output outp;
  reg outp;
  assign #5 outp = ~inp;
endmodule;

module JK(J, K, C, Q, nQ);
  input J, K, C;
  output Q, nQ;
  wire nor1, nor2, nor3, nor4, nor11, nor12, nor13, nor14, inv;
  reg Q, nQ;

  Nor3 noru1(nQ,J,inv,nor1);
  Nor3 nord11(Q,K,inv,nor11);
  Nor2 noru2(nor1,nor12,nor2);
  Nor2 nord12(nor11,nor2,nor12);
  Nor2 noru3(nor3,C,nor3);
  Nor2 nord13(nor13,C,nor13);
  Nor2 noru4(nor4,nor14,nor4);
  Nor2 nord14(nor14,nor4,nor14);
  inventor inv1(C,inv);

endmodule;