ex6_44

module MUX2_1(output reg Y,input I0,I1,Sel);
    always @(I0,I1,Sel)
        if(Sel) Y=I1;
        else Y=I0;
endmodule

module FA(output reg carry,sum,input a,b,c_in);
    always @(a,b,c_in)
        {carry,sum}=a+b+c_in;
endmodule

module DFF(output reg Q,input D,Clk,Reset);
    always @(posedge Clk,negedge Reset)
        if(Reset==0) Q<=0;
        else Q<=D;

endmodule

module DFF_Clock(output Q,input D,Shift_Control,Clk,Reset);

    MUX2_1 m0(w0,Q,D,Shift_Control);
    DFF m1(Q,w0,Clk,Reset);

endmodule

module Shift_Register(output SO, output reg[3:0] Y ,input[3:0] data, input SI, Load, Shift_Control,Clk,Reset);
    assign SO=Y[0];
    always @(posedge Clk,negedge Reset)
        if(Reset==0) Y<=0;
        else if (Load) Y<=data;
        else if (Shift_Control) Y<={SI,Y[3:1]};

endmodule

module ex6_44(output SO,output[3:0] sregA,sregB,
    input[3:0] data_A,data_B,input Load,Shift_Control,Clk,Reset);
    wire SO_A,SO_B;
    wire carry,sum;
    supply0 gnd;
    assign SO=sum;
    wire Q;

    Shift_Register MA(SO_A,sregA,data_A,sum,Load,Shift_Control,Clk,Reset);
    Shift_Register MB(SO_B,sregB,data_B,gnd,Load,Shift_Control,Clk,Reset);

    FA m0(carry,sum,SO_A,SO_B,Q);
    DFF_Clock m1(Q,carry,Shift_Control,Clk,Reset);
endmodule

//sregAB for Debug
module t_ex6_44();
    wire SO;
    wire[3:0] sregA,sregB;
    reg[3:0] data_A,data_B;
    reg Load,Shift_Control,Clk,Reset;

    ex6_44 m0(SO,sregA,sregB,data_A,data_B,Load,Shift_Control,Clk,Reset);

    initial begin Clk=0;forever #5 Clk=~Clk; end

    initial fork
        data_A=4'b1100;
        data_B=4'b0101;
        Load=0;
        Shift_Control=0;
        #2 Reset=0;
        #4 Reset=1;
        #20 Load=1;
        #30 Load=0;
        #50 Shift_Control=1;
        #90 Shift_Control=0;
        #100 $finish;
    join


endmodule