counter_tb.v

`include "counter.v"
`timescale 1us/1us
module counter_tb;

   // on testbenches, inputs are regs
   reg clk;
   reg en;
   reg rst;

   // on testbenches, outputs are wires
   wire [3:0] out;

   counter BLK1 (clk, rst, en, out);

   initial begin
      rst = 0;        en = 0;          clk = 0;
      #1 rst = 1;     #1 rst = 0;      #1;
      #2 en = 1;      #2;              #2 en = 0;
      #2;             #2 en = 1;       #2 en = 0;
      #2 $finish;

   end // initial begin

   always #1 clk = ~clk;

   initial begin
      $monitor ("%t | rst = %d | clk = %d | en = %d | out = %d", $time, rst, clk, en, out);
      $dumpfile("dump.vcd");
      $dumpvars();
   end // initial begin
endmodule