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N64 Memory Map

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Aug 30th, 2017
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  1. ***********************************************************************
  2. ************************* MEMORY MAP OVERVIEW ***********************
  3. ***********************************************************************
  4.  
  5. 0x0000 0000 to 0x03EF FFFF RDRAM Memory
  6. 0x03F0 0000 to 0x03FF FFFF RDRAM Registers
  7. 0x0400 0000 to 0x040F FFFF SP Registers
  8. 0x0410 0000 to 0x041F FFFF DP Command Registers
  9. 0x0420 0000 to 0x042F FFFF DP Span Registers
  10. 0x0430 0000 to 0x043F FFFF MIPS Interface (MI) Registers
  11. 0x0440 0000 to 0x044F FFFF Video Interface (VI) Registers
  12. 0x0450 0000 to 0x045F FFFF Audio Interface (AI) Registers
  13. 0x0460 0000 to 0x046F FFFF Peripheral Interface (PI) Registers
  14. 0x0470 0000 to 0x047F FFFF RDRAM Interface (RI) Registers
  15. 0x0480 0000 to 0x048F FFFF Serial Interface (SI) Registers
  16. 0x0490 0000 to 0x04FF FFFF Unused
  17. 0x0500 0000 to 0x05FF FFFF Cartridge Domain 2 Address 1
  18. 0x0600 0000 to 0x07FF FFFF Cartridge Domain 1 Address 1
  19. 0x0800 0000 to 0x0FFF FFFF Cartridge Domain 2 Address 2
  20. 0x1000 0000 to 0x1FBF FFFF Cartridge Domain 1 Address 2
  21. 0x1FC0 0000 to 0x1FC0 07BF PIF Boot ROM
  22. 0x1FC0 07C0 to 0x1FC0 07FF PIF RAM
  23. 0x1FC0 0800 to 0x1FCF FFFF Reserved
  24. 0x1FD0 0000 to 0x7FFF FFFF Cartridge Domain 1 Address 3
  25. 0x8000 0000 to 0xFFFF FFFF External SysAD Device
  26.  
  27. ***********************************************************************
  28. ************************* MEMORY MAP DETAILED ***********************
  29. ***********************************************************************
  30.  
  31. 0x0000 0000 to 0x03EF FFFF RDRAM memory:
  32. -----------------------------------------
  33. 0x0000 0000 to 0x001F FFFF RDRAM range 0
  34. 0x0020 0000 to 0x003F FFFF RDRAM range 1
  35. 0x0040 0000 to 0x03EF FFFF Unused
  36.  
  37. 0x03F0 0000 to 0x03FF FFFF RDRAM registers:
  38. --------------------------------------------
  39. RDRAM_BASE_REG - 0x03F00000
  40.  
  41. 0x03F0 0000 to 0x03F0 0003 RDRAM_CONFIG_REG or
  42. RDRAM_DEVICE_TYPE_REG
  43. 0x03F0 0004 to 0x03F0 0007 RDRAM_DEVICE_ID_REG
  44. 0x03F0 0008 to 0x03F0 000B RDRAM_DELAY_REG
  45. 0x03F0 000C to 0x03F0 000F RDRAM_MODE_REG
  46. 0x03F0 0010 to 0x03F0 0013 RDRAM_REF_INTERVAL_REG
  47. 0x03F0 0014 to 0x03F0 0017 RDRAM_REF_ROW_REG
  48. 0x03F0 0018 to 0x03F0 001B RDRAM_RAS_INTERVAL_REG
  49. 0x03F0 001C to 0x03F0 001F RDRAM_MIN_INTERVAL_REG
  50. 0x03F0 0020 to 0x03F0 0023 RDRAM_ADDR_SELECT_REG
  51. 0x03F0 0024 to 0x03F0 0027 RDRAM_DEVICE_MANUF_REG
  52. 0x03F0 0028 to 0x03FF FFFF Unknown
  53.  
  54. 0x0400 0000 to 0x0400 FFFF SP registers:
  55. -----------------------------------------
  56. SP_BASE_REG - 0x04040000
  57.  
  58. 0x0400 0000 to 0x0400 0FFF SP_DMEM read/write
  59. 0x0400 1000 to 0x0400 1FFF SP_IMEM read/write
  60. 0x0400 2000 to 0x0403 FFFF Unused
  61. 0x0404 0000 to 0x0404 0003 SP_MEM_ADDR_REG
  62. Master, SP memory address
  63. (RW): [11:0] DMEM/IMEM address
  64. [12] 0=DMEM,1=IMEM
  65. 0x0404 0004 to 0x0404 0007 SP_DRAM_ADDR_REG
  66. Slave, SP DRAM DMA address
  67. (RW): [23:0] RDRAM address
  68. 0x0404 0008 to 0x0404 000B SP_RD_LEN_REG
  69. SP read DMA length
  70. (RW): [11:0] length
  71. [19:12] count
  72. [31:20] skip
  73. direction: I/DMEM <- RDRAM
  74. 0x0404 000C to 0x0404 000F SP_WR_LEN_REG
  75. SP write DMA length
  76. (RW): [11:0] length
  77. [19:12] count
  78. [31:20] skip
  79. direction: I/DMEM to RDRAM
  80. 0x0404 0010 to 0x0404 0013 SP_STATUS_REG
  81. SP status
  82. (W): [0] clear halt (R): [0] halt
  83. [1] set halt [1] broke
  84. [2] clear broke [2] dma busy
  85. [3] clear intr [3] dma full
  86. [4] set intr [4] io full
  87. [5] clear sstep [5] single step
  88. [6] set sstep [6] interrupt on break
  89. [7] clear intr on break [7] signal 0 set
  90. [8] set intr on break [8] signal 1 set
  91. [9] clear signal 0 [9] signal 2 set
  92. [10] set signal 0 [10] signal 3 set
  93. [11] clear signal 1 [11] signal 4 set
  94. [12] set signal 1 [12] signal 5 set
  95. [13] clear signal 2 [13] signal 6 set
  96. [14] set signal 2 [14] signal 7 set
  97. [15] clear signal 3
  98. [16] set signal 3
  99. [17] clear signal 4
  100. [18] set signal 4
  101. [19] clear signal 5
  102. [20] set signal 5
  103. [21] clear signal 6
  104. [22] set signal 6
  105. [23] clear signal 7
  106. [24] set signal 7
  107. 0x0404 0014 to 0x0404 0017 SP_DMA_FULL_REG
  108. SP DMA full
  109. (R): [0] valid bit
  110. dma full
  111. 0x0404 0018 to 0x0404 001B SP_DMA_BUSY_REG
  112. SP DMA busy
  113. (R): [0] valid bit
  114. dma busy
  115. 0x0404 001C to 0x0404 001F SP_SEMAPHORE_REG
  116. SP semaphore
  117. (R): [0] semaphore flag (set on read)
  118. (W): [] clear semaphore flag
  119. 0x0404 0020 to 0x0407 FFFF Unused
  120. 0x0408 0000 to 0x0408 0003 SP_PC_REG
  121. SP PC
  122. (RW): [11:0] program counter
  123. 0x0408 0004 to 0x0408 0007 SP_IBIST_REG
  124. SP IMEM BIST REG
  125. (W): [0] BIST check (R): [0] BIST check
  126. [1] BIST go [1] BIST go
  127. [2] BIST clear [2] BIST done
  128. [6:3] BIST fail
  129. 0x0408 0008 to 0x040F FFFF Unused
  130.  
  131. 0x0410 0000 to 0x041F FFFF DP command registers:
  132. -------------------------------------------------
  133. DPC_BASE_REG - 0x04100000
  134.  
  135. 0x0410 0000 to 0x0410 0003 DPC_START_REG
  136. DP CMD DMA start
  137. (RW): [23:0] DMEM/RDRAM start address
  138. 0x0410 0004 to 0x0410 0007 DPC_END_REG
  139. DP CMD DMA end
  140. (RW): [23:0] DMEM/RDRAM end address
  141. 0x0410 0008 to 0x0410 000B DPC_CURRENT_REG
  142. DP CMD DMA end
  143. (R): [23:0] DMEM/RDRAM current address
  144. 0x0410 000C to 0x0410 000F DPC_STATUS_REG
  145. DP CMD status
  146. (W): [0] clear xbus_dmem_dma (R): [0] xbus_dmem_dma
  147. [1] set xbus_dmem_dma [1] freeze
  148. [2] clear freeze [2] flush
  149. [3] set freeze [3] start gclk
  150. [4] clear flush [4] tmem busy
  151. [5] set flush [5] pipe busy
  152. [6] clear tmem ctr [6] cmd busy
  153. [7] clear pipe ctr [7] cbuf ready
  154. [8] clear cmd ctr [8] dma busy
  155. [9] clear clock ctr [9] end valid
  156. [10] start valid
  157. 0x0410 0010 to 0x0410 0013 DPC_CLOCK_REG
  158. DP clock counter
  159. (R): [23:0] clock counter
  160. 0x0410 0014 to 0x0410 0017 DPC_BUFBUSY_REG
  161. DP buffer busy counter
  162. (R): [23:0] clock counter
  163. 0x0410 0018 to 0x0410 001B DPC_PIPEBUSY_REG
  164. DP pipe busy counter
  165. (R): [23:0] clock counter
  166. 0x0410 001C to 0x0410 001F DPC_TMEM_REG
  167. DP TMEM load counter
  168. (R): [23:0] clock counter
  169. 0x0410 0020 to 0x041F FFFF Unused
  170.  
  171. 0x0420 0000 to 0x042F FFFF DP span registers:
  172. ----------------------------------------------
  173. DPS_BASE_REG - 0x04200000
  174.  
  175. 0x0420 0000 to 0x0420 0003 DPS_TBIST_REG
  176. DP tmem bist
  177. (W): [0] BIST check (R): [0] BIST check
  178. [1] BIST go [1] BIST go
  179. [2] BIST clear [2] BIST done
  180. [10:3] BIST fail
  181. 0x0420 0004 to 0x0420 0007 DPS_TEST_MODE_REG
  182. DP span test mode
  183. (RW): [0] Span buffer test access enable
  184. 0x0420 0008 to 0x0420 000B DPS_BUFTEST_ADDR_REG
  185. DP span buffer test address
  186. (RW): [6:0] bits
  187. 0x0420 000C to 0x0420 000F DPS_BUFTEST_DATA_REG
  188. DP span buffer test data
  189. (RW): [31:0] span buffer data
  190. 0x0420 0010 to 0x042F FFFF Unused
  191.  
  192. 0x0430 0000 to 0x043F FFFF MIPS interface (MI) registers:
  193. ----------------------------------------------------------
  194. MI_BASE_REG - 0x04300000
  195.  
  196. 0x0430 0000 to 0x0430 0003 MI_INIT_MODE_REG or MI_MODE_REG
  197. MI init mode
  198. (W): [6:0] init length (R): [6:0] init length
  199. [7] clear init mode [7] init mode
  200. [8] set init mode [8] ebus test mode
  201. [9/10] clr/set ebus test mode [9] RDRAM reg mode
  202. [11] clear DP interrupt
  203. [12] clear RDRAM reg
  204. [13] set RDRAM reg mode
  205. 0x0430 0004 to 0x0430 0007 MI_VERSION_REG or MI_NOOP_REG
  206. MI version
  207. (R): [7:0] io
  208. [15:8] rac
  209. [23:16] rdp
  210. [31:24] rsp
  211. 0x0430 0008 to 0x0430 000B MI_INTR_REG
  212. MI interrupt
  213. (R): [0] SP intr
  214. [1] SI intr
  215. [2] AI intr
  216. [3] VI intr
  217. [4] PI intr
  218. [5] DP intr
  219. 0x0430 000C to 0x0430 000F MI_INTR_MASK_REG
  220. MI interrupt mask
  221. (W): [0/1] clear/set SP mask (R): [0] SP intr mask
  222. [2/3] clear/set SI mask [1] SI intr mask
  223. [4/5] clear/set AI mask [2] AI intr mask
  224. [6/7] clear/set VI mask [3] VI intr mask
  225. [8/9] clear/set PI mask [4] PI intr mask
  226. [10/11] clear/set DP mask [5] DP intr mask
  227. 0x0430 0010 to 0x043F FFFF Unused
  228.  
  229. 0x0440 0000 to 0x044F FFFF Video interface (VI) registers:
  230. -----------------------------------------------------------
  231. VI_BASE_REG - 0x04400000
  232.  
  233. 0x0440 0000 to 0x0440 0003 VI_STATUS_REG or VI_CONTROL_REG
  234. VI status/control
  235. (RW): [1:0] type[1:0] (pixel size)
  236. 0: blank (no data, no sync)
  237. 1: reserved
  238. 2: 5/5/5/3 ("16" bit)
  239. 3: 8/8/8/8 (32 bit)
  240. [2] gamma_dither_enable (normally on, unless "special effect")
  241. [3] gamma_enable (normally on, unless MPEG/JPEG)
  242. [4] divot_enable (normally on if antialiased,
  243. unless decal lines)
  244. [5] reserved - always off
  245. [6] serrate (always on if interlaced, off if not)
  246. [7] reserved - diagnostics only
  247. [9:8] anti-alias (aa) mode[1:0]
  248. 0: aa & resamp (always fetch extra lines)
  249. 1: aa & resamp (fetch extra lines if needed)
  250. 2: resamp only (treat as all fully covered)
  251. 3: neither (replicate pixels, no interpolate)
  252. [11] reserved - diagnostics only
  253. [15:12] reserved
  254. 0x0440 0004 to 0x0440 0007 VI_ORIGIN_REG or VI_DRAM_ADDR_REG
  255. VI origin
  256. (RW): [23:0] frame buffer origin in bytes
  257. 0x0440 0008 to 0x0440 000B VI_WIDTH_REG or VI_H_WIDTH_REG
  258. VI width
  259. (RW): [11:0] frame buffer line width in pixels
  260. 0x0440 000C to 0x0440 000F VI_INTR_REG or VI_V_INTR_REG
  261. VI vertical intr
  262. (RW): [9:0] interrupt when current half-line = V_INTR
  263. 0x0440 0010 to 0x0440 0013 VI_CURRENT_REG or VI_V_CURRENT_LINE_REG
  264. VI current vertical line
  265. (RW): [9:0] current half line, sampled once per line (the lsb of
  266. V_CURRENT is constant within a field, and in
  267. interlaced modes gives the field number - which is
  268. constant for non-interlaced modes)
  269. - Writes clears interrupt line
  270. 0x0440 0014 to 0x0440 0017 VI_BURST_REG or VI_TIMING_REG
  271. VI video timing
  272. (RW): [7:0] horizontal sync width in pixels
  273. [15:8] color burst width in pixels
  274. [19:16] vertical sync width in half lines
  275. [29:20] start of color burst in pixels from h-sync
  276. 0x0440 0018 to 0x0440 001B VI_V_SYNC_REG
  277. VI vertical sync
  278. (RW): [9:0] number of half-lines per field
  279. 0x0440 001C to 0x0440 001F VI_H_SYNC_REG
  280. VI horizontal sync
  281. (RW): [11:0] total duration of a line in 1/4 pixel
  282. [20:16] a 5-bit leap pattern used for PAL only (h_sync_period)
  283. 0x0440 0020 to 0x0440 0023 VI_LEAP_REG or VI_H_SYNC_LEAP_REG
  284. VI horizontal sync leap
  285. (RW): [11:0] identical to h_sync_period
  286. [27:16] identical to h_sync_period
  287. 0x0440 0024 to 0x0440 0027 VI_H_START_REG or VI_H_VIDEO_REG
  288. VI horizontal video
  289. (RW): [9:0] end of active video in screen pixels
  290. [25:16] start of active video in screen pixels
  291. 0x0440 0028 to 0x0440 002B VI_V_START_REG or VI_V_VIDEO_REG
  292. VI vertical video
  293. (RW): [9:0] end of active video in screen half-lines
  294. [25:16] start of active video in screen half-lines
  295. 0x0440 002C to 0x0440 002F VI_V_BURST_REG
  296. VI vertical burst
  297. (RW): [9:0] end of color burst enable in half-lines
  298. [25:16] start of color burst enable in half-lines
  299. 0x0440 0030 to 0x0440 0033 VI_X_SCALE_REG
  300. VI x-scale
  301. (RW): [11:0] 1/horizontal scale up factor (2.10 format)
  302. [27:16] horizontal subpixel offset (2.10 format)
  303. 0x0440 0034 to 0x0440 0037 VI_Y_SCALE_REG
  304. VI y-scale
  305. (RW): [11:0] 1/vertical scale up factor (2.10 format)
  306. [27:16] vertical subpixel offset (2.10 format)
  307. 0x0440 0038 to 0x044F FFFF Unused
  308.  
  309. 0x0450 0000 to 0x045F FFFF Audio interface (AI) registers:
  310. -----------------------------------------------------------
  311. AI_BASE_REG - 0x04500000
  312.  
  313. 0x0450 0000 to 0x0450 0003 AI_DRAM_ADDR_REG
  314. AI DRAM address
  315. (W): [23:0] starting RDRAM address (8B-aligned)
  316. 0x0450 0004 to 0x0450 0007 AI_LEN_REG
  317. AI length
  318. (RW): [14:0] transfer length (v1.0) - Bottom 3 bits are ignored
  319. [17:0] transfer length (v2.0) - Bottom 3 bits are ignored
  320. 0x0450 0008 to 0x0450 000B AI_CONTROL_REG
  321. AI control
  322. (W): [0] DMA enable - if LSB == 1, DMA is enabled
  323. 0x0450 000C to 0x0450 000F AI_STATUS_REG
  324. AI status
  325. (R): [31]/[0] ai_full (addr & len buffer full)
  326. [30] ai_busy
  327. Note that a 1to0 transition in ai_full will set interrupt
  328. (W): clear audio interrupt
  329. 0x0450 0010 to 0x0450 0013 AI_DACRATE_REG
  330. AI DAC sample period register
  331. (W): [13:0] dac rate
  332. - vid_clock/(dperiod + 1) is the DAC sample rate
  333. - (dperiod + 1) >= 66 * (aclockhp + 1) must be true
  334. 0x0450 0014 to 0x0450 0017 AI_BITRATE_REG
  335. AI bit rate
  336. (W): [3:0] bit rate (abus clock half period register - aclockhp)
  337. - vid_clock/(2*(aclockhp + 1)) is the DAC clock rate
  338. - The abus clock stops if aclockhp is zero
  339. 0x0450 0018 to 0x045F FFFF Unused
  340.  
  341. 0x0460 0000 to 0x046F FFFF Peripheral interface (PI) registers:
  342. ----------------------------------------------------------------
  343. PI_BASE_REG - 0x04600000
  344.  
  345. 0x0460 0000 to 0x0460 0003 PI_DRAM_ADDR_REG
  346. PI DRAM address
  347. (RW): [23:0] starting RDRAM address
  348. 0x0460 0004 to 0x0460 0007 PI_CART_ADDR_REG
  349. PI pbus (cartridge) address
  350. (RW): [31:0] starting AD16 address
  351. 0x0460 0008 to 0x0460 000B PI_RD_LEN_REG
  352. PI read length
  353. (RW): [23:0] read data length
  354. 0x0460 000C to 0x0460 000F PI_WR_LEN_REG
  355. PI write length
  356. (RW): [23:0] write data length
  357. 0x0460 0010 to 0x0460 0013 PI_STATUS_REG
  358. PI status
  359. (R): [0] DMA busy (W): [0] reset controller
  360. [1] IO busy (and abort current op)
  361. [2] error [1] clear intr
  362. 0x0460 0014 to 0x0460 0017 PI_BSD_DOM1_LAT_REG or PI_DOMAIN1_REG
  363. PI dom1 latency
  364. (RW): [7:0] domain 1 device latency
  365. 0x0460 0018 to 0x0460 001B PI_BSD_DOM1_PWD_REG
  366. PI dom1 pulse width
  367. (RW): [7:0] domain 1 device R/W strobe pulse width
  368. 0x0460 001C to 0x0460 001F PI_BSD_DOM1_PGS_REG
  369. PI dom1 page size
  370. (RW): [3:0] domain 1 device page size
  371. 0x0460 0020 to 0x0460 0023 PI_BSD_DOM1_RLS_REG
  372. PI dom1 release
  373. (RW): [1:0] domain 1 device R/W release duration
  374. 0x0460 0024 to 0x0460 0027 PI_BSD_DOM2_LAT_REG or PI_DOMAIN2_REG
  375. PI dom2 latency
  376. (RW): [7:0] domain 2 device latency
  377. 0x0460 0028 to 0x0460 002B PI_BSD_DOM2_PWD_REG
  378. PI dom2 pulse width
  379. (RW): [7:0] domain 2 device R/W strobe pulse width
  380. 0x0460 002C to 0x0460 002F PI_BSD_DOM2_PGS_REG
  381. PI dom2 page size
  382. (RW): [3:0] domain 2 device page size
  383. 0x0460 0030 to 0x0460 0033 PI_BSD_DOM2_RLS_REG
  384. PI dom2 release
  385. (RW): [1:0] domain 2 device R/W release duration
  386. 0x0460 0034 to 0x046F FFFF Unused
  387.  
  388. 0x0470 0000 to 0x047F FFFF RDRAM interface (RI) registers:
  389. -----------------------------------------------------------
  390. RI_BASE_REG - 0x04700000
  391.  
  392. 0x0470 0000 to 0x0470 0003 RI_MODE_REG
  393. RI mode
  394. (RW): [1:0] operating mode
  395. [2] stop T active
  396. [3] stop R active
  397. 0x0470 0004 to 0x0470 0007 RI_CONFIG_REG
  398. RI config
  399. (RW): [5:0] current control input
  400. [6] current control enable
  401. 0x0470 0008 to 0x0470 000B RI_CURRENT_LOAD_REG
  402. RI current load
  403. (W): [] any write updates current control register
  404. 0x0470 000C to 0x0470 000F RI_SELECT_REG
  405. RI select
  406. (RW): [2:0] receive select
  407. [2:0] transmit select
  408. 0x0470 0010 to 0x0470 0013 RI_REFRESH_REG or RI_COUNT_REG
  409. RI refresh
  410. (RW): [7:0] clean refresh delay
  411. [15:8] dirty refresh delay
  412. [16] refresh bank
  413. [17] refresh enable
  414. [18] refresh optimize
  415. 0x0470 0014 to 0x0470 0017 RI_LATENCY_REG
  416. RI latency
  417. (RW): [3:0] DMA latency/overlap
  418. 0x0470 0018 to 0x0470 001B RI_RERROR_REG
  419. RI error
  420. (R): [0] nack error
  421. [1] ack error
  422. 0x0470 001C to 0x0470 001F RI_WERROR_REG
  423. RI error
  424. (W): [] any write clears all error bits
  425. 0x0470 0020 to 0x047F FFFF Unused
  426.  
  427. 0x0480 0000 to 0x048F FFFF Serial interface (SI) registers:
  428. ------------------------------------------------------------
  429. SI_BASE_REG - 0x04800000
  430.  
  431. 0x0480 0000 to 0x0480 0003 SI_DRAM_ADDR_REG
  432. SI DRAM address
  433. (R/W): [23:0] starting RDRAM address
  434. 0x0480 0004 to 0x0480 0007 SI_PIF_ADDR_RD64B_REG
  435. SI address read 64B
  436. (W): [] any write causes a 64B DMA write
  437. 0x0480 0008 to 0x0480 000B Reserved
  438. 0x0480 000C to 0x0480 000F Reserved
  439. 0x0480 0010 to 0x0480 0013 SI_PIF_ADDR_WR64B_REG
  440. SI address write 64B
  441. (W): [] any write causes a 64B DMA read
  442. 0x0480 0014 to 0x0480 0017 Reserved
  443. 0x0480 0018 to 0x0480 001B SI_STATUS_REG
  444. SI status
  445. (W): [] any write clears interrupt
  446. (R): [0] DMA busy
  447. [1] IO read busy
  448. [2] reserved
  449. [3] DMA error
  450. [12] interrupt
  451. 0x0480 001C to 0x048F FFFF Unused
  452.  
  453.  
  454. Unused:
  455. -------
  456. 0x0490 0000 to 0x04FF FFFF Unused
  457.  
  458. Cartridge Domain 2(Address 1): 64DD ASIC Registers
  459. ------------------------------
  460. 0x0500 0000 to 0x05FF FFFF Cartridge Domain 2
  461. 0x0500 0000 to 0x0500 03FF C2 Buffer
  462. 0x0500 0400 to 0x0500 04FF Sector Data (0x80 bytes at a time)
  463. 0x0500 0500 Leo data
  464. 0x0500 0504 ???
  465. 0x0500 0508 DD status (R), commands (w)
  466. 0x0500 050C Current track
  467. 0x0500 0510 Transfer Buffer status (R), buffer control (w) register
  468. 0x0500 0514 Sector error
  469. 0x0500 0518 Sequence Status
  470. 0x0500 051C Sequence Control
  471. 0x0500 0520 Leo reset
  472. 0x0500 0528 host secbyte
  473. 0x0500 0530 secbyte
  474. 0x0500 0540 Leo Attrib
  475. 0x0500 0580 to 0x0500 05BF RAM sequence data
  476.  
  477. Cartridge Domain 1(Address 1): Other Devices
  478. ------------------------------
  479. 0x0600 0000 to 0x07FF FFFF Cartridge Domain 1
  480. 0x0600 0000 to 0x0609 FFFF 64DD IPL ROM
  481. 0x060A 0000 to 0x0613 FFFF 64DD IPL Font Data
  482. 0x0614 0000 to 0x063F FFFF 64DD IPL Sound Data
  483.  
  484. 0x0800 0000 to 0x0FFF FFFF Cartridge Domain 2
  485. SRAM / FLASHram
  486.  
  487. Cartridge Domain 1(Address 2): Inserted Cartridge or Development Board
  488. ------------------------------
  489. 0x1000 0000 to 0x1000 003F ROM header:
  490. ---------------------------------------
  491. 0x1000 0000 initial PI_BSD_DOM1 REG settings
  492. 80000000 indicator for endianess
  493. 00F00000 initial PI_BSD_DOM1_RLS_REG
  494. 000F0000 initial PI_BSD_DOM1_PGS_REG
  495. 0000FF00 initial PI_BSD_DOM1_PWD_REG
  496. 000000FF initial PI_BSD_DOM1_LAT_REG
  497. 0x1000 0004 to 0x1000 0007 Clock Rate
  498. FFFFFFF0 ClockRate
  499. 0000000F
  500. 0x1000 0008 to 0x1000 000B Boot address offset
  501. 0x1000 000C to 0x1000 000F Release offset
  502. 0x1000 0010 to 0x1000 0013 CRC1
  503. 0x1000 0014 to 0x1000 0017 CRC2
  504. 0x1000 0018 to 0x1000 001F Unused
  505. 0x1000 0020 to 0x1000 0033 Image name
  506. 0x1000 0034 to 0x1000 003A Unused
  507. 0x1000 003B Manufacturer ID (Format)
  508. 0x1000 003C to 0x1000 003D Cartridge ID
  509. 0x1000 003E Country code
  510. 0x1000 003F Version (00 = 1.0, 15 = 2.5)
  511.  
  512. 0x1000 0040 to 0x1000 0B6F RAMROM_BOOTSTRAP_OFFSET
  513. 0x1000 0B70 to 0x1000 0FEF RAMROM_FONTDATA_OFFSET
  514. 0x1000 0FF0 to 0x1000 0FFF Unused
  515.  
  516. (Normal carts are bulk data. Below refers to development hardware)
  517. 0x1000 1000 to 0x10FF 9FFF RAMROM_GAME_OFFSET
  518. 0x10FF A000 to 0x10FF AFFF RAMROM_APP_READ_ADDR
  519. 0x10FF B000 to 0x10FF BFFF RAMROM_APP_WRITE_ADDR
  520. 0x10FF C000 to 0x10FF CFFF RAMROM_RMON_READ_ADDR
  521. 0x10FF D000 to 0x10FF DFFF RAMROM_RMON_WRITE_ADDR
  522. 0x10FF E000 to 0x10FF EFFF RAMROM_PRINTF_ADDR
  523. 0x10FF F000 to 0x10FF FFFF RAMROM_LOG_ADDR
  524. 0x1100 0000 to 0x17FF FFFF Unused
  525. 0x1800 0000 to 0x1800 0003 GIO Interrupt Register (R)
  526. 0x1800 0004 to 0x1800 03FF Unused
  527. 0x1800 0400 to 0x1800 0403 GIO Sync Register (R/W)
  528. 0x1800 0404 to 0x1800 07FF Unused
  529. 0x1800 0800 to 0x1800 0803 Cartridge interrupt Register (R)
  530. 0x1800 0804 to 0x1F39 FFFF Unused
  531.  
  532. 0x1800 0000 to 0x187F FFFF Modem Cartridge:
  533. --------------------------------------------
  534. 0x1800 0000 to 0x1800 003F Header
  535. 0x1800 0040 to 0x1809 09EF ELF1
  536. 0x1810 0000 to 0x1819 4273 ELF2
  537. 0x1820 0000 to 0x1829 0E27 ELF3
  538.  
  539. PIF Boot ROM: (occluded after boot)
  540. -------------
  541. 0x1FC0 0000 PIF_ROM_START
  542. 0x1FC0 07BF PIF_ROM_END
  543.  
  544. PIF RAM:
  545. ---------------------
  546. 0x1FC0 07C0 PIF_RAM_START
  547. 0x1FC0 07FF PIF_RAM_END
  548.  
  549. Reserved:
  550. ---------
  551. 0x1FC0 0800 to 0x1FCF FFFF Reserved
  552.  
  553. Cartridge Domain 1(Address 3):
  554. ------------------------------
  555. 0x1FD0 0000 to 0x7FFF FFFF Reserved for other devices
  556.  
  557. 0x8000 0000 to 0xffff ffff external SysAD device
  558. -------------------------------------------------
  559. 0x8000 0000 to 0x9FFF FFFF kseg0 (Mirror of 0x0000 0000 to 0x1FFF FFFF)
  560. 0xA000 0000 to 0xBFFF FFFF kseg1 (Mirror of 0x0000 0000 to 0x1FFF FFFF)
  561. 0xC000 0000 to 0xDFFF FFFF ksseg (TLB mapped)
  562. 0xE000 0000 to 0xFFFF FFFF kseg3 (TLB mapped)
  563.  
  564. ***********************************************************************
  565. ***************************** REGISTERS *****************************
  566. ***********************************************************************
  567.  
  568. Main CPU registers:
  569. -------------------
  570. 00h = r0/reg0 08h = t0/reg8 10h = s0/reg16 18h = t8/reg24
  571. 01h = at/reg1 09h = t1/reg9 11h = s1/reg17 19h = t9/reg25
  572. 02h = v0/reg2 0Ah = t2/reg10 12h = s2/reg18 1Ah = k0/reg26
  573. 03h = v1/reg3 0Bh = t3/reg11 13h = s3/reg19 1Bh = k1/reg27
  574. 04h = a0/reg4 0Ch = t4/reg12 14h = s4/reg20 1Ch = gp/reg28
  575. 05h = a1/reg5 0Dh = t5/reg13 15h = s5/reg21 1Dh = sp/reg29
  576. 06h = a2/reg6 0Eh = t6/reg14 16h = s6/reg22 1Eh = s8/reg30
  577. 07h = a3/reg7 0Fh = t7/reg15 17h = s7/reg23 1Fh = ra/reg31
  578.  
  579. COP0 registers:
  580. ---------------
  581. 00h = Index 08h = BadVAddr 10h = Config 18h = *RESERVED*
  582. 01h = Random 09h = Count 11h = LLAddr 19h = *RESERVED*
  583. 02h = EntryLo0 0Ah = EntryHi 12h = WatchLo 1Ah = PErr
  584. 03h = EntryLo1 0Bh = Compare 13h = WatchHi 1Bh = CacheErr
  585. 04h = Context 0Ch = Status 14h = XContext 1Ch = TagLo
  586. 05h = PageMask 0Dh = Cause 15h = *RESERVED* 1Dh = TagHi
  587. 06h = Wired 0Eh = EPC 16h = *RESERVED* 1Eh = ErrorEPC
  588. 07h = *RESERVED* 0Fh = PRevID 17h = *RESERVED* 1Fh = *RESERVED*
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