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  1. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;0.�!,K��х��}���с0 1
  2. bl2_stage_init 0x81
  3. hw id: 0x0000 - pwm id 0x01
  4. bl2_stage_init 0xc1
  5. bl2_stage_init 0x02
  6.  
  7. L0:00000000
  8. L1:20000703
  9. L2:00008067
  10. L3:14000000
  11. B2:00402000
  12. B1:e0f83180
  13.  
  14. TE: 206888
  15.  
  16. BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
  17.  
  18. Board ID = 8
  19. Set A53 clk to 24M
  20. Set A73 clk to 24M
  21. Set clk81 to 24M
  22. A53 clk: 1200 MHz
  23. A73 clk: 1200 MHz
  24. CLK81: 166.6M
  25. smccc: 00037005
  26. eMMC boot @ 0
  27. sw8 s
  28. DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
  29. board id: 8
  30. Load FIP HDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
  31. fw parse done
  32. Load ddrfw from eMMC, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0
  33. Load ddrfw from eMMC, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0
  34. PIEI prepare done
  35. fastboot data load
  36. 00000000
  37. emmc switch 1 ok
  38. 00000000
  39. emmc switch 2 ok
  40. fastboot data verify
  41. verify result: 265
  42. Cfg max: 4, cur: 1. Board id: 255. Force loop cfg
  43. LPDDR4 probe
  44. ddr clk to 1608MHz
  45. Load ddrfw from eMMC, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0
  46. 00000000
  47. emmc switch 0 ok
  48.  
  49. dmc_version 0001
  50. Check phy result
  51. INFO : End of CA training
  52. INFO : End of initialization
  53. INFO : Training has run successfully!
  54. Check phy result
  55. INFO : End of initialization
  56. INFO : End of read enable training
  57. INFO : End of fine write leveling
  58. INFO : End of Write leveling coarse delay
  59. INFO : Training has run successfully!
  60. Check phy result
  61. INFO : End of initialization
  62. INFO : End of read dq deskew training
  63. INFO : End of MPR read delay center optimization
  64. INFO : End of write delay center optimization
  65. INFO : End of read delay center optimization
  66. INFO : End of max read latency training
  67. INFO : Training has run successfully!
  68. 1D training succeed
  69. Load ddrfw from eMMC, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0
  70. Check phy result
  71. INFO : End of initialization
  72. INFO : End of 2D read delay Voltage center optimization
  73. INFO : End of 2D read delay Voltage center optimization
  74. INFO : End of 2D write delay Voltage center optimization
  75. INFO : End of 2D write delay Voltage center optimization
  76. INFO : Training has run successfully!
  77.  
  78. channel==0
  79. RxClkDly_Margin_A0==87 ps 9
  80. TxDqDly_Margin_A0==106 ps 11
  81. RxClkDly_Margin_A1==97 ps 10
  82. TxDqDly_Margin_A1==106 ps 11
  83. TrainedVREFDQ_A0==26
  84. TrainedVREFDQ_A1==26
  85. VrefDac_Margin_A0==27
  86. DeviceVref_Margin_A0==26
  87. VrefDac_Margin_A1==29
  88. DeviceVref_Margin_A1==26
  89.  
  90.  
  91. channel==1
  92. RxClkDly_Margin_A0==97 ps 10
  93. TxDqDly_Margin_A0==106 ps 11
  94. RxClkDly_Margin_A1==97 ps 10
  95. TxDqDly_Margin_A1==106 ps 11
  96. TrainedVREFDQ_A0==24
  97. TrainedVREFDQ_A1==24
  98. VrefDac_Margin_A0==27
  99. DeviceVref_Margin_A0==24
  100. VrefDac_Margin_A1==29
  101. DeviceVref_Margin_A1==24
  102.  
  103. dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  104.  
  105. soc_vref_reg_value 0x 00000026 00000028 00000028 00000028 00000027 00000027 00000027 002
  106. 2D training succeed
  107. aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
  108. auto size-- 65535DDR cs0 size: 2048MB
  109. DDR cs1 size: 2048MB
  110. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  111. cs0 DataBus test pass
  112. cs1 DataBus test pass
  113. cs0 AddrBus test pass
  114. cs1 AddrBus test pass
  115.  
  116. 100bdlr_step_size ps== 409
  117. result report
  118. boot times 0Enable ddr reg access
  119. 00000000
  120. emmc switch 3 ok
  121. Authentication key not yet programmed
  122. get rpmb counter error 0x00000007
  123. 00000000
  124. emmc switch 0 ok
  125. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  126. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x000dc000, part: 0
  127. 0.0;M3 CHK:0;cm4_sp_mode 0
  128. MVN_1=0x00000000
  129. MVN_2=0x00000000
  130. [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
  131. OPS=0x10
  132. ring efuse init
  133. chipver efuse init
  134. 29 0b 10 00 01 10 20 00 00 01 37 30 4e 42 4e 50
  135. [0.018960 Inits done]
  136. secure task start!
  137. high task start!
  138. low task start!
  139. run into bl31
  140. NOTICE: BL31: v1.3(release):4fc40b1
  141. NOTICE: BL31: Built : 15:58:17, May 22 2019
  142. NOTICE: BL31: G12A normal boot!
  143. NOTICE: BL31: BL33 decompress pass
  144. ERROR: Error initializing runtime service opteed_fast
  145.  
  146.  
  147. U-Boot 2015.01-g4752efb (Mar 19 2020 - 11:49:51)
  148.  
  149. DRAM: 3.8 GiB
  150. Relocation Offset is: d6e22000
  151. spi_post_bind(spifc): req_seq = 0
  152. register usb cfg[0][1] = 00000000d7f28538
  153. aml_i2c_init_port init regs for 0
  154. NAND: get_sys_clk_rate_mtd() 290, clock setting 200!
  155. NAND device id: 0 9f ff ff ff ff
  156. No NAND device found!!!
  157. nand init failed: -6
  158. get_sys_clk_rate_mtd() 290, clock setting 200!
  159. NAND device id: 0 9f ff ff ff ff
  160. No NAND device found!!!
  161. nand init failed: -6
  162. MMC: aml_priv->desc_buf = 0x00000000d3e12a70
  163. aml_priv->desc_buf = 0x00000000d3e14db0
  164. SDIO Port B: 0, SDIO Port C: 1
  165. co-phase 0x3, tx-dly 0, clock 400000
  166. co-phase 0x3, tx-dly 0, clock 400000
  167. co-phase 0x3, tx-dly 0, clock 400000
  168. emmc/sd response timeout, cmd8, status=0x3ff2800
  169. emmc/sd response timeout, cmd55, status=0x3ff2800
  170. co-phase 0x3, tx-dly 0, clock 400000
  171. co-phase 0x1, tx-dly 0, clock 40000000
  172. aml_sd_retry_refix[983]:delay = 0x0,gadjust =0x2000
  173. [mmc_startup] mmc refix success
  174. init_part() 297: PART_TYPE_AML
  175. [mmc_init] mmc init success
  176. start dts,buffer=00000000d3e17620,dt_addr=00000000d3e17620
  177. get_partition_from_dts() 91: ret 0
  178. parts: 17
  179. 00: logo 0000000000800000 1
  180. 01: recovery 0000000001800000 1
  181. 02: misc 0000000000800000 1
  182. 03: dtbo 0000000000800000 1
  183. 04: cri_data 0000000000800000 2
  184. 05: param 0000000001000000 2
  185. 06: boot 0000000001000000 1
  186. set has_boot_slot = 0
  187. 07: rsv 0000000001000000 1
  188. 08: metadata 0000000001000000 1
  189. 09: vbmeta 0000000000200000 1
  190. 10: tee 0000000002000000 1
  191. 11: vendor 0000000014000000 1
  192. 12: odm 0000000008000000 1
  193. 13: system 0000000050000000 1
  194. 14: product 0000000008000000 1
  195. 15: cache 0000000046000000 2
  196. 16: data ffffffffffffffff 4
  197. init_part() 297: PART_TYPE_AML
  198. eMMC/TSD partition table have been checked OK!
  199. crc32_s:0x1577dad == storage crc_pattern:0x1577dad!!!
  200. crc32_s:0xee152b83 == storage crc_pattern:0xee152b83!!!
  201. crc32_s:0x79f50f07 == storage crc_pattern:0x79f50f07!!!
  202. mmc env offset: 0x4d400000
  203. In: serial
  204. Out: serial
  205. Err: serial
  206. reboot_mode=cold_boot
  207. [store]To run cmd[emmc dtb_read 0x1000000 0x40000]
  208. _verify_dtb_checksum()-3477: calc 58267ef1, store 0
  209. update_dtb_info()-3585: cpy 1 is not valid
  210. _verify_dtb_checksum()-3477: calc 58267ef1, store 0
  211. update_dtb_info()-3585: cpy 0 is not valid
  212. dtb_read()-3694: total valid 0
  213. emmc - EMMC sub system
  214.  
  215. Usage:
  216. emmc dtb_read addr size
  217. emmc dtb_write addr size
  218. emmc erase dtb
  219. emmc erase key
  220. emmc fastboot_read addr size
  221. emmc fastboot_write addr size
  222.  
  223. aml_i2c_init_port init regs for 0
  224. fusb302_init: Device ID: 0x91
  225. CC connected in 0 as UFP
  226. fusb302 detect chip.port_num = 0
  227. amlkey_init() enter!
  228. [EFUSE_MSG]keynum is 1
  229. vpu: clk_level in dts: 7
  230. vpu: vpu_power_on
  231. vpu: set clk: 666667000Hz, readback: 666666667Hz(0x100)
  232. vpu: vpu_module_init_config
  233. vpp: vpp_init
  234. vpp: vpp osd2 matrix rgb2yuv..............
  235. cvbs: cpuid:0x29
  236. LCD_RESET PIN: 0
  237. lcd: detect mode: tablet, key_valid: 0
  238. lcd: detect lcd_clk_path: 1
  239. lcd: failed to get lcd_cpu_gpio_names
  240. lcd: load config from dts
  241. lcd: pinctrl_version: 2
  242. lcd: use panel_type=lcd_1
  243. lcd: bl: pinctrl_version: 2
  244. lcd: bl: name: backlight_pwm, method: 1
  245. lcd: bl: pwm_reg=0x00800002
  246. lcd: error: gpio: wrong name invalid
  247. lcd: bl: aml_bl_power_ctrl: 0
  248. Net: dwmac.ff3f0000amlkey_init() enter!
  249. amlkey_init() 71: already init!
  250. [EFUSE_MSG]keynum is 1
  251. MACADDR:02:00:00:20:10:01(from chipid)
  252.  
  253. CONFIG_AVB2: null
  254. Start read misc partition datas!
  255. info->magic =
  256. info->version_major = 1
  257. info->version_minor = 0
  258. info->slots[0].priority = 15
  259. info->slots[0].tries_remaining = 7
  260. info->slots[0].successful_boot = 0
  261. info->slots[1].priority = 14
  262. info->slots[1].tries_remaining = 7
  263. info->slots[1].successful_boot = 0
  264. info->crc32 = -1075449479
  265. active slot = 0
  266.  
  267. wipe_data=successful
  268. wipe_cache=successful
  269. upgrade_step=2
  270. reboot_mode:::: cold_boot
  271.  
  272.  
  273. lcd: error: outputmode[1080p60hz] is not support
  274. hpd_state=0
  275. edid preferred_mode is <NULL>[0]
  276. hdr mode is 0
  277. dv mode is ver:0 len: 0
  278. hdr10+ mode is 0
  279. [OSD]load fb addr from dts:/meson-fb
  280. [OSD]set initrd_high: 0x7f800000
  281. [OSD]fb_addr for logo: 0x7f800000
  282. [OSD]load fb addr from dts:/meson-fb
  283. [OSD]fb_addr for logo: 0x7f800000
  284. [CANVAS]canvas init
  285. [CANVAS]addr=0x7fbf4800 width=2176, height=3840
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