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Jan 11th, 2019
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  1. // Copyright 2017 ETH Zurich and University of Bologna.
  2. // Copyright and related rights are licensed under the Solderpad Hardware
  3. // License, Version 0.51 (the "License"); you may not use this file except in
  4. // compliance with the License. You may obtain a copy of the License at
  5. // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
  6. // or agreed to in writing, software, hardware and materials distributed under
  7. // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
  8. // CONDITIONS OF ANY KIND, either express or implied. See the License for the
  9. // specific language governing permissions and limitations under the License.
  10.  
  11. module cluster_clock_gating
  12. (
  13. input logic clk_i,
  14. input logic en_i,
  15. input logic test_en_i,
  16. output logic clk_o
  17. );
  18.  
  19. `ifdef PULP_FPGA_EMUL
  20. // no clock gates in FPGA flow
  21. assign clk_o = clk_i;
  22. `else
  23. logic clk_en;
  24.  
  25. always_latch
  26. begin
  27. if (clk_i == 1'b0)
  28. clk_en <= en_i | test_en_i;
  29. end
  30.  
  31. assign clk_o = clk_i & clk_en;
  32. `endif
  33.  
  34. endmodule // cluster_clock_gating
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