Non-functional sram led code

//////////
// Top menu
//////
    module top(clk, sw19, sw50, sw52, sw53, sw54, leds, write_address, write_data, write_enable, read_address, read_data, read_enable);

        //////////
        // Parameters
        //////
            // Input
            input wire            clk;
            input wire            sw19;
            input wire            sw50;
            input wire            sw52;
            input wire            sw53;
            input wire            sw54;

            // Output
            output wire [7:0]    leds;
            output wire [7:0]    write_address;
            output wire [7:0]    write_data;
            output wire          write_enable;
            output wire [7:0]    read_address;
            output wire [7:0]    read_data;
            output wire          read_enable;


        //////////
        // Local variables
        //////
            wire                 writing;
            reg                  mode;

            initial
            begin
                mode             = 1'b0;
            end


        //////////
        // Clock
        //////
            wire                 clk1;    // 10 MHz
            wire                 clkOk;
            my_pll    pll100 (.CLK(clk), .CLKOP(clk1), .LOCK(clkOk));


        //////////
        // Sub-clocks
        //////
            wire [31:0]          subclk1000_count;
            wire                 subclk1000;
            // 10 KHz clock
            subclock #(1000) clk_1000(clk1, subclk1000_count[31:0], subclk1000);

            wire [31:0]          subclk100_count;
            wire                 subclk100;
            // 100 KHz clock
            subclock #(100)  clk_100(clk1, subclk100_count[31:0], subclk100);


        //////////
        // Main loop
        //////
            // Reads buttons presses, displays the memory at that location
            led_switch         main  (subclk1000, sw19, sw50, sw52, sw53, sw54, leds, mode, read_address, read_data, read_enable, writing);

            // Used only at startup, where it writes data to the first 256 bytes of memory (00h..FFh)
            read_write_memory  rwm   (mode, subclk1000, subclk100, write_address, write_data, write_enable, read_address, read_data, read_enable, writing);

    endmodule


//////////
// LED switches
//////
    module led_switch(clk_1000, sw19, sw50, sw52, sw53, sw54, leds, mode, read_address, read_data, read_enable, writing);

        //////////
        // Parameters
        //////
            // Input
            input  wire         clk_1000;
            input  wire         sw19;
            input  wire         sw50;
            input  wire         sw52;
            input  wire         sw53;
            input  wire         sw54;
            input  wire         mode;
            input  wire[7:0]    read_address;
            input  wire[7:0]    read_data;
            input  wire         read_enable;
            input  wire         writing;

            // Output
            output reg [7:0]    leds;


        //////////
        // Switches up/down the address
        //////
            always @(posedge clk_1000)
            begin
                // Switch 4
                if (sw53 == 1'b0)
                begin
                    // Decrease address
                    // if address > 0x00
                end

                // Switch 5
                if (sw54 == 1'b0)
                begin
                    // Increase address
                    // if address < 0xff
                end

                // Display the value
                leds[7:0] <= read_data[7:0];
            end

    endmodule


//////////
// Sub-clock definition
//////
    module subclock(clk_in, count, clk_out);

        parameter            MAX = 10;
        input  wire          clk_in;
        output reg[31:0]     count;
        output reg           clk_out;

        // Initialize count to 0, and clock low
        initial
        begin
            count    = 32'b0;
            clk_out  = 1'b0;
        end

        // Based on input clock, cycle through
        always @(posedge clk_in)
        begin
            // Increase the count
            count <= count + 32'b1;

            // Once we reach our max, we're there
            if (count > MAX - 1)
            begin
                // Reset the count
                count <= 32'b0;

                // Flipi the clock out
                clk_out = ~clk_out;
            end
        end

    endmodule


//////////
// Read/write memory
//////
    module read_write_memory (mode, clk_slow, clk_fast, write_address, write_data, write_enable, read_address, read_data, read_enable, writing);

        //////////
        // Input/output
        //////
            input  wire         mode;
            input  wire         clk_slow;         // .001 main clock
            input  wire         clk_fast;         // .01 main clock

            input  wire[7:0]    read_address;     // Read info
            input  wire[7:0]    read_data;
            input  wire         read_enable;

            output wire[7:0]    write_address;    // Write info
            output wire[7:0]    write_data;
            output wire         write_enable;
            output reg          writing;          // Flag indicating we're still writing during the initial bootup



        //////////
        // Memory
        //////
            reg [7:0]           waddress;         // Write address
            reg [7:0]           wdata;            // Write data
            reg [7:0]           raddress;         // Read address

            reg                 wenable;
            reg                 renable;

            // Initialized values
            initial begin
                waddress        = 8'b_0000_0000;
                data            = 8'b_1111_1111;

                raddress        = 8'b_1000_0000;

                wenable         = 1'b0;
                renable         = 1'b0;
                writing         = 1'b1;
            end


        //////////
        // Pass-thru
        //////
            assign write_address = ((writing) ? waddress[7:0] : 8'bZZZZZZZZ);
            assign write_data    = ((writing) ? data[7:0]     : 8'bZZZZZZZZ);
            assign write_enable  = ((writing) ? wenable       : 1'bZ);


        //////////
        // Main
        //////
            // Turn off strobes
            always @(posedge clk_fast)
            begin
                if (wenable)    wenable <= 1'b0;        // Write enable
                if (renable)    renable <= 1'b0;        // Read enable
            end

            // Handle address and data
            always @(posedge clk_slow)
            begin
                if (writing == 1'b0)
                begin
                    // Reading
                    // ?? don't know what to do
                end
                else
                begin
                    // Writing
                    waddress[7:0]  <= waddress[7:0]  + 8'b1;        // Next address
                    data[7:0]      <= data[7:0]      - 8'b1;        // New data value

                    // Raise the write flags
                    wenable        <= 1'b1;
                    writing        <= ((waddress[7:0] == 8'b_1111_1111) ? 1'b0 : 1'b1);
                end
            end

    endmodule