task

module contTest;
parameter T = 10;
parameter X = 5;
parameter M = 3;
parameter N = 8;

reg clk = 1;
reg reset;

reg [M-1:0] addr_in;
reg [N-1:0] data_in;
reg rd_in;
reg wr_in;
wire busy;
wire [M-1:0] addr_resp;
wire [N-1:0] data_resp;
wire finish;

wire [M-1:0] mem_addr;
wire [N-1:0] mem_data;
wire mem_wr;
wire mem_rd;


always
    #(T/2) clk <= ~clk;

controller #(.T(T), .X(X), .M(M), .N(N))DUT(.clk(clk), .reset(reset), .addr_in(addr_in), .data_in(data_in),
                .wr_in(wr_in), .rd_in(rd_in), .busy(busy), .addr_resp(addr_resp), .data_resp(data_resp),
                .finish(finish), .mem_addr(mem_addr), .mem_data(mem_data), .mem_wr(mem_wr), .mem_rd(mem_rd));

mem  #(.T(T), .X(X), .M(M), .N(N))mem1(.addr(mem_addr), .data(mem_data), .clk(clk), .rd(mem_rd), .wr(mem_wr));

initial begin
    init;
    #T @(posedge clk)
    writeCnt('b011, 'b01101);
    #(6*T) @(posedge clk)
    writeCnt('b001, 'b01001);
    #(10*T) @(posedge clk)
    readCnt('b011);
end

task init;
    begin
        addr_in <= 'b0;
        data_in <= 'b1;
        rd_in <= 0;
        wr_in <= 0;
        reset <= 1;
        #(2*T) @(posedge clk)
        reset <= 0;
  end
endtask

task writeCnt(input [M-1:0] addrVal, input [N-1:0] dataVal);
  begin
    addr_in <= addrVal;
    data_in <= dataVal;
    wr_in <= 1;
    #(T) @(posedge clk)
    wr_in <= 0;
  end
endtask

task readCnt(input [M-1:0] addrVal);
  begin
    addr_in <= addrVal;
    rd_in <= 1;
    #(T) @(posedge clk)
    rd_in <= 0;
  end
endtask

endmodule