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-- Company:
-- Engineer:
--
-- Create Date:   10:42:52 04/12/2016
-- Design Name:
-- Module Name:   C:/Designs/Klimek_Wisniewski6/tb1.vhd
-- Project Name:  Klimek_Wisniewski6
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: cw6
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb1 IS
END tb1;

ARCHITECTURE behavior OF tb1 IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT cw6
    PORT(
         clk_i : IN  std_logic;
         led7_seg_o : OUT  std_logic_vector(7 downto 0);
         led7_an_o : OUT  std_logic_vector(3 downto 0);
         sw_i : IN  std_logic_vector(7 downto 0);
         btn_i : IN  std_logic_vector(3 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal clk_i : std_logic := '0';
   signal sw_i : std_logic_vector(7 downto 0) := (others => '0');
   signal btn_i : std_logic_vector(3 downto 0) := (others => '0');

 	--Outputs
   signal led7_seg_o : std_logic_vector(7 downto 0);
   signal led7_an_o : std_logic_vector(3 downto 0);

   -- Clock period definitions
   constant clk_i_period : time := 1ms;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
   uut: cw6 PORT MAP (
          clk_i => clk_i,
          led7_seg_o => led7_seg_o,
          led7_an_o => led7_an_o,
          sw_i => sw_i,
          btn_i => btn_i
        );

   -- Clock process definitions
   clk_i_process :process
   begin
		clk_i <= '0';
		wait for clk_i_period/2;
		clk_i <= '1';
		wait for clk_i_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100ms.
        wait for 10 ms;
		sw_i <= "11110011";
		wait for 5 ms;
		btn_i <= "1000";
		wait for 5 ms;
		btn_i <= "0000";
		wait for 10 ms;
		sw_i <= "11000001";
		  wait for 10 ms;
		sw_i <= "11110011";
		wait for 5 ms;
		btn_i <= "0001";
		wait for 5 ms;
		btn_i <= "0000";
		wait for 10 ms;




		wait for 50 ms;

      -- insert stimulus here

      wait;
   end process;

END;