F1C100s (Lichee Pi nano) clock memo

U-Boot 2018.01-05679-g013ca457fd (Dec 26 2019 - 18:18:28 +0900) Allwinner Technology

CPU:   Allwinner F Series (SUNIV)
Model: Lichee Pi Nano
DRAM:  32 MiB
MMC:   SUNXI SD/MMC: 0

(snip)

=> md 01c20000
01c20000: 90001000 00000000 00005514 00000000    .........U......

PLL_CPU_CTRL_REG(@0x01c20000): 0x90001000
	PLL_ENABLE(1:Enable)
	LOCK(1:Locked)
	PLL_OUT_EXT_DIV_P(00:/1)
	PLL_FACTOR_N(0x10:N=17)
	PLL_FACTOR_K(0x00:K=1)
	PLL_FACTOR_M(0x00:M=1)	==> CPU_PLL: (24MHz*17*1)/(1*1) = 408MHz

01c20010: 03006207 00000000 03004507 00000000    .b.......E......
01c20020: 90000c00 00000000 90041800 00000000    ................

PLL_DDR_CTRL_REG(@0x01c20020): 0x90000c00
	PLL_ENABLE(1:Enable)
	LOCK(1:Locked)
	PLL_FACTOR_N(0x0c:N=13)
	PLL_FACTOR_K(0x00:K=1)
	PLL_FACTOR_M(0x00:M=1)	==> DDR_PLL: (24MHz*13*1)/(1) = 312MHz

PLL_PERIPH_CTRL_REG(@0x01c20028): 0x90041800
	PLL_ENABLE(1:Enable)
	LOCK(1:Locked)
	PLL_24M_OUT_EN(1:Enable)
	PLL_24M_POST_DIV(00:/1)
	PLL_FACTOR_N(0x18:N=25)
	PLL_FACTOR_K(0x00:K=1)
	PLL_FACTOR_M(0x00:M=1)	==> PERIPH_PLL: (24MHz*25*1)/(1) = 600MHz

01c20030: 00000000 00000000 00000000 00000000    ................
01c20040: 00000000 00000000 00000000 00000000    ................
01c20050: 00020000 00003180 00000000 00000000    .....1..........

CPU_CLK_SRC_REG(@0x01c20050): 0x00020000
	CPU_CLK_SRC_SEL(10:PLL_CPU)
				==> CPU_CLK = CPU_PLL = 408MHz

AHB_APB_HLKC_CFG_REG(@0x01c20054): 0x00003180
	HCLKC_DIV(00:/1)	==> HCLK = CPUCLK / 1 = 408MHz
	AHB_CLK_SRC_SEL(11:PLL_PERIPH/AHB_PRE_DIV)
	APB_CLK_RATIO(01:/2)
	AHB_PRE_DIV(10:/3)
	AHB_CLK_DIV_RATIO(00:/1)
				==> AHB_CLK = PERIPH_PLL / (3*1) = 200MHz
				==> APB_CLK = AHB_CLK / 2 = 100MHz

01c20060: 00004100 00000000 00100000 00000000    .A..............
01c20070: 00000000 00000000 00000000 00000000    ................
01c20080: 00000000 00000000 8151000b 00000000    ..........Q.....

SDMMC0_CLK_REG(@0x01c20088): 0x8151000b
	SCLK_GATING(1:Clock is ON)
	CLK_SRC_SEL(01:PLL_PERIPH)
	SAMPLE_CLK_PHASE_CTR(5)
	CLK_DIV_RATIO_N(00:N=1)
	OUTPUT_CLK_PHASE_CTR(0)
	CLK_DIV_RATIO_M(0x0b:M=12)
				==> SDMMC0_CLK = PERIPH_PLL / (12*1) = 50MHz

01c20090: 00000000 00000000 00000000 00000000    ................
01c200a0: 00000000 00000000 00000000 00000000    ................
01c200b0: 00000000 00010000 00000000 00000000    ................
01c200c0: 00000000 00000000 00000000 00000000    ................
01c200d0: 00000000 00000000 00000000 00000000    ................
01c200e0: 00000000 00000000 00000000 00000000    ................
01c200f0: 00000000 00000000 00000000 00000000    ................
=>